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24#include "qemu/osdep.h"
25#include "hw/hw.h"
26#include "hw/timer/m48t59.h"
27#include "hw/i386/pc.h"
28#include "hw/char/serial.h"
29#include "hw/block/fdc.h"
30#include "net/net.h"
31#include "sysemu/sysemu.h"
32#include "hw/isa/isa.h"
33#include "hw/pci/pci.h"
34#include "hw/pci/pci_host.h"
35#include "hw/ppc/ppc.h"
36#include "hw/boards.h"
37#include "qemu/error-report.h"
38#include "qemu/log.h"
39#include "hw/ide.h"
40#include "hw/loader.h"
41#include "hw/timer/mc146818rtc.h"
42#include "hw/isa/pc87312.h"
43#include "sysemu/block-backend.h"
44#include "sysemu/arch_init.h"
45#include "sysemu/qtest.h"
46#include "exec/address-spaces.h"
47#include "trace.h"
48#include "elf.h"
49#include "qemu/cutils.h"
50
51
52#define MAX_CPUS 1
53
54#define MAX_IDE_BUS 2
55
56#define BIOS_SIZE (1024 * 1024)
57#define BIOS_FILENAME "ppc_rom.bin"
58#define KERNEL_LOAD_ADDR 0x01000000
59#define INITRD_LOAD_ADDR 0x01800000
60
61
62static const int ide_iobase[2] = { 0x1f0, 0x170 };
63static const int ide_iobase2[2] = { 0x3f6, 0x376 };
64static const int ide_irq[2] = { 13, 13 };
65
66#define NE2000_NB_MAX 6
67
68static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
69static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
70
71
72#define PPC_IO_BASE 0x80000000
73
74
75#if 0
76static struct {
77
78 uint32_t veni_devi;
79 uint32_t revi;
80
81 uint32_t gcsr;
82 uint32_t xcfr;
83 uint32_t ct32;
84 uint32_t mcsr;
85
86 uint32_t gprg[6];
87
88 uint32_t feen;
89 uint32_t fest;
90 uint32_t fema;
91 uint32_t fecl;
92 uint32_t eeen;
93 uint32_t eest;
94 uint32_t eecl;
95 uint32_t eeint;
96 uint32_t eemck0;
97 uint32_t eemck1;
98
99} XCSR;
100
101static void PPC_XCSR_writeb (void *opaque,
102 hwaddr addr, uint32_t value)
103{
104 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
105 value);
106}
107
108static void PPC_XCSR_writew (void *opaque,
109 hwaddr addr, uint32_t value)
110{
111 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
112 value);
113}
114
115static void PPC_XCSR_writel (void *opaque,
116 hwaddr addr, uint32_t value)
117{
118 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
119 value);
120}
121
122static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
123{
124 uint32_t retval = 0;
125
126 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
127 retval);
128
129 return retval;
130}
131
132static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
133{
134 uint32_t retval = 0;
135
136 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
137 retval);
138
139 return retval;
140}
141
142static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
143{
144 uint32_t retval = 0;
145
146 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
147 retval);
148
149 return retval;
150}
151
152static const MemoryRegionOps PPC_XCSR_ops = {
153 .old_mmio = {
154 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
155 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
156 },
157 .endianness = DEVICE_LITTLE_ENDIAN,
158};
159
160#endif
161
162
163typedef struct sysctrl_t {
164 qemu_irq reset_irq;
165 Nvram *nvram;
166 uint8_t state;
167 uint8_t syscontrol;
168 int contiguous_map;
169 qemu_irq contiguous_map_irq;
170 int endian;
171} sysctrl_t;
172
173enum {
174 STATE_HARDFILE = 0x01,
175};
176
177static sysctrl_t *sysctrl;
178
179static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
180{
181 sysctrl_t *sysctrl = opaque;
182
183 trace_prep_io_800_writeb(addr - PPC_IO_BASE, val);
184 switch (addr) {
185 case 0x0092:
186
187
188 if (val & 0x01) {
189 qemu_irq_raise(sysctrl->reset_irq);
190 } else {
191 qemu_irq_lower(sysctrl->reset_irq);
192 }
193
194 if (val & 0x02) {
195 sysctrl->endian = 1;
196 } else {
197 sysctrl->endian = 0;
198 }
199 break;
200 case 0x0800:
201
202 break;
203 case 0x0802:
204
205 break;
206 case 0x0803:
207
208 break;
209 case 0x0808:
210
211 if (val & 1)
212 sysctrl->state |= STATE_HARDFILE;
213 else
214 sysctrl->state &= ~STATE_HARDFILE;
215 break;
216 case 0x0810:
217
218 if (sysctrl->nvram != NULL) {
219 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
220 (k->toggle_lock)(sysctrl->nvram, 1);
221 }
222 break;
223 case 0x0812:
224
225 if (sysctrl->nvram != NULL) {
226 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
227 (k->toggle_lock)(sysctrl->nvram, 2);
228 }
229 break;
230 case 0x0814:
231
232
233 break;
234 case 0x081C:
235
236 sysctrl->syscontrol = val & 0x0F;
237 break;
238 case 0x0850:
239
240 sysctrl->contiguous_map = val & 0x01;
241 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
242 break;
243 default:
244 printf("ERROR: unaffected IO port write: %04" PRIx32
245 " => %02" PRIx32"\n", addr, val);
246 break;
247 }
248}
249
250static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
251{
252 sysctrl_t *sysctrl = opaque;
253 uint32_t retval = 0xFF;
254
255 switch (addr) {
256 case 0x0092:
257
258 retval = sysctrl->endian << 1;
259 break;
260 case 0x0800:
261
262 retval = 0xEF;
263 break;
264 case 0x0802:
265
266 retval = 0xAD;
267 break;
268 case 0x0803:
269
270 retval = 0xE0;
271 break;
272 case 0x080C:
273
274
275
276
277
278
279 retval = 0x3C;
280 break;
281 case 0x0810:
282
283 retval = 0x39;
284 break;
285 case 0x0814:
286
287 break;
288 case 0x0818:
289
290 retval = 0x00;
291 break;
292 case 0x081C:
293
294
295
296 retval = sysctrl->syscontrol;
297 break;
298 case 0x0823:
299
300 retval = 0x03;
301 break;
302 case 0x0850:
303
304 retval = sysctrl->contiguous_map;
305 break;
306 default:
307 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
308 break;
309 }
310 trace_prep_io_800_readb(addr - PPC_IO_BASE, retval);
311
312 return retval;
313}
314
315
316#define NVRAM_SIZE 0x2000
317
318static void ppc_prep_reset(void *opaque)
319{
320 PowerPCCPU *cpu = opaque;
321
322 cpu_reset(CPU(cpu));
323}
324
325static const MemoryRegionPortio prep_portio_list[] = {
326
327 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
328 { 0x0800, 0x52, 1,
329 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
330
331 { 0x0F00, 4, 1, .write = PPC_debug_write, },
332 PORTIO_END_OF_LIST(),
333};
334
335static PortioList prep_port_list;
336
337
338
339static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
340{
341 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
342 return (k->read)(nvram, addr);
343}
344
345static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
346{
347 NvramClass *k = NVRAM_GET_CLASS(sysctrl->nvram);
348 (k->write)(nvram, addr, val);
349}
350
351static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
352{
353 nvram_write(nvram, addr, value);
354}
355
356static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
357{
358 return nvram_read(nvram, addr);
359}
360
361static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
362{
363 nvram_write(nvram, addr, value >> 8);
364 nvram_write(nvram, addr + 1, value & 0xFF);
365}
366
367static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
368{
369 uint16_t tmp;
370
371 tmp = nvram_read(nvram, addr) << 8;
372 tmp |= nvram_read(nvram, addr + 1);
373
374 return tmp;
375}
376
377static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
378{
379 nvram_write(nvram, addr, value >> 24);
380 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
381 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
382 nvram_write(nvram, addr + 3, value & 0xFF);
383}
384
385static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
386 uint32_t max)
387{
388 int i;
389
390 for (i = 0; i < max && str[i] != '\0'; i++) {
391 nvram_write(nvram, addr + i, str[i]);
392 }
393 nvram_write(nvram, addr + i, str[i]);
394 nvram_write(nvram, addr + max - 1, '\0');
395}
396
397static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
398{
399 uint16_t tmp;
400 uint16_t pd, pd1, pd2;
401
402 tmp = prev >> 8;
403 pd = prev ^ value;
404 pd1 = pd & 0x000F;
405 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
406 tmp ^= (pd1 << 3) | (pd1 << 8);
407 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
408
409 return tmp;
410}
411
412static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
413{
414 uint32_t i;
415 uint16_t crc = 0xFFFF;
416 int odd;
417
418 odd = count & 1;
419 count &= ~1;
420 for (i = 0; i != count; i++) {
421 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
422 }
423 if (odd) {
424 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
425 }
426
427 return crc;
428}
429
430#define CMDLINE_ADDR 0x017ff000
431
432static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
433 const char *arch,
434 uint32_t RAM_size, int boot_device,
435 uint32_t kernel_image, uint32_t kernel_size,
436 const char *cmdline,
437 uint32_t initrd_image, uint32_t initrd_size,
438 uint32_t NVRAM_image,
439 int width, int height, int depth)
440{
441 uint16_t crc;
442
443
444 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
445 NVRAM_set_lword(nvram, 0x10, 0x00000002);
446 NVRAM_set_word(nvram, 0x14, NVRAM_size);
447 NVRAM_set_string(nvram, 0x20, arch, 16);
448 NVRAM_set_lword(nvram, 0x30, RAM_size);
449 NVRAM_set_byte(nvram, 0x34, boot_device);
450 NVRAM_set_lword(nvram, 0x38, kernel_image);
451 NVRAM_set_lword(nvram, 0x3C, kernel_size);
452 if (cmdline) {
453
454 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
455 cmdline);
456 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
457 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
458 } else {
459 NVRAM_set_lword(nvram, 0x40, 0);
460 NVRAM_set_lword(nvram, 0x44, 0);
461 }
462 NVRAM_set_lword(nvram, 0x48, initrd_image);
463 NVRAM_set_lword(nvram, 0x4C, initrd_size);
464 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
465
466 NVRAM_set_word(nvram, 0x54, width);
467 NVRAM_set_word(nvram, 0x56, height);
468 NVRAM_set_word(nvram, 0x58, depth);
469 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
470 NVRAM_set_word(nvram, 0xFC, crc);
471
472 return 0;
473}
474
475
476static void ppc_prep_init(MachineState *machine)
477{
478 ram_addr_t ram_size = machine->ram_size;
479 const char *kernel_filename = machine->kernel_filename;
480 const char *kernel_cmdline = machine->kernel_cmdline;
481 const char *initrd_filename = machine->initrd_filename;
482 const char *boot_device = machine->boot_order;
483 MemoryRegion *sysmem = get_system_memory();
484 PowerPCCPU *cpu = NULL;
485 CPUPPCState *env = NULL;
486 Nvram *m48t59;
487#if 0
488 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
489#endif
490 int linux_boot, i, nb_nics1;
491 MemoryRegion *ram = g_new(MemoryRegion, 1);
492 uint32_t kernel_base, initrd_base;
493 long kernel_size, initrd_size;
494 DeviceState *dev;
495 PCIHostState *pcihost;
496 PCIBus *pci_bus;
497 PCIDevice *pci;
498 ISABus *isa_bus;
499 ISADevice *isa;
500 int ppc_boot_device;
501 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
502
503 sysctrl = g_malloc0(sizeof(sysctrl_t));
504
505 linux_boot = (kernel_filename != NULL);
506
507
508 if (machine->cpu_model == NULL)
509 machine->cpu_model = "602";
510 for (i = 0; i < smp_cpus; i++) {
511 cpu = cpu_ppc_init(machine->cpu_model);
512 if (cpu == NULL) {
513 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
514 exit(1);
515 }
516 env = &cpu->env;
517
518 if (env->flags & POWERPC_FLAG_RTC_CLK) {
519
520 cpu_ppc_tb_init(env, 7812500UL);
521 } else {
522
523 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
524 }
525 qemu_register_reset(ppc_prep_reset, cpu);
526 }
527
528
529 memory_region_allocate_system_memory(ram, NULL, "ppc_prep.ram", ram_size);
530 memory_region_add_subregion(sysmem, 0, ram);
531
532 if (linux_boot) {
533 kernel_base = KERNEL_LOAD_ADDR;
534
535 kernel_size = load_image_targphys(kernel_filename, kernel_base,
536 ram_size - kernel_base);
537 if (kernel_size < 0) {
538 error_report("could not load kernel '%s'", kernel_filename);
539 exit(1);
540 }
541
542 if (initrd_filename) {
543 initrd_base = INITRD_LOAD_ADDR;
544 initrd_size = load_image_targphys(initrd_filename, initrd_base,
545 ram_size - initrd_base);
546 if (initrd_size < 0) {
547 error_report("could not load initial ram disk '%s'",
548 initrd_filename);
549 exit(1);
550 }
551 } else {
552 initrd_base = 0;
553 initrd_size = 0;
554 }
555 ppc_boot_device = 'm';
556 } else {
557 kernel_base = 0;
558 kernel_size = 0;
559 initrd_base = 0;
560 initrd_size = 0;
561 ppc_boot_device = '\0';
562
563 for (i = 0; boot_device[i] != '\0'; i++) {
564 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
565 ppc_boot_device = boot_device[i];
566 break;
567 }
568 }
569 if (ppc_boot_device == '\0') {
570 fprintf(stderr, "No valid boot device for Mac99 machine\n");
571 exit(1);
572 }
573 }
574
575 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
576 error_report("Only 6xx bus is supported on PREP machine");
577 exit(1);
578 }
579
580 dev = qdev_create(NULL, "raven-pcihost");
581 if (bios_name == NULL) {
582 bios_name = BIOS_FILENAME;
583 }
584 qdev_prop_set_string(dev, "bios-name", bios_name);
585 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
586 pcihost = PCI_HOST_BRIDGE(dev);
587 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
588 qdev_init_nofail(dev);
589 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
590 if (pci_bus == NULL) {
591 fprintf(stderr, "Couldn't create PCI host controller.\n");
592 exit(1);
593 }
594 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
595
596
597 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
598 cpu = POWERPC_CPU(first_cpu);
599 qdev_connect_gpio_out(&pci->qdev, 0,
600 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
601 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
602 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
603 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
604 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
605 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
606
607
608 isa = isa_create(isa_bus, TYPE_PC87312);
609 dev = DEVICE(isa);
610 qdev_prop_set_uint8(dev, "config", 13);
611 qdev_init_nofail(dev);
612
613
614 pci_vga_init(pci_bus);
615
616 nb_nics1 = nb_nics;
617 if (nb_nics1 > NE2000_NB_MAX)
618 nb_nics1 = NE2000_NB_MAX;
619 for(i = 0; i < nb_nics1; i++) {
620 if (nd_table[i].model == NULL) {
621 nd_table[i].model = g_strdup("ne2k_isa");
622 }
623 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
624 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
625 &nd_table[i]);
626 } else {
627 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
628 }
629 }
630
631 ide_drive_get(hd, ARRAY_SIZE(hd));
632 for(i = 0; i < MAX_IDE_BUS; i++) {
633 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
634 hd[2 * i],
635 hd[2 * i + 1]);
636 }
637 isa_create_simple(isa_bus, "i8042");
638
639 cpu = POWERPC_CPU(first_cpu);
640 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
641
642 portio_list_init(&prep_port_list, NULL, prep_portio_list, sysctrl, "prep");
643 portio_list_add(&prep_port_list, isa_address_space_io(isa), 0x0);
644
645
646#if 0
647 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
648 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
649#endif
650
651 if (usb_enabled()) {
652 pci_create_simple(pci_bus, -1, "pci-ohci");
653 }
654
655 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 2000, 59);
656 if (m48t59 == NULL)
657 return;
658 sysctrl->nvram = m48t59;
659
660
661 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
662 ppc_boot_device,
663 kernel_base, kernel_size,
664 kernel_cmdline,
665 initrd_base, initrd_size,
666
667 0,
668 graphic_width, graphic_height, graphic_depth);
669}
670
671static void prep_machine_init(MachineClass *mc)
672{
673 mc->desc = "PowerPC PREP platform";
674 mc->init = ppc_prep_init;
675 mc->max_cpus = MAX_CPUS;
676 mc->default_boot_order = "cad";
677}
678
679DEFINE_MACHINE("prep", prep_machine_init)
680