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27#include "qemu/osdep.h"
28#include "qapi/error.h"
29#include "sysemu/sysemu.h"
30#include "sysemu/numa.h"
31#include "hw/hw.h"
32#include "hw/fw-path-provider.h"
33#include "elf.h"
34#include "net/net.h"
35#include "sysemu/device_tree.h"
36#include "sysemu/block-backend.h"
37#include "sysemu/cpus.h"
38#include "sysemu/kvm.h"
39#include "sysemu/device_tree.h"
40#include "kvm_ppc.h"
41#include "migration/migration.h"
42#include "mmu-hash64.h"
43#include "qom/cpu.h"
44
45#include "hw/boards.h"
46#include "hw/ppc/ppc.h"
47#include "hw/loader.h"
48
49#include "hw/ppc/spapr.h"
50#include "hw/ppc/spapr_vio.h"
51#include "hw/pci-host/spapr.h"
52#include "hw/ppc/xics.h"
53#include "hw/pci/msi.h"
54
55#include "hw/pci/pci.h"
56#include "hw/scsi/scsi.h"
57#include "hw/virtio/virtio-scsi.h"
58
59#include "exec/address-spaces.h"
60#include "hw/usb.h"
61#include "qemu/config-file.h"
62#include "qemu/error-report.h"
63#include "trace.h"
64#include "hw/nmi.h"
65
66#include "hw/compat.h"
67#include "qemu/cutils.h"
68
69#include <libfdt.h>
70
71
72
73
74
75
76
77
78
79
80
81#define FDT_MAX_SIZE 0x100000
82#define RTAS_MAX_SIZE 0x10000
83#define RTAS_MAX_ADDR 0x80000000
84#define FW_MAX_SIZE 0x400000
85#define FW_FILE_NAME "slof.bin"
86#define FW_OVERHEAD 0x2800000
87#define KERNEL_LOAD_ADDR FW_MAX_SIZE
88
89#define MIN_RMA_SLOF 128UL
90
91#define TIMEBASE_FREQ 512000000ULL
92
93#define PHANDLE_XICP 0x00001111
94
95#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
96
97static XICSState *try_create_xics(const char *type, int nr_servers,
98 int nr_irqs, Error **errp)
99{
100 Error *err = NULL;
101 DeviceState *dev;
102
103 dev = qdev_create(NULL, type);
104 qdev_prop_set_uint32(dev, "nr_servers", nr_servers);
105 qdev_prop_set_uint32(dev, "nr_irqs", nr_irqs);
106 object_property_set_bool(OBJECT(dev), true, "realized", &err);
107 if (err) {
108 error_propagate(errp, err);
109 object_unparent(OBJECT(dev));
110 return NULL;
111 }
112 return XICS_COMMON(dev);
113}
114
115static XICSState *xics_system_init(MachineState *machine,
116 int nr_servers, int nr_irqs, Error **errp)
117{
118 XICSState *icp = NULL;
119
120 if (kvm_enabled()) {
121 Error *err = NULL;
122
123 if (machine_kernel_irqchip_allowed(machine)) {
124 icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
125 }
126 if (machine_kernel_irqchip_required(machine) && !icp) {
127 error_reportf_err(err,
128 "kernel_irqchip requested but unavailable: ");
129 } else {
130 error_free(err);
131 }
132 }
133
134 if (!icp) {
135 icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
136 }
137
138 return icp;
139}
140
141static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
142 int smt_threads)
143{
144 int i, ret = 0;
145 uint32_t servers_prop[smt_threads];
146 uint32_t gservers_prop[smt_threads * 2];
147 int index = ppc_get_vcpu_dt_id(cpu);
148
149 if (cpu->cpu_version) {
150 ret = fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version);
151 if (ret < 0) {
152 return ret;
153 }
154 }
155
156
157 for (i = 0; i < smt_threads; i++) {
158 servers_prop[i] = cpu_to_be32(index + i);
159
160 gservers_prop[i*2] = cpu_to_be32(index + i);
161 gservers_prop[i*2 + 1] = 0;
162 }
163 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
164 servers_prop, sizeof(servers_prop));
165 if (ret < 0) {
166 return ret;
167 }
168 ret = fdt_setprop(fdt, offset, "ibm,ppc-interrupt-gserver#s",
169 gservers_prop, sizeof(gservers_prop));
170
171 return ret;
172}
173
174static int spapr_fixup_cpu_numa_dt(void *fdt, int offset, CPUState *cs)
175{
176 int ret = 0;
177 PowerPCCPU *cpu = POWERPC_CPU(cs);
178 int index = ppc_get_vcpu_dt_id(cpu);
179 uint32_t associativity[] = {cpu_to_be32(0x5),
180 cpu_to_be32(0x0),
181 cpu_to_be32(0x0),
182 cpu_to_be32(0x0),
183 cpu_to_be32(cs->numa_node),
184 cpu_to_be32(index)};
185
186
187 if (nb_numa_nodes > 1) {
188 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
189 sizeof(associativity));
190 }
191
192 return ret;
193}
194
195static int spapr_fixup_cpu_dt(void *fdt, sPAPRMachineState *spapr)
196{
197 int ret = 0, offset, cpus_offset;
198 CPUState *cs;
199 char cpu_model[32];
200 int smt = kvmppc_smt_threads();
201 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
202
203 CPU_FOREACH(cs) {
204 PowerPCCPU *cpu = POWERPC_CPU(cs);
205 DeviceClass *dc = DEVICE_GET_CLASS(cs);
206 int index = ppc_get_vcpu_dt_id(cpu);
207
208 if ((index % smt) != 0) {
209 continue;
210 }
211
212 snprintf(cpu_model, 32, "%s@%x", dc->fw_name, index);
213
214 cpus_offset = fdt_path_offset(fdt, "/cpus");
215 if (cpus_offset < 0) {
216 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
217 "cpus");
218 if (cpus_offset < 0) {
219 return cpus_offset;
220 }
221 }
222 offset = fdt_subnode_offset(fdt, cpus_offset, cpu_model);
223 if (offset < 0) {
224 offset = fdt_add_subnode(fdt, cpus_offset, cpu_model);
225 if (offset < 0) {
226 return offset;
227 }
228 }
229
230 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
231 pft_size_prop, sizeof(pft_size_prop));
232 if (ret < 0) {
233 return ret;
234 }
235
236 ret = spapr_fixup_cpu_numa_dt(fdt, offset, cs);
237 if (ret < 0) {
238 return ret;
239 }
240
241 ret = spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
242 ppc_get_compat_smt_threads(cpu));
243 if (ret < 0) {
244 return ret;
245 }
246 }
247 return ret;
248}
249
250
251static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
252 size_t maxsize)
253{
254 size_t maxcells = maxsize / sizeof(uint32_t);
255 int i, j, count;
256 uint32_t *p = prop;
257
258 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
259 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
260
261 if (!sps->page_shift) {
262 break;
263 }
264 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
265 if (sps->enc[count].page_shift == 0) {
266 break;
267 }
268 }
269 if ((p - prop) >= (maxcells - 3 - count * 2)) {
270 break;
271 }
272 *(p++) = cpu_to_be32(sps->page_shift);
273 *(p++) = cpu_to_be32(sps->slb_enc);
274 *(p++) = cpu_to_be32(count);
275 for (j = 0; j < count; j++) {
276 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
277 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
278 }
279 }
280
281 return (p - prop) * sizeof(uint32_t);
282}
283
284static hwaddr spapr_node0_size(void)
285{
286 MachineState *machine = MACHINE(qdev_get_machine());
287
288 if (nb_numa_nodes) {
289 int i;
290 for (i = 0; i < nb_numa_nodes; ++i) {
291 if (numa_info[i].node_mem) {
292 return MIN(pow2floor(numa_info[i].node_mem),
293 machine->ram_size);
294 }
295 }
296 }
297 return machine->ram_size;
298}
299
300#define _FDT(exp) \
301 do { \
302 int ret = (exp); \
303 if (ret < 0) { \
304 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
305 #exp, fdt_strerror(ret)); \
306 exit(1); \
307 } \
308 } while (0)
309
310static void add_str(GString *s, const gchar *s1)
311{
312 g_string_append_len(s, s1, strlen(s1) + 1);
313}
314
315static void *spapr_create_fdt_skel(hwaddr initrd_base,
316 hwaddr initrd_size,
317 hwaddr kernel_size,
318 bool little_endian,
319 const char *kernel_cmdline,
320 uint32_t epow_irq)
321{
322 void *fdt;
323 uint32_t start_prop = cpu_to_be32(initrd_base);
324 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
325 GString *hypertas = g_string_sized_new(256);
326 GString *qemu_hypertas = g_string_sized_new(256);
327 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
328 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(max_cpus)};
329 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
330 char *buf;
331
332 add_str(hypertas, "hcall-pft");
333 add_str(hypertas, "hcall-term");
334 add_str(hypertas, "hcall-dabr");
335 add_str(hypertas, "hcall-interrupt");
336 add_str(hypertas, "hcall-tce");
337 add_str(hypertas, "hcall-vio");
338 add_str(hypertas, "hcall-splpar");
339 add_str(hypertas, "hcall-bulk");
340 add_str(hypertas, "hcall-set-mode");
341 add_str(qemu_hypertas, "hcall-memop1");
342
343 fdt = g_malloc0(FDT_MAX_SIZE);
344 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
345
346 if (kernel_size) {
347 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
348 }
349 if (initrd_size) {
350 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
351 }
352 _FDT((fdt_finish_reservemap(fdt)));
353
354
355 _FDT((fdt_begin_node(fdt, "")));
356 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
357 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
358 _FDT((fdt_property_string(fdt, "compatible", "qemu,pseries")));
359
360
361
362
363
364 if (kvmppc_get_host_model(&buf)) {
365 _FDT((fdt_property_string(fdt, "host-model", buf)));
366 g_free(buf);
367 }
368 if (kvmppc_get_host_serial(&buf)) {
369 _FDT((fdt_property_string(fdt, "host-serial", buf)));
370 g_free(buf);
371 }
372
373 buf = g_strdup_printf(UUID_FMT, qemu_uuid[0], qemu_uuid[1],
374 qemu_uuid[2], qemu_uuid[3], qemu_uuid[4],
375 qemu_uuid[5], qemu_uuid[6], qemu_uuid[7],
376 qemu_uuid[8], qemu_uuid[9], qemu_uuid[10],
377 qemu_uuid[11], qemu_uuid[12], qemu_uuid[13],
378 qemu_uuid[14], qemu_uuid[15]);
379
380 _FDT((fdt_property_string(fdt, "vm,uuid", buf)));
381 if (qemu_uuid_set) {
382 _FDT((fdt_property_string(fdt, "system-id", buf)));
383 }
384 g_free(buf);
385
386 if (qemu_get_vm_name()) {
387 _FDT((fdt_property_string(fdt, "ibm,partition-name",
388 qemu_get_vm_name())));
389 }
390
391 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
392 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
393
394
395 _FDT((fdt_begin_node(fdt, "chosen")));
396
397
398 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
399
400 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
401 _FDT((fdt_property(fdt, "linux,initrd-start",
402 &start_prop, sizeof(start_prop))));
403 _FDT((fdt_property(fdt, "linux,initrd-end",
404 &end_prop, sizeof(end_prop))));
405 if (kernel_size) {
406 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
407 cpu_to_be64(kernel_size) };
408
409 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
410 if (little_endian) {
411 _FDT((fdt_property(fdt, "qemu,boot-kernel-le", NULL, 0)));
412 }
413 }
414 if (boot_menu) {
415 _FDT((fdt_property_cell(fdt, "qemu,boot-menu", boot_menu)));
416 }
417 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
418 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
419 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
420
421 _FDT((fdt_end_node(fdt)));
422
423
424 _FDT((fdt_begin_node(fdt, "rtas")));
425
426 if (!kvm_enabled() || kvmppc_spapr_use_multitce()) {
427 add_str(hypertas, "hcall-multi-tce");
428 }
429 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas->str,
430 hypertas->len)));
431 g_string_free(hypertas, TRUE);
432 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas->str,
433 qemu_hypertas->len)));
434 g_string_free(qemu_hypertas, TRUE);
435
436 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
437 refpoints, sizeof(refpoints))));
438
439 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
440 _FDT((fdt_property_cell(fdt, "rtas-event-scan-rate",
441 RTAS_EVENT_SCAN_RATE)));
442
443 if (msi_nonbroken) {
444 _FDT((fdt_property(fdt, "ibm,change-msix-capable", NULL, 0)));
445 }
446
447
448
449
450
451
452
453
454 _FDT((fdt_property(fdt, "ibm,extended-os-term", NULL, 0)));
455
456 _FDT((fdt_end_node(fdt)));
457
458
459 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
460
461 _FDT((fdt_property_string(fdt, "device_type",
462 "PowerPC-External-Interrupt-Presentation")));
463 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
464 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
465 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
466 interrupt_server_ranges_prop,
467 sizeof(interrupt_server_ranges_prop))));
468 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
469 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
470 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
471
472 _FDT((fdt_end_node(fdt)));
473
474
475 _FDT((fdt_begin_node(fdt, "vdevice")));
476
477 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
478 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
479 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
480 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
481 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
482 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
483
484 _FDT((fdt_end_node(fdt)));
485
486
487 spapr_events_fdt_skel(fdt, epow_irq);
488
489
490 if (kvm_enabled()) {
491 uint8_t hypercall[16];
492
493
494 _FDT((fdt_begin_node(fdt, "hypervisor")));
495 _FDT((fdt_property_string(fdt, "compatible", "linux,kvm")));
496 if (kvmppc_has_cap_fixup_hcalls()) {
497
498
499
500
501 if (!kvmppc_get_hypercall(first_cpu->env_ptr, hypercall,
502 sizeof(hypercall))) {
503 _FDT((fdt_property(fdt, "hcall-instructions", hypercall,
504 sizeof(hypercall))));
505 }
506 }
507 _FDT((fdt_end_node(fdt)));
508 }
509
510 _FDT((fdt_end_node(fdt)));
511 _FDT((fdt_finish(fdt)));
512
513 return fdt;
514}
515
516static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start,
517 hwaddr size)
518{
519 uint32_t associativity[] = {
520 cpu_to_be32(0x4),
521 cpu_to_be32(0x0), cpu_to_be32(0x0),
522 cpu_to_be32(0x0), cpu_to_be32(nodeid)
523 };
524 char mem_name[32];
525 uint64_t mem_reg_property[2];
526 int off;
527
528 mem_reg_property[0] = cpu_to_be64(start);
529 mem_reg_property[1] = cpu_to_be64(size);
530
531 sprintf(mem_name, "memory@" TARGET_FMT_lx, start);
532 off = fdt_add_subnode(fdt, 0, mem_name);
533 _FDT(off);
534 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
535 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
536 sizeof(mem_reg_property))));
537 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
538 sizeof(associativity))));
539 return off;
540}
541
542static int spapr_populate_memory(sPAPRMachineState *spapr, void *fdt)
543{
544 MachineState *machine = MACHINE(spapr);
545 hwaddr mem_start, node_size;
546 int i, nb_nodes = nb_numa_nodes;
547 NodeInfo *nodes = numa_info;
548 NodeInfo ramnode;
549
550
551 if (!nb_numa_nodes) {
552 nb_nodes = 1;
553 ramnode.node_mem = machine->ram_size;
554 nodes = &ramnode;
555 }
556
557 for (i = 0, mem_start = 0; i < nb_nodes; ++i) {
558 if (!nodes[i].node_mem) {
559 continue;
560 }
561 if (mem_start >= machine->ram_size) {
562 node_size = 0;
563 } else {
564 node_size = nodes[i].node_mem;
565 if (node_size > machine->ram_size - mem_start) {
566 node_size = machine->ram_size - mem_start;
567 }
568 }
569 if (!mem_start) {
570
571 spapr_populate_memory_node(fdt, i, 0, spapr->rma_size);
572 mem_start += spapr->rma_size;
573 node_size -= spapr->rma_size;
574 }
575 for ( ; node_size; ) {
576 hwaddr sizetmp = pow2floor(node_size);
577
578
579 if (ctzl(mem_start) < ctzl(sizetmp)) {
580 sizetmp = 1ULL << ctzl(mem_start);
581 }
582
583 spapr_populate_memory_node(fdt, i, mem_start, sizetmp);
584 node_size -= sizetmp;
585 mem_start += sizetmp;
586 }
587 }
588
589 return 0;
590}
591
592static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset,
593 sPAPRMachineState *spapr)
594{
595 PowerPCCPU *cpu = POWERPC_CPU(cs);
596 CPUPPCState *env = &cpu->env;
597 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
598 int index = ppc_get_vcpu_dt_id(cpu);
599 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
600 0xffffffff, 0xffffffff};
601 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
602 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
603 uint32_t page_sizes_prop[64];
604 size_t page_sizes_prop_size;
605 uint32_t vcpus_per_socket = smp_threads * smp_cores;
606 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
607
608
609
610
611
612
613
614
615
616 uint8_t pa_features_206[] = { 6, 0,
617 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 };
618 uint8_t pa_features_207[] = { 24, 0,
619 0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0,
620 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
621 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
622 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
623 uint8_t *pa_features;
624 size_t pa_size;
625
626 _FDT((fdt_setprop_cell(fdt, offset, "reg", index)));
627 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
628
629 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
630 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
631 env->dcache_line_size)));
632 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
633 env->dcache_line_size)));
634 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
635 env->icache_line_size)));
636 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
637 env->icache_line_size)));
638
639 if (pcc->l1_dcache_size) {
640 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
641 pcc->l1_dcache_size)));
642 } else {
643 fprintf(stderr, "Warning: Unknown L1 dcache size for cpu\n");
644 }
645 if (pcc->l1_icache_size) {
646 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
647 pcc->l1_icache_size)));
648 } else {
649 fprintf(stderr, "Warning: Unknown L1 icache size for cpu\n");
650 }
651
652 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
653 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
654 _FDT((fdt_setprop_cell(fdt, offset, "slb-size", env->slb_nr)));
655 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
656 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
657 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
658
659 if (env->spr_cb[SPR_PURR].oea_read) {
660 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
661 }
662
663 if (env->mmu_model & POWERPC_MMU_1TSEG) {
664 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
665 segs, sizeof(segs))));
666 }
667
668
669
670
671
672 if (env->insns_flags & PPC_ALTIVEC) {
673 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
674
675 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
676 }
677
678
679
680
681 if (env->insns_flags2 & PPC2_DFP) {
682 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
683 }
684
685 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
686 sizeof(page_sizes_prop));
687 if (page_sizes_prop_size) {
688 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
689 page_sizes_prop, page_sizes_prop_size)));
690 }
691
692
693 if (env->mmu_model == POWERPC_MMU_2_06) {
694 pa_features = pa_features_206;
695 pa_size = sizeof(pa_features_206);
696 } else {
697 pa_features = pa_features_207;
698 pa_size = sizeof(pa_features_207);
699 }
700 if (env->ci_large_pages) {
701 pa_features[3] |= 0x20;
702 }
703 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size)));
704
705 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id",
706 cs->cpu_index / vcpus_per_socket)));
707
708 _FDT((fdt_setprop(fdt, offset, "ibm,pft-size",
709 pft_size_prop, sizeof(pft_size_prop))));
710
711 _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cs));
712
713 _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu,
714 ppc_get_compat_smt_threads(cpu)));
715}
716
717static void spapr_populate_cpus_dt_node(void *fdt, sPAPRMachineState *spapr)
718{
719 CPUState *cs;
720 int cpus_offset;
721 char *nodename;
722 int smt = kvmppc_smt_threads();
723
724 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
725 _FDT(cpus_offset);
726 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
727 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
728
729
730
731
732
733
734 CPU_FOREACH_REVERSE(cs) {
735 PowerPCCPU *cpu = POWERPC_CPU(cs);
736 int index = ppc_get_vcpu_dt_id(cpu);
737 DeviceClass *dc = DEVICE_GET_CLASS(cs);
738 int offset;
739
740 if ((index % smt) != 0) {
741 continue;
742 }
743
744 nodename = g_strdup_printf("%s@%x", dc->fw_name, index);
745 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
746 g_free(nodename);
747 _FDT(offset);
748 spapr_populate_cpu_dt(cs, fdt, offset, spapr);
749 }
750
751}
752
753
754
755
756
757
758static int spapr_populate_drconf_memory(sPAPRMachineState *spapr, void *fdt)
759{
760 MachineState *machine = MACHINE(spapr);
761 int ret, i, offset;
762 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
763 uint32_t prop_lmb_size[] = {0, cpu_to_be32(lmb_size)};
764 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
765 uint32_t *int_buf, *cur_index, buf_len;
766 int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
767
768
769
770
771 if (!nr_lmbs) {
772 return 0;
773 }
774
775
776
777
778
779 buf_len = MAX(nr_lmbs * SPAPR_DR_LMB_LIST_ENTRY_SIZE + 1, nr_nodes * 4 + 2)
780 * sizeof(uint32_t);
781 cur_index = int_buf = g_malloc0(buf_len);
782
783 offset = fdt_add_subnode(fdt, 0, "ibm,dynamic-reconfiguration-memory");
784
785 ret = fdt_setprop(fdt, offset, "ibm,lmb-size", prop_lmb_size,
786 sizeof(prop_lmb_size));
787 if (ret < 0) {
788 goto out;
789 }
790
791 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-flags-mask", 0xff);
792 if (ret < 0) {
793 goto out;
794 }
795
796 ret = fdt_setprop_cell(fdt, offset, "ibm,memory-preservation-time", 0x0);
797 if (ret < 0) {
798 goto out;
799 }
800
801
802 int_buf[0] = cpu_to_be32(nr_lmbs);
803 cur_index++;
804 for (i = 0; i < nr_lmbs; i++) {
805 sPAPRDRConnector *drc;
806 sPAPRDRConnectorClass *drck;
807 uint64_t addr = i * lmb_size + spapr->hotplug_memory.base;;
808 uint32_t *dynamic_memory = cur_index;
809
810 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
811 addr/lmb_size);
812 g_assert(drc);
813 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
814
815 dynamic_memory[0] = cpu_to_be32(addr >> 32);
816 dynamic_memory[1] = cpu_to_be32(addr & 0xffffffff);
817 dynamic_memory[2] = cpu_to_be32(drck->get_index(drc));
818 dynamic_memory[3] = cpu_to_be32(0);
819 dynamic_memory[4] = cpu_to_be32(numa_get_node(addr, NULL));
820 if (addr < machine->ram_size ||
821 memory_region_present(get_system_memory(), addr)) {
822 dynamic_memory[5] = cpu_to_be32(SPAPR_LMB_FLAGS_ASSIGNED);
823 } else {
824 dynamic_memory[5] = cpu_to_be32(0);
825 }
826
827 cur_index += SPAPR_DR_LMB_LIST_ENTRY_SIZE;
828 }
829 ret = fdt_setprop(fdt, offset, "ibm,dynamic-memory", int_buf, buf_len);
830 if (ret < 0) {
831 goto out;
832 }
833
834
835 cur_index = int_buf;
836 int_buf[0] = cpu_to_be32(nr_nodes);
837 int_buf[1] = cpu_to_be32(4);
838 cur_index += 2;
839 for (i = 0; i < nr_nodes; i++) {
840 uint32_t associativity[] = {
841 cpu_to_be32(0x0),
842 cpu_to_be32(0x0),
843 cpu_to_be32(0x0),
844 cpu_to_be32(i)
845 };
846 memcpy(cur_index, associativity, sizeof(associativity));
847 cur_index += 4;
848 }
849 ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
850 (cur_index - int_buf) * sizeof(uint32_t));
851out:
852 g_free(int_buf);
853 return ret;
854}
855
856int spapr_h_cas_compose_response(sPAPRMachineState *spapr,
857 target_ulong addr, target_ulong size,
858 bool cpu_update, bool memory_update)
859{
860 void *fdt, *fdt_skel;
861 sPAPRDeviceTreeUpdateHeader hdr = { .version_id = 1 };
862 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
863
864 size -= sizeof(hdr);
865
866
867 fdt_skel = g_malloc0(size);
868 _FDT((fdt_create(fdt_skel, size)));
869 _FDT((fdt_begin_node(fdt_skel, "")));
870 _FDT((fdt_end_node(fdt_skel)));
871 _FDT((fdt_finish(fdt_skel)));
872 fdt = g_malloc0(size);
873 _FDT((fdt_open_into(fdt_skel, fdt, size)));
874 g_free(fdt_skel);
875
876
877 if (cpu_update) {
878 _FDT((spapr_fixup_cpu_dt(fdt, spapr)));
879 }
880
881
882 if (memory_update && smc->dr_lmb_enabled) {
883 _FDT((spapr_populate_drconf_memory(spapr, fdt)));
884 }
885
886
887 _FDT((fdt_pack(fdt)));
888
889 if (fdt_totalsize(fdt) + sizeof(hdr) > size) {
890 trace_spapr_cas_failed(size);
891 return -1;
892 }
893
894 cpu_physical_memory_write(addr, &hdr, sizeof(hdr));
895 cpu_physical_memory_write(addr + sizeof(hdr), fdt, fdt_totalsize(fdt));
896 trace_spapr_cas_continue(fdt_totalsize(fdt) + sizeof(hdr));
897 g_free(fdt);
898
899 return 0;
900}
901
902static void spapr_finalize_fdt(sPAPRMachineState *spapr,
903 hwaddr fdt_addr,
904 hwaddr rtas_addr,
905 hwaddr rtas_size)
906{
907 MachineState *machine = MACHINE(qdev_get_machine());
908 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
909 const char *boot_device = machine->boot_order;
910 int ret, i;
911 size_t cb = 0;
912 char *bootlist;
913 void *fdt;
914 sPAPRPHBState *phb;
915
916 fdt = g_malloc(FDT_MAX_SIZE);
917
918
919 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
920
921 ret = spapr_populate_memory(spapr, fdt);
922 if (ret < 0) {
923 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
924 exit(1);
925 }
926
927 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
928 if (ret < 0) {
929 fprintf(stderr, "couldn't setup vio devices in fdt\n");
930 exit(1);
931 }
932
933 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) {
934 ret = spapr_rng_populate_dt(fdt);
935 if (ret < 0) {
936 fprintf(stderr, "could not set up rng device in the fdt\n");
937 exit(1);
938 }
939 }
940
941 QLIST_FOREACH(phb, &spapr->phbs, list) {
942 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
943 if (ret < 0) {
944 error_report("couldn't setup PCI devices in fdt");
945 exit(1);
946 }
947 }
948
949
950 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
951 if (ret < 0) {
952 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
953 }
954
955
956 spapr_populate_cpus_dt_node(fdt, spapr);
957
958 bootlist = get_boot_devices_list(&cb, true);
959 if (cb && bootlist) {
960 int offset = fdt_path_offset(fdt, "/chosen");
961 if (offset < 0) {
962 exit(1);
963 }
964 for (i = 0; i < cb; i++) {
965 if (bootlist[i] == '\n') {
966 bootlist[i] = ' ';
967 }
968
969 }
970 ret = fdt_setprop_string(fdt, offset, "qemu,boot-list", bootlist);
971 }
972
973 if (boot_device && strlen(boot_device)) {
974 int offset = fdt_path_offset(fdt, "/chosen");
975
976 if (offset < 0) {
977 exit(1);
978 }
979 fdt_setprop_string(fdt, offset, "qemu,boot-device", boot_device);
980 }
981
982 if (!spapr->has_graphics) {
983 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
984 }
985
986 if (smc->dr_lmb_enabled) {
987 _FDT(spapr_drc_populate_dt(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB));
988 }
989
990 _FDT((fdt_pack(fdt)));
991
992 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
993 error_report("FDT too big ! 0x%x bytes (max is 0x%x)",
994 fdt_totalsize(fdt), FDT_MAX_SIZE);
995 exit(1);
996 }
997
998 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
999 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
1000
1001 g_free(bootlist);
1002 g_free(fdt);
1003}
1004
1005static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
1006{
1007 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
1008}
1009
1010static void emulate_spapr_hypercall(PowerPCCPU *cpu)
1011{
1012 CPUPPCState *env = &cpu->env;
1013
1014 if (msr_pr) {
1015 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
1016 env->gpr[3] = H_PRIVILEGE;
1017 } else {
1018 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
1019 }
1020}
1021
1022#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
1023#define HPTE_VALID(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
1024#define HPTE_DIRTY(_hpte) (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
1025#define CLEAN_HPTE(_hpte) ((*(uint64_t *)(_hpte)) &= tswap64(~HPTE64_V_HPTE_DIRTY))
1026#define DIRTY_HPTE(_hpte) ((*(uint64_t *)(_hpte)) |= tswap64(HPTE64_V_HPTE_DIRTY))
1027
1028
1029
1030
1031static int get_htab_fd(sPAPRMachineState *spapr)
1032{
1033 if (spapr->htab_fd >= 0) {
1034 return spapr->htab_fd;
1035 }
1036
1037 spapr->htab_fd = kvmppc_get_htab_fd(false);
1038 if (spapr->htab_fd < 0) {
1039 error_report("Unable to open fd for reading hash table from KVM: %s",
1040 strerror(errno));
1041 }
1042
1043 return spapr->htab_fd;
1044}
1045
1046static void close_htab_fd(sPAPRMachineState *spapr)
1047{
1048 if (spapr->htab_fd >= 0) {
1049 close(spapr->htab_fd);
1050 }
1051 spapr->htab_fd = -1;
1052}
1053
1054static int spapr_hpt_shift_for_ramsize(uint64_t ramsize)
1055{
1056 int shift;
1057
1058
1059
1060
1061 shift = ctz64(pow2ceil(ramsize)) - 7;
1062 shift = MAX(shift, 18);
1063 shift = MIN(shift, 46);
1064 return shift;
1065}
1066
1067static void spapr_reallocate_hpt(sPAPRMachineState *spapr, int shift,
1068 Error **errp)
1069{
1070 long rc;
1071
1072
1073 g_free(spapr->htab);
1074 spapr->htab = NULL;
1075 spapr->htab_shift = 0;
1076 close_htab_fd(spapr);
1077
1078 rc = kvmppc_reset_htab(shift);
1079 if (rc < 0) {
1080
1081 error_setg_errno(errp, errno,
1082 "Failed to allocate KVM HPT of order %d (try smaller maxmem?)",
1083 shift);
1084
1085
1086 } else if (rc > 0) {
1087
1088 if (rc != shift) {
1089 error_setg(errp,
1090 "Requested order %d HPT, but kernel allocated order %ld (try smaller maxmem?)",
1091 shift, rc);
1092 }
1093
1094 spapr->htab_shift = shift;
1095 spapr->htab = NULL;
1096 } else {
1097
1098 size_t size = 1ULL << shift;
1099 int i;
1100
1101 spapr->htab = qemu_memalign(size, size);
1102 if (!spapr->htab) {
1103 error_setg_errno(errp, errno,
1104 "Could not allocate HPT of order %d", shift);
1105 return;
1106 }
1107
1108 memset(spapr->htab, 0, size);
1109 spapr->htab_shift = shift;
1110
1111 for (i = 0; i < size / HASH_PTE_SIZE_64; i++) {
1112 DIRTY_HPTE(HPTE(spapr->htab, i));
1113 }
1114 }
1115}
1116
1117static int find_unknown_sysbus_device(SysBusDevice *sbdev, void *opaque)
1118{
1119 bool matched = false;
1120
1121 if (object_dynamic_cast(OBJECT(sbdev), TYPE_SPAPR_PCI_HOST_BRIDGE)) {
1122 matched = true;
1123 }
1124
1125 if (!matched) {
1126 error_report("Device %s is not supported by this machine yet.",
1127 qdev_fw_name(DEVICE(sbdev)));
1128 exit(1);
1129 }
1130
1131 return 0;
1132}
1133
1134static void ppc_spapr_reset(void)
1135{
1136 MachineState *machine = MACHINE(qdev_get_machine());
1137 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1138 PowerPCCPU *first_ppc_cpu;
1139 uint32_t rtas_limit;
1140
1141
1142 foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
1143
1144
1145 spapr_reallocate_hpt(spapr,
1146 spapr_hpt_shift_for_ramsize(machine->maxram_size),
1147 &error_fatal);
1148
1149
1150 if (spapr->vrma_adjust) {
1151 spapr->rma_size = kvmppc_rma_size(spapr_node0_size(),
1152 spapr->htab_shift);
1153 }
1154
1155 qemu_devices_reset();
1156
1157
1158
1159
1160
1161
1162 rtas_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR);
1163 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
1164 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
1165
1166
1167 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
1168 spapr->rtas_size);
1169
1170
1171 cpu_physical_memory_write(spapr->rtas_addr, spapr->rtas_blob,
1172 spapr->rtas_size);
1173
1174
1175 first_ppc_cpu = POWERPC_CPU(first_cpu);
1176 first_ppc_cpu->env.gpr[3] = spapr->fdt_addr;
1177 first_ppc_cpu->env.gpr[5] = 0;
1178 first_cpu->halted = 0;
1179 first_ppc_cpu->env.nip = SPAPR_ENTRY_POINT;
1180
1181}
1182
1183static void spapr_cpu_reset(void *opaque)
1184{
1185 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
1186 PowerPCCPU *cpu = opaque;
1187 CPUState *cs = CPU(cpu);
1188 CPUPPCState *env = &cpu->env;
1189
1190 cpu_reset(cs);
1191
1192
1193
1194
1195 cs->halted = 1;
1196
1197 env->spr[SPR_HIOR] = 0;
1198
1199 ppc_hash64_set_external_hpt(cpu, spapr->htab, spapr->htab_shift,
1200 &error_fatal);
1201}
1202
1203static void spapr_create_nvram(sPAPRMachineState *spapr)
1204{
1205 DeviceState *dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
1206 DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
1207
1208 if (dinfo) {
1209 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
1210 &error_fatal);
1211 }
1212
1213 qdev_init_nofail(dev);
1214
1215 spapr->nvram = (struct sPAPRNVRAM *)dev;
1216}
1217
1218static void spapr_rtc_create(sPAPRMachineState *spapr)
1219{
1220 DeviceState *dev = qdev_create(NULL, TYPE_SPAPR_RTC);
1221
1222 qdev_init_nofail(dev);
1223 spapr->rtc = dev;
1224
1225 object_property_add_alias(qdev_get_machine(), "rtc-time",
1226 OBJECT(spapr->rtc), "date", NULL);
1227}
1228
1229
1230static bool spapr_vga_init(PCIBus *pci_bus, Error **errp)
1231{
1232 switch (vga_interface_type) {
1233 case VGA_NONE:
1234 return false;
1235 case VGA_DEVICE:
1236 return true;
1237 case VGA_STD:
1238 case VGA_VIRTIO:
1239 return pci_vga_init(pci_bus) != NULL;
1240 default:
1241 error_setg(errp,
1242 "Unsupported VGA mode, only -vga std or -vga virtio is supported");
1243 return false;
1244 }
1245}
1246
1247static int spapr_post_load(void *opaque, int version_id)
1248{
1249 sPAPRMachineState *spapr = (sPAPRMachineState *)opaque;
1250 int err = 0;
1251
1252
1253
1254
1255
1256 if (version_id < 3) {
1257 err = spapr_rtc_import_offset(spapr->rtc, spapr->rtc_offset);
1258 }
1259
1260 return err;
1261}
1262
1263static bool version_before_3(void *opaque, int version_id)
1264{
1265 return version_id < 3;
1266}
1267
1268static const VMStateDescription vmstate_spapr = {
1269 .name = "spapr",
1270 .version_id = 3,
1271 .minimum_version_id = 1,
1272 .post_load = spapr_post_load,
1273 .fields = (VMStateField[]) {
1274
1275 VMSTATE_UNUSED_BUFFER(version_before_3, 0, 4),
1276
1277
1278 VMSTATE_UINT64_TEST(rtc_offset, sPAPRMachineState, version_before_3),
1279
1280 VMSTATE_PPC_TIMEBASE_V(tb, sPAPRMachineState, 2),
1281 VMSTATE_END_OF_LIST()
1282 },
1283};
1284
1285static int htab_save_setup(QEMUFile *f, void *opaque)
1286{
1287 sPAPRMachineState *spapr = opaque;
1288
1289
1290 qemu_put_be32(f, spapr->htab_shift);
1291
1292 if (spapr->htab) {
1293 spapr->htab_save_index = 0;
1294 spapr->htab_first_pass = true;
1295 } else {
1296 assert(kvm_enabled());
1297 }
1298
1299
1300 return 0;
1301}
1302
1303static void htab_save_first_pass(QEMUFile *f, sPAPRMachineState *spapr,
1304 int64_t max_ns)
1305{
1306 bool has_timeout = max_ns != -1;
1307 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1308 int index = spapr->htab_save_index;
1309 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1310
1311 assert(spapr->htab_first_pass);
1312
1313 do {
1314 int chunkstart;
1315
1316
1317 while ((index < htabslots)
1318 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1319 index++;
1320 CLEAN_HPTE(HPTE(spapr->htab, index));
1321 }
1322
1323
1324 chunkstart = index;
1325 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1326 && HPTE_VALID(HPTE(spapr->htab, index))) {
1327 index++;
1328 CLEAN_HPTE(HPTE(spapr->htab, index));
1329 }
1330
1331 if (index > chunkstart) {
1332 int n_valid = index - chunkstart;
1333
1334 qemu_put_be32(f, chunkstart);
1335 qemu_put_be16(f, n_valid);
1336 qemu_put_be16(f, 0);
1337 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1338 HASH_PTE_SIZE_64 * n_valid);
1339
1340 if (has_timeout &&
1341 (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1342 break;
1343 }
1344 }
1345 } while ((index < htabslots) && !qemu_file_rate_limit(f));
1346
1347 if (index >= htabslots) {
1348 assert(index == htabslots);
1349 index = 0;
1350 spapr->htab_first_pass = false;
1351 }
1352 spapr->htab_save_index = index;
1353}
1354
1355static int htab_save_later_pass(QEMUFile *f, sPAPRMachineState *spapr,
1356 int64_t max_ns)
1357{
1358 bool final = max_ns < 0;
1359 int htabslots = HTAB_SIZE(spapr) / HASH_PTE_SIZE_64;
1360 int examined = 0, sent = 0;
1361 int index = spapr->htab_save_index;
1362 int64_t starttime = qemu_clock_get_ns(QEMU_CLOCK_REALTIME);
1363
1364 assert(!spapr->htab_first_pass);
1365
1366 do {
1367 int chunkstart, invalidstart;
1368
1369
1370 while ((index < htabslots)
1371 && !HPTE_DIRTY(HPTE(spapr->htab, index))) {
1372 index++;
1373 examined++;
1374 }
1375
1376 chunkstart = index;
1377
1378 while ((index < htabslots) && (index - chunkstart < USHRT_MAX)
1379 && HPTE_DIRTY(HPTE(spapr->htab, index))
1380 && HPTE_VALID(HPTE(spapr->htab, index))) {
1381 CLEAN_HPTE(HPTE(spapr->htab, index));
1382 index++;
1383 examined++;
1384 }
1385
1386 invalidstart = index;
1387
1388 while ((index < htabslots) && (index - invalidstart < USHRT_MAX)
1389 && HPTE_DIRTY(HPTE(spapr->htab, index))
1390 && !HPTE_VALID(HPTE(spapr->htab, index))) {
1391 CLEAN_HPTE(HPTE(spapr->htab, index));
1392 index++;
1393 examined++;
1394 }
1395
1396 if (index > chunkstart) {
1397 int n_valid = invalidstart - chunkstart;
1398 int n_invalid = index - invalidstart;
1399
1400 qemu_put_be32(f, chunkstart);
1401 qemu_put_be16(f, n_valid);
1402 qemu_put_be16(f, n_invalid);
1403 qemu_put_buffer(f, HPTE(spapr->htab, chunkstart),
1404 HASH_PTE_SIZE_64 * n_valid);
1405 sent += index - chunkstart;
1406
1407 if (!final && (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) - starttime) > max_ns) {
1408 break;
1409 }
1410 }
1411
1412 if (examined >= htabslots) {
1413 break;
1414 }
1415
1416 if (index >= htabslots) {
1417 assert(index == htabslots);
1418 index = 0;
1419 }
1420 } while ((examined < htabslots) && (!qemu_file_rate_limit(f) || final));
1421
1422 if (index >= htabslots) {
1423 assert(index == htabslots);
1424 index = 0;
1425 }
1426
1427 spapr->htab_save_index = index;
1428
1429 return (examined >= htabslots) && (sent == 0) ? 1 : 0;
1430}
1431
1432#define MAX_ITERATION_NS 5000000
1433#define MAX_KVM_BUF_SIZE 2048
1434
1435static int htab_save_iterate(QEMUFile *f, void *opaque)
1436{
1437 sPAPRMachineState *spapr = opaque;
1438 int fd;
1439 int rc = 0;
1440
1441
1442 qemu_put_be32(f, 0);
1443
1444 if (!spapr->htab) {
1445 assert(kvm_enabled());
1446
1447 fd = get_htab_fd(spapr);
1448 if (fd < 0) {
1449 return fd;
1450 }
1451
1452 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, MAX_ITERATION_NS);
1453 if (rc < 0) {
1454 return rc;
1455 }
1456 } else if (spapr->htab_first_pass) {
1457 htab_save_first_pass(f, spapr, MAX_ITERATION_NS);
1458 } else {
1459 rc = htab_save_later_pass(f, spapr, MAX_ITERATION_NS);
1460 }
1461
1462
1463 qemu_put_be32(f, 0);
1464 qemu_put_be16(f, 0);
1465 qemu_put_be16(f, 0);
1466
1467 return rc;
1468}
1469
1470static int htab_save_complete(QEMUFile *f, void *opaque)
1471{
1472 sPAPRMachineState *spapr = opaque;
1473 int fd;
1474
1475
1476 qemu_put_be32(f, 0);
1477
1478 if (!spapr->htab) {
1479 int rc;
1480
1481 assert(kvm_enabled());
1482
1483 fd = get_htab_fd(spapr);
1484 if (fd < 0) {
1485 return fd;
1486 }
1487
1488 rc = kvmppc_save_htab(f, fd, MAX_KVM_BUF_SIZE, -1);
1489 if (rc < 0) {
1490 return rc;
1491 }
1492 close_htab_fd(spapr);
1493 } else {
1494 if (spapr->htab_first_pass) {
1495 htab_save_first_pass(f, spapr, -1);
1496 }
1497 htab_save_later_pass(f, spapr, -1);
1498 }
1499
1500
1501 qemu_put_be32(f, 0);
1502 qemu_put_be16(f, 0);
1503 qemu_put_be16(f, 0);
1504
1505 return 0;
1506}
1507
1508static int htab_load(QEMUFile *f, void *opaque, int version_id)
1509{
1510 sPAPRMachineState *spapr = opaque;
1511 uint32_t section_hdr;
1512 int fd = -1;
1513
1514 if (version_id < 1 || version_id > 1) {
1515 error_report("htab_load() bad version");
1516 return -EINVAL;
1517 }
1518
1519 section_hdr = qemu_get_be32(f);
1520
1521 if (section_hdr) {
1522 Error *local_err = NULL;
1523
1524
1525 spapr_reallocate_hpt(spapr, section_hdr, &local_err);
1526 if (local_err) {
1527 error_report_err(local_err);
1528 return -EINVAL;
1529 }
1530 return 0;
1531 }
1532
1533 if (!spapr->htab) {
1534 assert(kvm_enabled());
1535
1536 fd = kvmppc_get_htab_fd(true);
1537 if (fd < 0) {
1538 error_report("Unable to open fd to restore KVM hash table: %s",
1539 strerror(errno));
1540 }
1541 }
1542
1543 while (true) {
1544 uint32_t index;
1545 uint16_t n_valid, n_invalid;
1546
1547 index = qemu_get_be32(f);
1548 n_valid = qemu_get_be16(f);
1549 n_invalid = qemu_get_be16(f);
1550
1551 if ((index == 0) && (n_valid == 0) && (n_invalid == 0)) {
1552
1553 break;
1554 }
1555
1556 if ((index + n_valid + n_invalid) >
1557 (HTAB_SIZE(spapr) / HASH_PTE_SIZE_64)) {
1558
1559 error_report(
1560 "htab_load() bad index %d (%hd+%hd entries) in htab stream (htab_shift=%d)",
1561 index, n_valid, n_invalid, spapr->htab_shift);
1562 return -EINVAL;
1563 }
1564
1565 if (spapr->htab) {
1566 if (n_valid) {
1567 qemu_get_buffer(f, HPTE(spapr->htab, index),
1568 HASH_PTE_SIZE_64 * n_valid);
1569 }
1570 if (n_invalid) {
1571 memset(HPTE(spapr->htab, index + n_valid), 0,
1572 HASH_PTE_SIZE_64 * n_invalid);
1573 }
1574 } else {
1575 int rc;
1576
1577 assert(fd >= 0);
1578
1579 rc = kvmppc_load_htab_chunk(f, fd, index, n_valid, n_invalid);
1580 if (rc < 0) {
1581 return rc;
1582 }
1583 }
1584 }
1585
1586 if (!spapr->htab) {
1587 assert(fd >= 0);
1588 close(fd);
1589 }
1590
1591 return 0;
1592}
1593
1594static SaveVMHandlers savevm_htab_handlers = {
1595 .save_live_setup = htab_save_setup,
1596 .save_live_iterate = htab_save_iterate,
1597 .save_live_complete_precopy = htab_save_complete,
1598 .load_state = htab_load,
1599};
1600
1601static void spapr_boot_set(void *opaque, const char *boot_device,
1602 Error **errp)
1603{
1604 MachineState *machine = MACHINE(qdev_get_machine());
1605 machine->boot_order = g_strdup(boot_device);
1606}
1607
1608static void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu,
1609 Error **errp)
1610{
1611 CPUPPCState *env = &cpu->env;
1612
1613
1614 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
1615
1616
1617 cpu_ppc_set_papr(cpu);
1618
1619 if (cpu->max_compat) {
1620 Error *local_err = NULL;
1621
1622 ppc_set_compat(cpu, cpu->max_compat, &local_err);
1623 if (local_err) {
1624 error_propagate(errp, local_err);
1625 return;
1626 }
1627 }
1628
1629 xics_cpu_setup(spapr->icp, cpu);
1630
1631 qemu_register_reset(spapr_cpu_reset, cpu);
1632}
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642static void spapr_drc_reset(void *opaque)
1643{
1644 sPAPRDRConnector *drc = opaque;
1645 DeviceState *d = DEVICE(drc);
1646
1647 if (d) {
1648 device_reset(d);
1649 }
1650}
1651
1652static void spapr_create_lmb_dr_connectors(sPAPRMachineState *spapr)
1653{
1654 MachineState *machine = MACHINE(spapr);
1655 uint64_t lmb_size = SPAPR_MEMORY_BLOCK_SIZE;
1656 uint32_t nr_lmbs = (machine->maxram_size - machine->ram_size)/lmb_size;
1657 int i;
1658
1659 for (i = 0; i < nr_lmbs; i++) {
1660 sPAPRDRConnector *drc;
1661 uint64_t addr;
1662
1663 addr = i * lmb_size + spapr->hotplug_memory.base;
1664 drc = spapr_dr_connector_new(OBJECT(spapr), SPAPR_DR_CONNECTOR_TYPE_LMB,
1665 addr/lmb_size);
1666 qemu_register_reset(spapr_drc_reset, drc);
1667 }
1668}
1669
1670
1671
1672
1673
1674
1675static void spapr_validate_node_memory(MachineState *machine, Error **errp)
1676{
1677 int i;
1678
1679 if (machine->ram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1680 error_setg(errp, "Memory size 0x" RAM_ADDR_FMT
1681 " is not aligned to %llu MiB",
1682 machine->ram_size,
1683 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1684 return;
1685 }
1686
1687 if (machine->maxram_size % SPAPR_MEMORY_BLOCK_SIZE) {
1688 error_setg(errp, "Maximum memory size 0x" RAM_ADDR_FMT
1689 " is not aligned to %llu MiB",
1690 machine->ram_size,
1691 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1692 return;
1693 }
1694
1695 for (i = 0; i < nb_numa_nodes; i++) {
1696 if (numa_info[i].node_mem % SPAPR_MEMORY_BLOCK_SIZE) {
1697 error_setg(errp,
1698 "Node %d memory size 0x%" PRIx64
1699 " is not aligned to %llu MiB",
1700 i, numa_info[i].node_mem,
1701 SPAPR_MEMORY_BLOCK_SIZE / M_BYTE);
1702 return;
1703 }
1704 }
1705}
1706
1707
1708static void ppc_spapr_init(MachineState *machine)
1709{
1710 sPAPRMachineState *spapr = SPAPR_MACHINE(machine);
1711 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine);
1712 const char *kernel_filename = machine->kernel_filename;
1713 const char *kernel_cmdline = machine->kernel_cmdline;
1714 const char *initrd_filename = machine->initrd_filename;
1715 PowerPCCPU *cpu;
1716 PCIHostState *phb;
1717 int i;
1718 MemoryRegion *sysmem = get_system_memory();
1719 MemoryRegion *ram = g_new(MemoryRegion, 1);
1720 MemoryRegion *rma_region;
1721 void *rma = NULL;
1722 hwaddr rma_alloc_size;
1723 hwaddr node0_size = spapr_node0_size();
1724 uint32_t initrd_base = 0;
1725 long kernel_size = 0, initrd_size = 0;
1726 long load_limit, fw_size;
1727 bool kernel_le = false;
1728 char *filename;
1729
1730 msi_nonbroken = true;
1731
1732 QLIST_INIT(&spapr->phbs);
1733
1734 cpu_ppc_hypercall = emulate_spapr_hypercall;
1735
1736
1737 rma_alloc_size = kvmppc_alloc_rma(&rma);
1738
1739 if (rma_alloc_size == -1) {
1740 error_report("Unable to create RMA");
1741 exit(1);
1742 }
1743
1744 if (rma_alloc_size && (rma_alloc_size < node0_size)) {
1745 spapr->rma_size = rma_alloc_size;
1746 } else {
1747 spapr->rma_size = node0_size;
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758 if (kvm_enabled()) {
1759 spapr->vrma_adjust = 1;
1760 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
1761 }
1762 }
1763
1764 if (spapr->rma_size > node0_size) {
1765 error_report("Numa node 0 has to span the RMA (%#08"HWADDR_PRIx")",
1766 spapr->rma_size);
1767 exit(1);
1768 }
1769
1770
1771 load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
1772
1773
1774 spapr->icp = xics_system_init(machine,
1775 DIV_ROUND_UP(max_cpus * kvmppc_smt_threads(),
1776 smp_threads),
1777 XICS_IRQS, &error_fatal);
1778
1779 if (smc->dr_lmb_enabled) {
1780 spapr_validate_node_memory(machine, &error_fatal);
1781 }
1782
1783
1784 if (machine->cpu_model == NULL) {
1785 machine->cpu_model = kvm_enabled() ? "host" : "POWER7";
1786 }
1787 for (i = 0; i < smp_cpus; i++) {
1788 cpu = cpu_ppc_init(machine->cpu_model);
1789 if (cpu == NULL) {
1790 error_report("Unable to find PowerPC CPU definition");
1791 exit(1);
1792 }
1793 spapr_cpu_init(spapr, cpu, &error_fatal);
1794 }
1795
1796 if (kvm_enabled()) {
1797
1798 kvmppc_enable_logical_ci_hcalls();
1799 kvmppc_enable_set_mode_hcall();
1800 }
1801
1802
1803 memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram",
1804 machine->ram_size);
1805 memory_region_add_subregion(sysmem, 0, ram);
1806
1807 if (rma_alloc_size && rma) {
1808 rma_region = g_new(MemoryRegion, 1);
1809 memory_region_init_ram_ptr(rma_region, NULL, "ppc_spapr.rma",
1810 rma_alloc_size, rma);
1811 vmstate_register_ram_global(rma_region);
1812 memory_region_add_subregion(sysmem, 0, rma_region);
1813 }
1814
1815
1816 if (machine->ram_size < machine->maxram_size) {
1817 ram_addr_t hotplug_mem_size = machine->maxram_size - machine->ram_size;
1818
1819 if (machine->ram_slots > SPAPR_MAX_RAM_SLOTS) {
1820 error_report("Specified number of memory slots %"
1821 PRIu64" exceeds max supported %d",
1822 machine->ram_slots, SPAPR_MAX_RAM_SLOTS);
1823 exit(1);
1824 }
1825
1826 spapr->hotplug_memory.base = ROUND_UP(machine->ram_size,
1827 SPAPR_HOTPLUG_MEM_ALIGN);
1828 memory_region_init(&spapr->hotplug_memory.mr, OBJECT(spapr),
1829 "hotplug-memory", hotplug_mem_size);
1830 memory_region_add_subregion(sysmem, spapr->hotplug_memory.base,
1831 &spapr->hotplug_memory.mr);
1832 }
1833
1834 if (smc->dr_lmb_enabled) {
1835 spapr_create_lmb_dr_connectors(spapr);
1836 }
1837
1838 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
1839 if (!filename) {
1840 error_report("Could not find LPAR rtas '%s'", "spapr-rtas.bin");
1841 exit(1);
1842 }
1843 spapr->rtas_size = get_image_size(filename);
1844 spapr->rtas_blob = g_malloc(spapr->rtas_size);
1845 if (load_image_size(filename, spapr->rtas_blob, spapr->rtas_size) < 0) {
1846 error_report("Could not load LPAR rtas '%s'", filename);
1847 exit(1);
1848 }
1849 if (spapr->rtas_size > RTAS_MAX_SIZE) {
1850 error_report("RTAS too big ! 0x%zx bytes (max is 0x%x)",
1851 (size_t)spapr->rtas_size, RTAS_MAX_SIZE);
1852 exit(1);
1853 }
1854 g_free(filename);
1855
1856
1857 spapr_events_init(spapr);
1858
1859
1860 spapr_rtc_create(spapr);
1861
1862
1863 spapr->vio_bus = spapr_vio_bus_init();
1864
1865 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
1866 if (serial_hds[i]) {
1867 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
1868 }
1869 }
1870
1871
1872 spapr_create_nvram(spapr);
1873
1874
1875 spapr_pci_rtas_init();
1876
1877 phb = spapr_create_phb(spapr, 0);
1878
1879 for (i = 0; i < nb_nics; i++) {
1880 NICInfo *nd = &nd_table[i];
1881
1882 if (!nd->model) {
1883 nd->model = g_strdup("ibmveth");
1884 }
1885
1886 if (strcmp(nd->model, "ibmveth") == 0) {
1887 spapr_vlan_create(spapr->vio_bus, nd);
1888 } else {
1889 pci_nic_init_nofail(&nd_table[i], phb->bus, nd->model, NULL);
1890 }
1891 }
1892
1893 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
1894 spapr_vscsi_create(spapr->vio_bus);
1895 }
1896
1897
1898 if (spapr_vga_init(phb->bus, &error_fatal)) {
1899 spapr->has_graphics = true;
1900 machine->usb |= defaults_enabled() && !machine->usb_disabled;
1901 }
1902
1903 if (machine->usb) {
1904 if (smc->use_ohci_by_default) {
1905 pci_create_simple(phb->bus, -1, "pci-ohci");
1906 } else {
1907 pci_create_simple(phb->bus, -1, "nec-usb-xhci");
1908 }
1909
1910 if (spapr->has_graphics) {
1911 USBBus *usb_bus = usb_bus_find(-1);
1912
1913 usb_create_simple(usb_bus, "usb-kbd");
1914 usb_create_simple(usb_bus, "usb-mouse");
1915 }
1916 }
1917
1918 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
1919 error_report(
1920 "pSeries SLOF firmware requires >= %ldM guest RMA (Real Mode Area memory)",
1921 MIN_RMA_SLOF);
1922 exit(1);
1923 }
1924
1925 if (kernel_filename) {
1926 uint64_t lowaddr = 0;
1927
1928 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
1929 NULL, &lowaddr, NULL, 1, PPC_ELF_MACHINE,
1930 0, 0);
1931 if (kernel_size == ELF_LOAD_WRONG_ENDIAN) {
1932 kernel_size = load_elf(kernel_filename,
1933 translate_kernel_address, NULL,
1934 NULL, &lowaddr, NULL, 0, PPC_ELF_MACHINE,
1935 0, 0);
1936 kernel_le = kernel_size > 0;
1937 }
1938 if (kernel_size < 0) {
1939 error_report("error loading %s: %s",
1940 kernel_filename, load_elf_strerror(kernel_size));
1941 exit(1);
1942 }
1943
1944
1945 if (initrd_filename) {
1946
1947
1948
1949 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
1950 initrd_size = load_image_targphys(initrd_filename, initrd_base,
1951 load_limit - initrd_base);
1952 if (initrd_size < 0) {
1953 error_report("could not load initial ram disk '%s'",
1954 initrd_filename);
1955 exit(1);
1956 }
1957 } else {
1958 initrd_base = 0;
1959 initrd_size = 0;
1960 }
1961 }
1962
1963 if (bios_name == NULL) {
1964 bios_name = FW_FILE_NAME;
1965 }
1966 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1967 if (!filename) {
1968 error_report("Could not find LPAR firmware '%s'", bios_name);
1969 exit(1);
1970 }
1971 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
1972 if (fw_size <= 0) {
1973 error_report("Could not load LPAR firmware '%s'", filename);
1974 exit(1);
1975 }
1976 g_free(filename);
1977
1978
1979
1980
1981 vmstate_register(NULL, 0, &vmstate_spapr, spapr);
1982 register_savevm_live(NULL, "spapr/htab", -1, 1,
1983 &savevm_htab_handlers, spapr);
1984
1985
1986 spapr->fdt_skel = spapr_create_fdt_skel(initrd_base, initrd_size,
1987 kernel_size, kernel_le,
1988 kernel_cmdline,
1989 spapr->check_exception_irq);
1990 assert(spapr->fdt_skel != NULL);
1991
1992
1993 QTAILQ_INIT(&spapr->ccs_list);
1994 qemu_register_reset(spapr_ccs_reset_hook, spapr);
1995
1996 qemu_register_boot_set(spapr_boot_set, spapr);
1997}
1998
1999static int spapr_kvm_type(const char *vm_type)
2000{
2001 if (!vm_type) {
2002 return 0;
2003 }
2004
2005 if (!strcmp(vm_type, "HV")) {
2006 return 1;
2007 }
2008
2009 if (!strcmp(vm_type, "PR")) {
2010 return 2;
2011 }
2012
2013 error_report("Unknown kvm-type specified '%s'", vm_type);
2014 exit(1);
2015}
2016
2017
2018
2019
2020
2021static char *spapr_get_fw_dev_path(FWPathProvider *p, BusState *bus,
2022 DeviceState *dev)
2023{
2024#define CAST(type, obj, name) \
2025 ((type *)object_dynamic_cast(OBJECT(obj), (name)))
2026 SCSIDevice *d = CAST(SCSIDevice, dev, TYPE_SCSI_DEVICE);
2027 sPAPRPHBState *phb = CAST(sPAPRPHBState, dev, TYPE_SPAPR_PCI_HOST_BRIDGE);
2028
2029 if (d) {
2030 void *spapr = CAST(void, bus->parent, "spapr-vscsi");
2031 VirtIOSCSI *virtio = CAST(VirtIOSCSI, bus->parent, TYPE_VIRTIO_SCSI);
2032 USBDevice *usb = CAST(USBDevice, bus->parent, TYPE_USB_DEVICE);
2033
2034 if (spapr) {
2035
2036
2037
2038
2039
2040 unsigned id = 0x8000 | (d->id << 8) | d->lun;
2041 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2042 (uint64_t)id << 48);
2043 } else if (virtio) {
2044
2045
2046
2047
2048
2049
2050
2051 unsigned id = 0x1000000 | (d->id << 16) | d->lun;
2052 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2053 (uint64_t)id << 32);
2054 } else if (usb) {
2055
2056
2057
2058
2059 unsigned usb_port = atoi(usb->port->path);
2060 unsigned id = 0x1000000 | (usb_port << 16) | d->lun;
2061 return g_strdup_printf("%s@%"PRIX64, qdev_fw_name(dev),
2062 (uint64_t)id << 32);
2063 }
2064 }
2065
2066 if (phb) {
2067
2068 return g_strdup_printf("pci@%"PRIX64, phb->buid);
2069 }
2070
2071 return NULL;
2072}
2073
2074static char *spapr_get_kvm_type(Object *obj, Error **errp)
2075{
2076 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2077
2078 return g_strdup(spapr->kvm_type);
2079}
2080
2081static void spapr_set_kvm_type(Object *obj, const char *value, Error **errp)
2082{
2083 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2084
2085 g_free(spapr->kvm_type);
2086 spapr->kvm_type = g_strdup(value);
2087}
2088
2089static void spapr_machine_initfn(Object *obj)
2090{
2091 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2092
2093 spapr->htab_fd = -1;
2094 object_property_add_str(obj, "kvm-type",
2095 spapr_get_kvm_type, spapr_set_kvm_type, NULL);
2096 object_property_set_description(obj, "kvm-type",
2097 "Specifies the KVM virtualization mode (HV, PR)",
2098 NULL);
2099}
2100
2101static void spapr_machine_finalizefn(Object *obj)
2102{
2103 sPAPRMachineState *spapr = SPAPR_MACHINE(obj);
2104
2105 g_free(spapr->kvm_type);
2106}
2107
2108static void ppc_cpu_do_nmi_on_cpu(void *arg)
2109{
2110 CPUState *cs = arg;
2111
2112 cpu_synchronize_state(cs);
2113 ppc_cpu_do_system_reset(cs);
2114}
2115
2116static void spapr_nmi(NMIState *n, int cpu_index, Error **errp)
2117{
2118 CPUState *cs;
2119
2120 CPU_FOREACH(cs) {
2121 async_run_on_cpu(cs, ppc_cpu_do_nmi_on_cpu, cs);
2122 }
2123}
2124
2125static void spapr_add_lmbs(DeviceState *dev, uint64_t addr, uint64_t size,
2126 uint32_t node, Error **errp)
2127{
2128 sPAPRDRConnector *drc;
2129 sPAPRDRConnectorClass *drck;
2130 uint32_t nr_lmbs = size/SPAPR_MEMORY_BLOCK_SIZE;
2131 int i, fdt_offset, fdt_size;
2132 void *fdt;
2133
2134
2135
2136
2137
2138
2139 if (!dev->hotplugged) {
2140 return;
2141 }
2142
2143 for (i = 0; i < nr_lmbs; i++) {
2144 drc = spapr_dr_connector_by_id(SPAPR_DR_CONNECTOR_TYPE_LMB,
2145 addr/SPAPR_MEMORY_BLOCK_SIZE);
2146 g_assert(drc);
2147
2148 fdt = create_device_tree(&fdt_size);
2149 fdt_offset = spapr_populate_memory_node(fdt, node, addr,
2150 SPAPR_MEMORY_BLOCK_SIZE);
2151
2152 drck = SPAPR_DR_CONNECTOR_GET_CLASS(drc);
2153 drck->attach(drc, dev, fdt, fdt_offset, !dev->hotplugged, errp);
2154 addr += SPAPR_MEMORY_BLOCK_SIZE;
2155 }
2156 spapr_hotplug_req_add_by_count(SPAPR_DR_CONNECTOR_TYPE_LMB, nr_lmbs);
2157}
2158
2159static void spapr_memory_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2160 uint32_t node, Error **errp)
2161{
2162 Error *local_err = NULL;
2163 sPAPRMachineState *ms = SPAPR_MACHINE(hotplug_dev);
2164 PCDIMMDevice *dimm = PC_DIMM(dev);
2165 PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
2166 MemoryRegion *mr = ddc->get_memory_region(dimm);
2167 uint64_t align = memory_region_get_alignment(mr);
2168 uint64_t size = memory_region_size(mr);
2169 uint64_t addr;
2170
2171 if (size % SPAPR_MEMORY_BLOCK_SIZE) {
2172 error_setg(&local_err, "Hotplugged memory size must be a multiple of "
2173 "%lld MB", SPAPR_MEMORY_BLOCK_SIZE/M_BYTE);
2174 goto out;
2175 }
2176
2177 pc_dimm_memory_plug(dev, &ms->hotplug_memory, mr, align, &local_err);
2178 if (local_err) {
2179 goto out;
2180 }
2181
2182 addr = object_property_get_int(OBJECT(dimm), PC_DIMM_ADDR_PROP, &local_err);
2183 if (local_err) {
2184 pc_dimm_memory_unplug(dev, &ms->hotplug_memory, mr);
2185 goto out;
2186 }
2187
2188 spapr_add_lmbs(dev, addr, size, node, &error_abort);
2189
2190out:
2191 error_propagate(errp, local_err);
2192}
2193
2194static void spapr_machine_device_plug(HotplugHandler *hotplug_dev,
2195 DeviceState *dev, Error **errp)
2196{
2197 sPAPRMachineClass *smc = SPAPR_MACHINE_GET_CLASS(qdev_get_machine());
2198
2199 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2200 int node;
2201
2202 if (!smc->dr_lmb_enabled) {
2203 error_setg(errp, "Memory hotplug not supported for this machine");
2204 return;
2205 }
2206 node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP, errp);
2207 if (*errp) {
2208 return;
2209 }
2210 if (node < 0 || node >= MAX_NODES) {
2211 error_setg(errp, "Invaild node %d", node);
2212 return;
2213 }
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231 if (nb_numa_nodes && !numa_info[node].node_mem) {
2232 error_setg(errp, "Can't hotplug memory to memory-less node %d",
2233 node);
2234 return;
2235 }
2236
2237 spapr_memory_plug(hotplug_dev, dev, node, errp);
2238 }
2239}
2240
2241static void spapr_machine_device_unplug(HotplugHandler *hotplug_dev,
2242 DeviceState *dev, Error **errp)
2243{
2244 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2245 error_setg(errp, "Memory hot unplug not supported by sPAPR");
2246 }
2247}
2248
2249static HotplugHandler *spapr_get_hotpug_handler(MachineState *machine,
2250 DeviceState *dev)
2251{
2252 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2253 return HOTPLUG_HANDLER(machine);
2254 }
2255 return NULL;
2256}
2257
2258static unsigned spapr_cpu_index_to_socket_id(unsigned cpu_index)
2259{
2260
2261
2262 return cpu_index / smp_threads / smp_cores;
2263}
2264
2265static void spapr_machine_class_init(ObjectClass *oc, void *data)
2266{
2267 MachineClass *mc = MACHINE_CLASS(oc);
2268 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(oc);
2269 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
2270 NMIClass *nc = NMI_CLASS(oc);
2271 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
2272
2273 mc->desc = "pSeries Logical Partition (PAPR compliant)";
2274
2275
2276
2277
2278
2279
2280 mc->init = ppc_spapr_init;
2281 mc->reset = ppc_spapr_reset;
2282 mc->block_default_type = IF_SCSI;
2283 mc->max_cpus = MAX_CPUMASK_BITS;
2284 mc->no_parallel = 1;
2285 mc->default_boot_order = "";
2286 mc->default_ram_size = 512 * M_BYTE;
2287 mc->kvm_type = spapr_kvm_type;
2288 mc->has_dynamic_sysbus = true;
2289 mc->pci_allow_0_address = true;
2290 mc->get_hotplug_handler = spapr_get_hotpug_handler;
2291 hc->plug = spapr_machine_device_plug;
2292 hc->unplug = spapr_machine_device_unplug;
2293 mc->cpu_index_to_socket_id = spapr_cpu_index_to_socket_id;
2294
2295 smc->dr_lmb_enabled = true;
2296 fwc->get_dev_path = spapr_get_fw_dev_path;
2297 nc->nmi_monitor_handler = spapr_nmi;
2298}
2299
2300static const TypeInfo spapr_machine_info = {
2301 .name = TYPE_SPAPR_MACHINE,
2302 .parent = TYPE_MACHINE,
2303 .abstract = true,
2304 .instance_size = sizeof(sPAPRMachineState),
2305 .instance_init = spapr_machine_initfn,
2306 .instance_finalize = spapr_machine_finalizefn,
2307 .class_size = sizeof(sPAPRMachineClass),
2308 .class_init = spapr_machine_class_init,
2309 .interfaces = (InterfaceInfo[]) {
2310 { TYPE_FW_PATH_PROVIDER },
2311 { TYPE_NMI },
2312 { TYPE_HOTPLUG_HANDLER },
2313 { }
2314 },
2315};
2316
2317#define DEFINE_SPAPR_MACHINE(suffix, verstr, latest) \
2318 static void spapr_machine_##suffix##_class_init(ObjectClass *oc, \
2319 void *data) \
2320 { \
2321 MachineClass *mc = MACHINE_CLASS(oc); \
2322 spapr_machine_##suffix##_class_options(mc); \
2323 if (latest) { \
2324 mc->alias = "pseries"; \
2325 mc->is_default = 1; \
2326 } \
2327 } \
2328 static void spapr_machine_##suffix##_instance_init(Object *obj) \
2329 { \
2330 MachineState *machine = MACHINE(obj); \
2331 spapr_machine_##suffix##_instance_options(machine); \
2332 } \
2333 static const TypeInfo spapr_machine_##suffix##_info = { \
2334 .name = MACHINE_TYPE_NAME("pseries-" verstr), \
2335 .parent = TYPE_SPAPR_MACHINE, \
2336 .class_init = spapr_machine_##suffix##_class_init, \
2337 .instance_init = spapr_machine_##suffix##_instance_init, \
2338 }; \
2339 static void spapr_machine_register_##suffix(void) \
2340 { \
2341 type_register(&spapr_machine_##suffix##_info); \
2342 } \
2343 type_init(spapr_machine_register_##suffix)
2344
2345
2346
2347
2348static void spapr_machine_2_6_instance_options(MachineState *machine)
2349{
2350}
2351
2352static void spapr_machine_2_6_class_options(MachineClass *mc)
2353{
2354
2355}
2356
2357DEFINE_SPAPR_MACHINE(2_6, "2.6", true);
2358
2359
2360
2361
2362#define SPAPR_COMPAT_2_5 \
2363 HW_COMPAT_2_5 \
2364 { \
2365 .driver = "spapr-vlan", \
2366 .property = "use-rx-buffer-pools", \
2367 .value = "off", \
2368 },
2369
2370static void spapr_machine_2_5_instance_options(MachineState *machine)
2371{
2372}
2373
2374static void spapr_machine_2_5_class_options(MachineClass *mc)
2375{
2376 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2377
2378 spapr_machine_2_6_class_options(mc);
2379 smc->use_ohci_by_default = true;
2380 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_5);
2381}
2382
2383DEFINE_SPAPR_MACHINE(2_5, "2.5", false);
2384
2385
2386
2387
2388#define SPAPR_COMPAT_2_4 \
2389 SPAPR_COMPAT_2_5 \
2390 HW_COMPAT_2_4
2391
2392static void spapr_machine_2_4_instance_options(MachineState *machine)
2393{
2394 spapr_machine_2_5_instance_options(machine);
2395}
2396
2397static void spapr_machine_2_4_class_options(MachineClass *mc)
2398{
2399 sPAPRMachineClass *smc = SPAPR_MACHINE_CLASS(mc);
2400
2401 spapr_machine_2_5_class_options(mc);
2402 smc->dr_lmb_enabled = false;
2403 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_4);
2404}
2405
2406DEFINE_SPAPR_MACHINE(2_4, "2.4", false);
2407
2408
2409
2410
2411#define SPAPR_COMPAT_2_3 \
2412 SPAPR_COMPAT_2_4 \
2413 HW_COMPAT_2_3 \
2414 {\
2415 .driver = "spapr-pci-host-bridge",\
2416 .property = "dynamic-reconfiguration",\
2417 .value = "off",\
2418 },
2419
2420static void spapr_machine_2_3_instance_options(MachineState *machine)
2421{
2422 spapr_machine_2_4_instance_options(machine);
2423 savevm_skip_section_footers();
2424 global_state_set_optional();
2425 savevm_skip_configuration();
2426}
2427
2428static void spapr_machine_2_3_class_options(MachineClass *mc)
2429{
2430 spapr_machine_2_4_class_options(mc);
2431 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_3);
2432}
2433DEFINE_SPAPR_MACHINE(2_3, "2.3", false);
2434
2435
2436
2437
2438
2439#define SPAPR_COMPAT_2_2 \
2440 SPAPR_COMPAT_2_3 \
2441 HW_COMPAT_2_2 \
2442 {\
2443 .driver = TYPE_SPAPR_PCI_HOST_BRIDGE,\
2444 .property = "mem_win_size",\
2445 .value = "0x20000000",\
2446 },
2447
2448static void spapr_machine_2_2_instance_options(MachineState *machine)
2449{
2450 spapr_machine_2_3_instance_options(machine);
2451 machine->suppress_vmdesc = true;
2452}
2453
2454static void spapr_machine_2_2_class_options(MachineClass *mc)
2455{
2456 spapr_machine_2_3_class_options(mc);
2457 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_2);
2458}
2459DEFINE_SPAPR_MACHINE(2_2, "2.2", false);
2460
2461
2462
2463
2464#define SPAPR_COMPAT_2_1 \
2465 SPAPR_COMPAT_2_2 \
2466 HW_COMPAT_2_1
2467
2468static void spapr_machine_2_1_instance_options(MachineState *machine)
2469{
2470 spapr_machine_2_2_instance_options(machine);
2471}
2472
2473static void spapr_machine_2_1_class_options(MachineClass *mc)
2474{
2475 spapr_machine_2_2_class_options(mc);
2476 SET_MACHINE_COMPAT(mc, SPAPR_COMPAT_2_1);
2477}
2478DEFINE_SPAPR_MACHINE(2_1, "2.1", false);
2479
2480static void spapr_machine_register_types(void)
2481{
2482 type_register_static(&spapr_machine_info);
2483}
2484
2485type_init(spapr_machine_register_types)
2486