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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "hw/hw.h"
28#include "hw/char/serial.h"
29#include "hw/block/flash.h"
30#include "sysemu/sysemu.h"
31#include "hw/devices.h"
32#include "hw/boards.h"
33#include "sysemu/device_tree.h"
34#include "hw/loader.h"
35#include "elf.h"
36#include "qemu/error-report.h"
37#include "qemu/log.h"
38#include "exec/address-spaces.h"
39
40#include "hw/ppc/ppc.h"
41#include "hw/ppc/ppc4xx.h"
42#include "ppc405.h"
43
44#include "sysemu/block-backend.h"
45
46#define EPAPR_MAGIC (0x45504150)
47#define FLASH_SIZE (16 * 1024 * 1024)
48
49#define INTC_BASEADDR 0x81800000
50#define UART16550_BASEADDR 0x83e01003
51#define TIMER_BASEADDR 0x83c00000
52#define PFLASH_BASEADDR 0xfc000000
53
54#define TIMER_IRQ 3
55#define UART16550_IRQ 9
56
57static struct boot_info
58{
59 uint32_t bootstrap_pc;
60 uint32_t cmdline;
61 uint32_t fdt;
62 uint32_t ima_size;
63 void *vfdt;
64} boot_info;
65
66
67static void mmubooke_create_initial_mapping(CPUPPCState *env,
68 target_ulong va,
69 hwaddr pa)
70{
71 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
72
73 tlb->attr = 0;
74 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
75 tlb->size = 1U << 31;
76 tlb->EPN = va & TARGET_PAGE_MASK;
77 tlb->RPN = pa & TARGET_PAGE_MASK;
78 tlb->PID = 0;
79
80 tlb = &env->tlb.tlbe[1];
81 tlb->attr = 0;
82 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
83 tlb->size = 1U << 31;
84 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
85 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
86 tlb->PID = 0;
87}
88
89static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size,
90 int do_init,
91 const char *cpu_model,
92 uint32_t sysclk)
93{
94 PowerPCCPU *cpu;
95 CPUPPCState *env;
96 qemu_irq *irqs;
97
98 cpu = cpu_ppc_init(cpu_model);
99 if (cpu == NULL) {
100 fprintf(stderr, "Unable to initialize CPU!\n");
101 exit(1);
102 }
103 env = &cpu->env;
104
105 ppc_booke_timers_init(cpu, sysclk, 0);
106
107 ppc_dcr_init(env, NULL, NULL);
108
109
110 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
111 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
112 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
113 ppcuic_init(env, irqs, 0x0C0, 0, 1);
114 return cpu;
115}
116
117static void main_cpu_reset(void *opaque)
118{
119 PowerPCCPU *cpu = opaque;
120 CPUPPCState *env = &cpu->env;
121 struct boot_info *bi = env->load_info;
122
123 cpu_reset(CPU(cpu));
124
125
126
127
128
129
130
131
132
133 env->gpr[1] = (16<<20) - 8;
134
135 env->gpr[3] = bi->fdt;
136 env->nip = bi->bootstrap_pc;
137
138
139 mmubooke_create_initial_mapping(env, 0, 0);
140 env->gpr[6] = tswap32(EPAPR_MAGIC);
141 env->gpr[7] = bi->ima_size;
142}
143
144#define BINARY_DEVICE_TREE_FILE "virtex-ml507.dtb"
145static int xilinx_load_device_tree(hwaddr addr,
146 uint32_t ramsize,
147 hwaddr initrd_base,
148 hwaddr initrd_size,
149 const char *kernel_cmdline)
150{
151 char *path;
152 int fdt_size;
153 void *fdt = NULL;
154 int r;
155 const char *dtb_filename;
156
157 dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
158 if (dtb_filename) {
159 fdt = load_device_tree(dtb_filename, &fdt_size);
160 if (!fdt) {
161 error_report("Error while loading device tree file '%s'",
162 dtb_filename);
163 }
164 } else {
165
166 fdt = load_device_tree("ppc.dtb", &fdt_size);
167 if (!fdt) {
168 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
169 if (path) {
170 fdt = load_device_tree(path, &fdt_size);
171 g_free(path);
172 }
173 }
174 }
175 if (!fdt) {
176 return 0;
177 }
178
179 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
180 initrd_base);
181 if (r < 0) {
182 error_report("couldn't set /chosen/linux,initrd-start");
183 }
184
185 r = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
186 (initrd_base + initrd_size));
187 if (r < 0) {
188 error_report("couldn't set /chosen/linux,initrd-end");
189 }
190
191 r = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
192 if (r < 0)
193 fprintf(stderr, "couldn't set /chosen/bootargs\n");
194 cpu_physical_memory_write(addr, fdt, fdt_size);
195 return fdt_size;
196}
197
198static void virtex_init(MachineState *machine)
199{
200 ram_addr_t ram_size = machine->ram_size;
201 const char *kernel_filename = machine->kernel_filename;
202 const char *kernel_cmdline = machine->kernel_cmdline;
203 hwaddr initrd_base = 0;
204 int initrd_size = 0;
205 MemoryRegion *address_space_mem = get_system_memory();
206 DeviceState *dev;
207 PowerPCCPU *cpu;
208 CPUPPCState *env;
209 hwaddr ram_base = 0;
210 DriveInfo *dinfo;
211 MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
212 qemu_irq irq[32], *cpu_irq;
213 int kernel_size;
214 int i;
215
216
217 if (machine->cpu_model == NULL) {
218 machine->cpu_model = "440-Xilinx";
219 }
220
221 cpu = ppc440_init_xilinx(&ram_size, 1, machine->cpu_model, 400000000);
222 env = &cpu->env;
223 qemu_register_reset(main_cpu_reset, cpu);
224
225 memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size);
226 memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
227
228 dinfo = drive_get(IF_PFLASH, 0, 0);
229 pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE,
230 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
231 (64 * 1024), FLASH_SIZE >> 16,
232 1, 0x89, 0x18, 0x0000, 0x0, 1);
233
234 cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
235 dev = qdev_create(NULL, "xlnx.xps-intc");
236 qdev_prop_set_uint32(dev, "kind-of-intr", 0);
237 qdev_init_nofail(dev);
238 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
239 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq[0]);
240 for (i = 0; i < 32; i++) {
241 irq[i] = qdev_get_gpio_in(dev, i);
242 }
243
244 serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ],
245 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
246
247
248 dev = qdev_create(NULL, "xlnx.xps-timer");
249 qdev_prop_set_uint32(dev, "one-timer-only", 0);
250 qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
251 qdev_init_nofail(dev);
252 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
253 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
254
255 if (kernel_filename) {
256 uint64_t entry, low, high;
257 hwaddr boot_offset;
258
259
260 kernel_size = load_elf(kernel_filename, NULL, NULL,
261 &entry, &low, &high, 1, PPC_ELF_MACHINE,
262 0, 0);
263 boot_info.bootstrap_pc = entry & 0x00ffffff;
264
265 if (kernel_size < 0) {
266 boot_offset = 0x1200000;
267
268 kernel_size = load_image_targphys(kernel_filename,
269 boot_offset,
270 ram_size);
271 boot_info.bootstrap_pc = boot_offset;
272 high = boot_info.bootstrap_pc + kernel_size + 8192;
273 }
274
275 boot_info.ima_size = kernel_size;
276
277
278 if (machine->initrd_filename) {
279 initrd_base = high = ROUND_UP(high, 4);
280 initrd_size = load_image_targphys(machine->initrd_filename,
281 high, ram_size - high);
282
283 if (initrd_size < 0) {
284 error_report("couldn't load ram disk '%s'",
285 machine->initrd_filename);
286 exit(1);
287 }
288 high = ROUND_UP(high + initrd_size, 4);
289 }
290
291
292 boot_info.fdt = high + (8192 * 2);
293 boot_info.fdt &= ~8191;
294
295 xilinx_load_device_tree(boot_info.fdt, ram_size,
296 initrd_base, initrd_size,
297 kernel_cmdline);
298 }
299 env->load_info = &boot_info;
300}
301
302static void virtex_machine_init(MachineClass *mc)
303{
304 mc->desc = "Xilinx Virtex ML507 reference design";
305 mc->init = virtex_init;
306}
307
308DEFINE_MACHINE("virtex-ml507", virtex_machine_init)
309
