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14#ifndef HW_S390_PCI_BUS_H
15#define HW_S390_PCI_BUS_H
16
17#include <hw/pci/pci.h>
18#include <hw/pci/pci_host.h>
19#include "hw/s390x/sclp.h"
20#include "hw/s390x/s390_flic.h"
21#include "hw/s390x/css.h"
22
23#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
24#define FH_VIRT 0x00ff0000
25#define ENABLE_BIT_OFFSET 31
26#define FH_ENABLED (1 << ENABLE_BIT_OFFSET)
27#define S390_PCIPT_ADAPTER 2
28
29#define S390_PCI_HOST_BRIDGE(obj) \
30 OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
31
32#define HP_EVENT_TO_CONFIGURED 0x0301
33#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
34#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
35#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
36
37#define ERR_EVENT_INVALAS 0x1
38#define ERR_EVENT_OORANGE 0x2
39#define ERR_EVENT_INVALTF 0x3
40#define ERR_EVENT_TPROTE 0x4
41#define ERR_EVENT_APROTE 0x5
42#define ERR_EVENT_KEYE 0x6
43#define ERR_EVENT_INVALTE 0x7
44#define ERR_EVENT_INVALTL 0x8
45#define ERR_EVENT_TT 0x9
46#define ERR_EVENT_INVALMS 0xa
47#define ERR_EVENT_SERR 0xb
48#define ERR_EVENT_NOMSI 0x10
49#define ERR_EVENT_INVALBV 0x11
50#define ERR_EVENT_AIBV 0x12
51#define ERR_EVENT_AIRERR 0x13
52#define ERR_EVENT_FMBA 0x2a
53#define ERR_EVENT_FMBUP 0x2b
54#define ERR_EVENT_FMBPRO 0x2c
55#define ERR_EVENT_CCONF 0x30
56#define ERR_EVENT_SERVAC 0x3a
57#define ERR_EVENT_PERMERR 0x3b
58
59#define ERR_EVENT_Q_BIT 0x2
60#define ERR_EVENT_MVN_OFFSET 16
61
62#define ZPCI_MSI_VEC_BITS 11
63#define ZPCI_MSI_VEC_MASK 0x7ff
64
65#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
66#define ZPCI_SDMA_ADDR 0x100000000ULL
67#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
68
69#define PAGE_SHIFT 12
70#define PAGE_MASK (~(PAGE_SIZE-1))
71#define PAGE_DEFAULT_ACC 0
72#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
73
74
75enum ZpciIoatDtype {
76 ZPCI_IOTA_STO = 0,
77 ZPCI_IOTA_RTTO = 1,
78 ZPCI_IOTA_RSTO = 2,
79 ZPCI_IOTA_RFTO = 3,
80 ZPCI_IOTA_PFAA = 4,
81 ZPCI_IOTA_IOPFAA = 5,
82 ZPCI_IOTA_IOPTO = 7
83};
84
85#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
86#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
87#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
88#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
89#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
90#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
91#define ZPCI_IOTA_FS_4K 0
92#define ZPCI_IOTA_FS_1M 1
93#define ZPCI_IOTA_FS_2G 2
94#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
95
96#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
97#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
98#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
99#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
100#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
101 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
102
103
104#define ZPCI_INDEX_MASK 0x7ffULL
105
106#define ZPCI_TABLE_TYPE_MASK 0xc
107#define ZPCI_TABLE_TYPE_RFX 0xc
108#define ZPCI_TABLE_TYPE_RSX 0x8
109#define ZPCI_TABLE_TYPE_RTX 0x4
110#define ZPCI_TABLE_TYPE_SX 0x0
111
112#define ZPCI_TABLE_LEN_RFX 0x3
113#define ZPCI_TABLE_LEN_RSX 0x3
114#define ZPCI_TABLE_LEN_RTX 0x3
115
116#define ZPCI_TABLE_OFFSET_MASK 0xc0
117#define ZPCI_TABLE_SIZE 0x4000
118#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
119#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
120#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
121
122#define ZPCI_TABLE_BITS 11
123#define ZPCI_PT_BITS 8
124#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
125#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
126
127#define ZPCI_RTE_FLAG_MASK 0x3fffULL
128#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
129#define ZPCI_STE_FLAG_MASK 0x7ffULL
130#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
131
132
133#define ZPCI_PTE_VALID_MASK 0x400
134#define ZPCI_PTE_INVALID 0x400
135#define ZPCI_PTE_VALID 0x000
136#define ZPCI_PT_SIZE 0x800
137#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
138#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
139#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
140
141#define ZPCI_PTE_FLAG_MASK 0xfffULL
142#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
143
144
145#define ZPCI_TABLE_VALID 0x00
146#define ZPCI_TABLE_INVALID 0x20
147#define ZPCI_TABLE_PROTECTED 0x200
148#define ZPCI_TABLE_UNPROTECTED 0x000
149
150#define ZPCI_TABLE_VALID_MASK 0x20
151#define ZPCI_TABLE_PROT_MASK 0x200
152
153typedef struct SeiContainer {
154 QTAILQ_ENTRY(SeiContainer) link;
155 uint32_t fid;
156 uint32_t fh;
157 uint8_t cc;
158 uint16_t pec;
159 uint64_t faddr;
160 uint32_t e;
161} SeiContainer;
162
163typedef struct PciCcdfErr {
164 uint32_t reserved1;
165 uint32_t fh;
166 uint32_t fid;
167 uint32_t e;
168 uint64_t faddr;
169 uint32_t reserved3;
170 uint16_t reserved4;
171 uint16_t pec;
172} QEMU_PACKED PciCcdfErr;
173
174typedef struct PciCcdfAvail {
175 uint32_t reserved1;
176 uint32_t fh;
177 uint32_t fid;
178 uint32_t reserved2;
179 uint32_t reserved3;
180 uint32_t reserved4;
181 uint32_t reserved5;
182 uint16_t reserved6;
183 uint16_t pec;
184} QEMU_PACKED PciCcdfAvail;
185
186typedef struct ChscSeiNt2Res {
187 uint16_t length;
188 uint16_t code;
189 uint16_t reserved1;
190 uint8_t reserved2;
191 uint8_t nt;
192 uint8_t flags;
193 uint8_t reserved3;
194 uint8_t reserved4;
195 uint8_t cc;
196 uint32_t reserved5[13];
197 uint8_t ccdf[4016];
198} QEMU_PACKED ChscSeiNt2Res;
199
200typedef struct PciCfgSccb {
201 SCCBHeader header;
202 uint8_t atype;
203 uint8_t reserved1;
204 uint16_t reserved2;
205 uint32_t aid;
206} QEMU_PACKED PciCfgSccb;
207
208typedef struct S390MsixInfo {
209 bool available;
210 uint8_t table_bar;
211 uint8_t pba_bar;
212 uint16_t entries;
213 uint32_t table_offset;
214 uint32_t pba_offset;
215} S390MsixInfo;
216
217typedef struct S390PCIBusDevice {
218 PCIDevice *pdev;
219 bool configured;
220 bool error_state;
221 bool lgstg_blocked;
222 uint32_t fh;
223 uint32_t fid;
224 uint64_t g_iota;
225 uint64_t pba;
226 uint64_t pal;
227 uint64_t fmb_addr;
228 uint8_t isc;
229 uint16_t noi;
230 uint8_t sum;
231 S390MsixInfo msix;
232 AdapterRoutes routes;
233 AddressSpace as;
234 MemoryRegion mr;
235 MemoryRegion iommu_mr;
236 IndAddr *summary_ind;
237 IndAddr *indicator;
238} S390PCIBusDevice;
239
240typedef struct S390pciState {
241 PCIHostState parent_obj;
242 S390PCIBusDevice pbdev[PCI_SLOT_MAX];
243 AddressSpace msix_notify_as;
244 MemoryRegion msix_notify_mr;
245 QTAILQ_HEAD(, SeiContainer) pending_sei;
246} S390pciState;
247
248int chsc_sei_nt2_get_event(void *res);
249int chsc_sei_nt2_have_event(void);
250void s390_pci_sclp_configure(int configure, SCCB *sccb);
251void s390_pcihost_iommu_configure(S390PCIBusDevice *pbdev, bool enable);
252S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
253S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
254S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
255
256#endif
257
