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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "hw/scsi/scsi.h"
31#include <block/scsi.h>
32#include "hw/pci/msi.h"
33#include "vmw_pvscsi.h"
34#include "trace.h"
35
36
37#define PVSCSI_USE_64BIT (true)
38#define PVSCSI_PER_VECTOR_MASK (false)
39
40#define PVSCSI_MAX_DEVS (64)
41#define PVSCSI_MSIX_NUM_VECTORS (1)
42
43#define PVSCSI_MAX_CMD_DATA_WORDS \
44 (sizeof(PVSCSICmdDescSetupRings)/sizeof(uint32_t))
45
46#define RS_GET_FIELD(m, field) \
47 (ldl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
48 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field)))
49#define RS_SET_FIELD(m, field, val) \
50 (stl_le_pci_dma(&container_of(m, PVSCSIState, rings)->parent_obj, \
51 (m)->rs_pa + offsetof(struct PVSCSIRingsState, field), val))
52
53typedef struct PVSCSIClass {
54 PCIDeviceClass parent_class;
55 DeviceRealize parent_dc_realize;
56} PVSCSIClass;
57
58#define TYPE_PVSCSI "pvscsi"
59#define PVSCSI(obj) OBJECT_CHECK(PVSCSIState, (obj), TYPE_PVSCSI)
60
61#define PVSCSI_DEVICE_CLASS(klass) \
62 OBJECT_CLASS_CHECK(PVSCSIClass, (klass), TYPE_PVSCSI)
63#define PVSCSI_DEVICE_GET_CLASS(obj) \
64 OBJECT_GET_CLASS(PVSCSIClass, (obj), TYPE_PVSCSI)
65
66
67#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT 0
68#define PVSCSI_COMPAT_OLD_PCI_CONFIGURATION \
69 (1 << PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT)
70#define PVSCSI_COMPAT_DISABLE_PCIE_BIT 1
71#define PVSCSI_COMPAT_DISABLE_PCIE \
72 (1 << PVSCSI_COMPAT_DISABLE_PCIE_BIT)
73
74#define PVSCSI_USE_OLD_PCI_CONFIGURATION(s) \
75 ((s)->compat_flags & PVSCSI_COMPAT_OLD_PCI_CONFIGURATION)
76#define PVSCSI_MSI_OFFSET(s) \
77 (PVSCSI_USE_OLD_PCI_CONFIGURATION(s) ? 0x50 : 0x7c)
78#define PVSCSI_EXP_EP_OFFSET (0x40)
79
80typedef struct PVSCSIRingInfo {
81 uint64_t rs_pa;
82 uint32_t txr_len_mask;
83 uint32_t rxr_len_mask;
84 uint32_t msg_len_mask;
85 uint64_t req_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
86 uint64_t cmp_ring_pages_pa[PVSCSI_SETUP_RINGS_MAX_NUM_PAGES];
87 uint64_t msg_ring_pages_pa[PVSCSI_SETUP_MSG_RING_MAX_NUM_PAGES];
88 uint64_t consumed_ptr;
89 uint64_t filled_cmp_ptr;
90 uint64_t filled_msg_ptr;
91} PVSCSIRingInfo;
92
93typedef struct PVSCSISGState {
94 hwaddr elemAddr;
95 hwaddr dataAddr;
96 uint32_t resid;
97} PVSCSISGState;
98
99typedef QTAILQ_HEAD(, PVSCSIRequest) PVSCSIRequestList;
100
101typedef struct {
102 PCIDevice parent_obj;
103 MemoryRegion io_space;
104 SCSIBus bus;
105 QEMUBH *completion_worker;
106 PVSCSIRequestList pending_queue;
107 PVSCSIRequestList completion_queue;
108
109 uint64_t reg_interrupt_status;
110 uint64_t reg_interrupt_enabled;
111 uint64_t reg_command_status;
112
113
114 uint64_t curr_cmd;
115 uint32_t curr_cmd_data_cntr;
116
117
118 uint32_t curr_cmd_data[PVSCSI_MAX_CMD_DATA_WORDS];
119
120 uint8_t rings_info_valid;
121 uint8_t msg_ring_info_valid;
122 uint8_t use_msg;
123
124 uint8_t msi_used;
125
126 PVSCSIRingInfo rings;
127 uint32_t resetting;
128
129 uint32_t compat_flags;
130} PVSCSIState;
131
132typedef struct PVSCSIRequest {
133 SCSIRequest *sreq;
134 PVSCSIState *dev;
135 uint8_t sense_key;
136 uint8_t completed;
137 int lun;
138 QEMUSGList sgl;
139 PVSCSISGState sg;
140 struct PVSCSIRingReqDesc req;
141 struct PVSCSIRingCmpDesc cmp;
142 QTAILQ_ENTRY(PVSCSIRequest) next;
143} PVSCSIRequest;
144
145
146static int
147pvscsi_log2(uint32_t input)
148{
149 int log = 0;
150 assert(input > 0);
151 while (input >> ++log) {
152 }
153 return log;
154}
155
156static void
157pvscsi_ring_init_data(PVSCSIRingInfo *m, PVSCSICmdDescSetupRings *ri)
158{
159 int i;
160 uint32_t txr_len_log2, rxr_len_log2;
161 uint32_t req_ring_size, cmp_ring_size;
162 m->rs_pa = ri->ringsStatePPN << VMW_PAGE_SHIFT;
163
164 req_ring_size = ri->reqRingNumPages * PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
165 cmp_ring_size = ri->cmpRingNumPages * PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
166 txr_len_log2 = pvscsi_log2(req_ring_size - 1);
167 rxr_len_log2 = pvscsi_log2(cmp_ring_size - 1);
168
169 m->txr_len_mask = MASK(txr_len_log2);
170 m->rxr_len_mask = MASK(rxr_len_log2);
171
172 m->consumed_ptr = 0;
173 m->filled_cmp_ptr = 0;
174
175 for (i = 0; i < ri->reqRingNumPages; i++) {
176 m->req_ring_pages_pa[i] = ri->reqRingPPNs[i] << VMW_PAGE_SHIFT;
177 }
178
179 for (i = 0; i < ri->cmpRingNumPages; i++) {
180 m->cmp_ring_pages_pa[i] = ri->cmpRingPPNs[i] << VMW_PAGE_SHIFT;
181 }
182
183 RS_SET_FIELD(m, reqProdIdx, 0);
184 RS_SET_FIELD(m, reqConsIdx, 0);
185 RS_SET_FIELD(m, reqNumEntriesLog2, txr_len_log2);
186
187 RS_SET_FIELD(m, cmpProdIdx, 0);
188 RS_SET_FIELD(m, cmpConsIdx, 0);
189 RS_SET_FIELD(m, cmpNumEntriesLog2, rxr_len_log2);
190
191 trace_pvscsi_ring_init_data(txr_len_log2, rxr_len_log2);
192
193
194 smp_wmb();
195}
196
197static void
198pvscsi_ring_init_msg(PVSCSIRingInfo *m, PVSCSICmdDescSetupMsgRing *ri)
199{
200 int i;
201 uint32_t len_log2;
202 uint32_t ring_size;
203
204 ring_size = ri->numPages * PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
205 len_log2 = pvscsi_log2(ring_size - 1);
206
207 m->msg_len_mask = MASK(len_log2);
208
209 m->filled_msg_ptr = 0;
210
211 for (i = 0; i < ri->numPages; i++) {
212 m->msg_ring_pages_pa[i] = ri->ringPPNs[i] << VMW_PAGE_SHIFT;
213 }
214
215 RS_SET_FIELD(m, msgProdIdx, 0);
216 RS_SET_FIELD(m, msgConsIdx, 0);
217 RS_SET_FIELD(m, msgNumEntriesLog2, len_log2);
218
219 trace_pvscsi_ring_init_msg(len_log2);
220
221
222 smp_wmb();
223}
224
225static void
226pvscsi_ring_cleanup(PVSCSIRingInfo *mgr)
227{
228 mgr->rs_pa = 0;
229 mgr->txr_len_mask = 0;
230 mgr->rxr_len_mask = 0;
231 mgr->msg_len_mask = 0;
232 mgr->consumed_ptr = 0;
233 mgr->filled_cmp_ptr = 0;
234 mgr->filled_msg_ptr = 0;
235 memset(mgr->req_ring_pages_pa, 0, sizeof(mgr->req_ring_pages_pa));
236 memset(mgr->cmp_ring_pages_pa, 0, sizeof(mgr->cmp_ring_pages_pa));
237 memset(mgr->msg_ring_pages_pa, 0, sizeof(mgr->msg_ring_pages_pa));
238}
239
240static hwaddr
241pvscsi_ring_pop_req_descr(PVSCSIRingInfo *mgr)
242{
243 uint32_t ready_ptr = RS_GET_FIELD(mgr, reqProdIdx);
244
245 if (ready_ptr != mgr->consumed_ptr) {
246 uint32_t next_ready_ptr =
247 mgr->consumed_ptr++ & mgr->txr_len_mask;
248 uint32_t next_ready_page =
249 next_ready_ptr / PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
250 uint32_t inpage_idx =
251 next_ready_ptr % PVSCSI_MAX_NUM_REQ_ENTRIES_PER_PAGE;
252
253 return mgr->req_ring_pages_pa[next_ready_page] +
254 inpage_idx * sizeof(PVSCSIRingReqDesc);
255 } else {
256 return 0;
257 }
258}
259
260static void
261pvscsi_ring_flush_req(PVSCSIRingInfo *mgr)
262{
263 RS_SET_FIELD(mgr, reqConsIdx, mgr->consumed_ptr);
264}
265
266static hwaddr
267pvscsi_ring_pop_cmp_descr(PVSCSIRingInfo *mgr)
268{
269
270
271
272
273
274
275
276
277 uint32_t free_cmp_ptr =
278 mgr->filled_cmp_ptr++ & mgr->rxr_len_mask;
279 uint32_t free_cmp_page =
280 free_cmp_ptr / PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
281 uint32_t inpage_idx =
282 free_cmp_ptr % PVSCSI_MAX_NUM_CMP_ENTRIES_PER_PAGE;
283 return mgr->cmp_ring_pages_pa[free_cmp_page] +
284 inpage_idx * sizeof(PVSCSIRingCmpDesc);
285}
286
287static hwaddr
288pvscsi_ring_pop_msg_descr(PVSCSIRingInfo *mgr)
289{
290 uint32_t free_msg_ptr =
291 mgr->filled_msg_ptr++ & mgr->msg_len_mask;
292 uint32_t free_msg_page =
293 free_msg_ptr / PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
294 uint32_t inpage_idx =
295 free_msg_ptr % PVSCSI_MAX_NUM_MSG_ENTRIES_PER_PAGE;
296 return mgr->msg_ring_pages_pa[free_msg_page] +
297 inpage_idx * sizeof(PVSCSIRingMsgDesc);
298}
299
300static void
301pvscsi_ring_flush_cmp(PVSCSIRingInfo *mgr)
302{
303
304 smp_wmb();
305
306 trace_pvscsi_ring_flush_cmp(mgr->filled_cmp_ptr);
307
308 RS_SET_FIELD(mgr, cmpProdIdx, mgr->filled_cmp_ptr);
309}
310
311static bool
312pvscsi_ring_msg_has_room(PVSCSIRingInfo *mgr)
313{
314 uint32_t prodIdx = RS_GET_FIELD(mgr, msgProdIdx);
315 uint32_t consIdx = RS_GET_FIELD(mgr, msgConsIdx);
316
317 return (prodIdx - consIdx) < (mgr->msg_len_mask + 1);
318}
319
320static void
321pvscsi_ring_flush_msg(PVSCSIRingInfo *mgr)
322{
323
324 smp_wmb();
325
326 trace_pvscsi_ring_flush_msg(mgr->filled_msg_ptr);
327
328 RS_SET_FIELD(mgr, msgProdIdx, mgr->filled_msg_ptr);
329}
330
331static void
332pvscsi_reset_state(PVSCSIState *s)
333{
334 s->curr_cmd = PVSCSI_CMD_FIRST;
335 s->curr_cmd_data_cntr = 0;
336 s->reg_command_status = PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
337 s->reg_interrupt_status = 0;
338 pvscsi_ring_cleanup(&s->rings);
339 s->rings_info_valid = FALSE;
340 s->msg_ring_info_valid = FALSE;
341 QTAILQ_INIT(&s->pending_queue);
342 QTAILQ_INIT(&s->completion_queue);
343}
344
345static void
346pvscsi_update_irq_status(PVSCSIState *s)
347{
348 PCIDevice *d = PCI_DEVICE(s);
349 bool should_raise = s->reg_interrupt_enabled & s->reg_interrupt_status;
350
351 trace_pvscsi_update_irq_level(should_raise, s->reg_interrupt_enabled,
352 s->reg_interrupt_status);
353
354 if (s->msi_used && msi_enabled(d)) {
355 if (should_raise) {
356 trace_pvscsi_update_irq_msi();
357 msi_notify(d, PVSCSI_VECTOR_COMPLETION);
358 }
359 return;
360 }
361
362 pci_set_irq(d, !!should_raise);
363}
364
365static void
366pvscsi_raise_completion_interrupt(PVSCSIState *s)
367{
368 s->reg_interrupt_status |= PVSCSI_INTR_CMPL_0;
369
370
371 smp_wmb();
372
373 pvscsi_update_irq_status(s);
374}
375
376static void
377pvscsi_raise_message_interrupt(PVSCSIState *s)
378{
379 s->reg_interrupt_status |= PVSCSI_INTR_MSG_0;
380
381
382 smp_wmb();
383
384 pvscsi_update_irq_status(s);
385}
386
387static void
388pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc)
389{
390 hwaddr cmp_descr_pa;
391
392 cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings);
393 trace_pvscsi_cmp_ring_put(cmp_descr_pa);
394 cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc,
395 sizeof(*cmp_desc));
396}
397
398static void
399pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc)
400{
401 hwaddr msg_descr_pa;
402
403 msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings);
404 trace_pvscsi_msg_ring_put(msg_descr_pa);
405 cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc,
406 sizeof(*msg_desc));
407}
408
409static void
410pvscsi_process_completion_queue(void *opaque)
411{
412 PVSCSIState *s = opaque;
413 PVSCSIRequest *pvscsi_req;
414 bool has_completed = false;
415
416 while (!QTAILQ_EMPTY(&s->completion_queue)) {
417 pvscsi_req = QTAILQ_FIRST(&s->completion_queue);
418 QTAILQ_REMOVE(&s->completion_queue, pvscsi_req, next);
419 pvscsi_cmp_ring_put(s, &pvscsi_req->cmp);
420 g_free(pvscsi_req);
421 has_completed = true;
422 }
423
424 if (has_completed) {
425 pvscsi_ring_flush_cmp(&s->rings);
426 pvscsi_raise_completion_interrupt(s);
427 }
428}
429
430static void
431pvscsi_reset_adapter(PVSCSIState *s)
432{
433 s->resetting++;
434 qbus_reset_all_fn(&s->bus);
435 s->resetting--;
436 pvscsi_process_completion_queue(s);
437 assert(QTAILQ_EMPTY(&s->pending_queue));
438 pvscsi_reset_state(s);
439}
440
441static void
442pvscsi_schedule_completion_processing(PVSCSIState *s)
443{
444
445 if (!QTAILQ_EMPTY(&s->completion_queue)) {
446 qemu_bh_schedule(s->completion_worker);
447 }
448}
449
450static void
451pvscsi_complete_request(PVSCSIState *s, PVSCSIRequest *r)
452{
453 assert(!r->completed);
454
455 trace_pvscsi_complete_request(r->cmp.context, r->cmp.dataLen,
456 r->sense_key);
457 if (r->sreq != NULL) {
458 scsi_req_unref(r->sreq);
459 r->sreq = NULL;
460 }
461 r->completed = 1;
462 QTAILQ_REMOVE(&s->pending_queue, r, next);
463 QTAILQ_INSERT_TAIL(&s->completion_queue, r, next);
464 pvscsi_schedule_completion_processing(s);
465}
466
467static QEMUSGList *pvscsi_get_sg_list(SCSIRequest *r)
468{
469 PVSCSIRequest *req = r->hba_private;
470
471 trace_pvscsi_get_sg_list(req->sgl.nsg, req->sgl.size);
472
473 return &req->sgl;
474}
475
476static void
477pvscsi_get_next_sg_elem(PVSCSISGState *sg)
478{
479 struct PVSCSISGElement elem;
480
481 cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem));
482 if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) {
483
484
485
486
487
488
489 trace_pvscsi_get_next_sg_elem(elem.flags);
490 }
491
492 sg->elemAddr += sizeof(elem);
493 sg->dataAddr = elem.addr;
494 sg->resid = elem.length;
495}
496
497static void
498pvscsi_write_sense(PVSCSIRequest *r, uint8_t *sense, int len)
499{
500 r->cmp.senseLen = MIN(r->req.senseLen, len);
501 r->sense_key = sense[(sense[0] & 2) ? 1 : 2];
502 cpu_physical_memory_write(r->req.senseAddr, sense, r->cmp.senseLen);
503}
504
505static void
506pvscsi_command_complete(SCSIRequest *req, uint32_t status, size_t resid)
507{
508 PVSCSIRequest *pvscsi_req = req->hba_private;
509 PVSCSIState *s;
510
511 if (!pvscsi_req) {
512 trace_pvscsi_command_complete_not_found(req->tag);
513 return;
514 }
515 s = pvscsi_req->dev;
516
517 if (resid) {
518
519 trace_pvscsi_command_complete_data_run();
520 pvscsi_req->cmp.hostStatus = BTSTAT_DATARUN;
521 }
522
523 pvscsi_req->cmp.scsiStatus = status;
524 if (pvscsi_req->cmp.scsiStatus == CHECK_CONDITION) {
525 uint8_t sense[SCSI_SENSE_BUF_SIZE];
526 int sense_len =
527 scsi_req_get_sense(pvscsi_req->sreq, sense, sizeof(sense));
528
529 trace_pvscsi_command_complete_sense_len(sense_len);
530 pvscsi_write_sense(pvscsi_req, sense, sense_len);
531 }
532 qemu_sglist_destroy(&pvscsi_req->sgl);
533 pvscsi_complete_request(s, pvscsi_req);
534}
535
536static void
537pvscsi_send_msg(PVSCSIState *s, SCSIDevice *dev, uint32_t msg_type)
538{
539 if (s->msg_ring_info_valid && pvscsi_ring_msg_has_room(&s->rings)) {
540 PVSCSIMsgDescDevStatusChanged msg = {0};
541
542 msg.type = msg_type;
543 msg.bus = dev->channel;
544 msg.target = dev->id;
545 msg.lun[1] = dev->lun;
546
547 pvscsi_msg_ring_put(s, (PVSCSIRingMsgDesc *)&msg);
548 pvscsi_ring_flush_msg(&s->rings);
549 pvscsi_raise_message_interrupt(s);
550 }
551}
552
553static void
554pvscsi_hotplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
555{
556 PVSCSIState *s = PVSCSI(hotplug_dev);
557
558 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_ADDED);
559}
560
561static void
562pvscsi_hot_unplug(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp)
563{
564 PVSCSIState *s = PVSCSI(hotplug_dev);
565
566 pvscsi_send_msg(s, SCSI_DEVICE(dev), PVSCSI_MSG_DEV_REMOVED);
567 qdev_simple_device_unplug_cb(hotplug_dev, dev, errp);
568}
569
570static void
571pvscsi_request_cancelled(SCSIRequest *req)
572{
573 PVSCSIRequest *pvscsi_req = req->hba_private;
574 PVSCSIState *s = pvscsi_req->dev;
575
576 if (pvscsi_req->completed) {
577 return;
578 }
579
580 if (pvscsi_req->dev->resetting) {
581 pvscsi_req->cmp.hostStatus = BTSTAT_BUSRESET;
582 } else {
583 pvscsi_req->cmp.hostStatus = BTSTAT_ABORTQUEUE;
584 }
585
586 pvscsi_complete_request(s, pvscsi_req);
587}
588
589static SCSIDevice*
590pvscsi_device_find(PVSCSIState *s, int channel, int target,
591 uint8_t *requested_lun, uint8_t *target_lun)
592{
593 if (requested_lun[0] || requested_lun[2] || requested_lun[3] ||
594 requested_lun[4] || requested_lun[5] || requested_lun[6] ||
595 requested_lun[7] || (target > PVSCSI_MAX_DEVS)) {
596 return NULL;
597 } else {
598 *target_lun = requested_lun[1];
599 return scsi_device_find(&s->bus, channel, target, *target_lun);
600 }
601}
602
603static PVSCSIRequest *
604pvscsi_queue_pending_descriptor(PVSCSIState *s, SCSIDevice **d,
605 struct PVSCSIRingReqDesc *descr)
606{
607 PVSCSIRequest *pvscsi_req;
608 uint8_t lun;
609
610 pvscsi_req = g_malloc0(sizeof(*pvscsi_req));
611 pvscsi_req->dev = s;
612 pvscsi_req->req = *descr;
613 pvscsi_req->cmp.context = pvscsi_req->req.context;
614 QTAILQ_INSERT_TAIL(&s->pending_queue, pvscsi_req, next);
615
616 *d = pvscsi_device_find(s, descr->bus, descr->target, descr->lun, &lun);
617 if (*d) {
618 pvscsi_req->lun = lun;
619 }
620
621 return pvscsi_req;
622}
623
624static void
625pvscsi_convert_sglist(PVSCSIRequest *r)
626{
627 int chunk_size;
628 uint64_t data_length = r->req.dataLen;
629 PVSCSISGState sg = r->sg;
630 while (data_length) {
631 while (!sg.resid) {
632 pvscsi_get_next_sg_elem(&sg);
633 trace_pvscsi_convert_sglist(r->req.context, r->sg.dataAddr,
634 r->sg.resid);
635 }
636 assert(data_length > 0);
637 chunk_size = MIN((unsigned) data_length, sg.resid);
638 if (chunk_size) {
639 qemu_sglist_add(&r->sgl, sg.dataAddr, chunk_size);
640 }
641
642 sg.dataAddr += chunk_size;
643 data_length -= chunk_size;
644 sg.resid -= chunk_size;
645 }
646}
647
648static void
649pvscsi_build_sglist(PVSCSIState *s, PVSCSIRequest *r)
650{
651 PCIDevice *d = PCI_DEVICE(s);
652
653 pci_dma_sglist_init(&r->sgl, d, 1);
654 if (r->req.flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
655 pvscsi_convert_sglist(r);
656 } else {
657 qemu_sglist_add(&r->sgl, r->req.dataAddr, r->req.dataLen);
658 }
659}
660
661static void
662pvscsi_process_request_descriptor(PVSCSIState *s,
663 struct PVSCSIRingReqDesc *descr)
664{
665 SCSIDevice *d;
666 PVSCSIRequest *r = pvscsi_queue_pending_descriptor(s, &d, descr);
667 int64_t n;
668
669 trace_pvscsi_process_req_descr(descr->cdb[0], descr->context);
670
671 if (!d) {
672 r->cmp.hostStatus = BTSTAT_SELTIMEO;
673 trace_pvscsi_process_req_descr_unknown_device();
674 pvscsi_complete_request(s, r);
675 return;
676 }
677
678 if (descr->flags & PVSCSI_FLAG_CMD_WITH_SG_LIST) {
679 r->sg.elemAddr = descr->dataAddr;
680 }
681
682 r->sreq = scsi_req_new(d, descr->context, r->lun, descr->cdb, r);
683 if (r->sreq->cmd.mode == SCSI_XFER_FROM_DEV &&
684 (descr->flags & PVSCSI_FLAG_CMD_DIR_TODEVICE)) {
685 r->cmp.hostStatus = BTSTAT_BADMSG;
686 trace_pvscsi_process_req_descr_invalid_dir();
687 scsi_req_cancel(r->sreq);
688 return;
689 }
690 if (r->sreq->cmd.mode == SCSI_XFER_TO_DEV &&
691 (descr->flags & PVSCSI_FLAG_CMD_DIR_TOHOST)) {
692 r->cmp.hostStatus = BTSTAT_BADMSG;
693 trace_pvscsi_process_req_descr_invalid_dir();
694 scsi_req_cancel(r->sreq);
695 return;
696 }
697
698 pvscsi_build_sglist(s, r);
699 n = scsi_req_enqueue(r->sreq);
700
701 if (n) {
702 scsi_req_continue(r->sreq);
703 }
704}
705
706static void
707pvscsi_process_io(PVSCSIState *s)
708{
709 PVSCSIRingReqDesc descr;
710 hwaddr next_descr_pa;
711
712 assert(s->rings_info_valid);
713 while ((next_descr_pa = pvscsi_ring_pop_req_descr(&s->rings)) != 0) {
714
715
716 smp_rmb();
717
718 trace_pvscsi_process_io(next_descr_pa);
719 cpu_physical_memory_read(next_descr_pa, &descr, sizeof(descr));
720 pvscsi_process_request_descriptor(s, &descr);
721 }
722
723 pvscsi_ring_flush_req(&s->rings);
724}
725
726static void
727pvscsi_dbg_dump_tx_rings_config(PVSCSICmdDescSetupRings *rc)
728{
729 int i;
730 trace_pvscsi_tx_rings_ppn("Rings State", rc->ringsStatePPN);
731
732 trace_pvscsi_tx_rings_num_pages("Request Ring", rc->reqRingNumPages);
733 for (i = 0; i < rc->reqRingNumPages; i++) {
734 trace_pvscsi_tx_rings_ppn("Request Ring", rc->reqRingPPNs[i]);
735 }
736
737 trace_pvscsi_tx_rings_num_pages("Confirm Ring", rc->cmpRingNumPages);
738 for (i = 0; i < rc->cmpRingNumPages; i++) {
739 trace_pvscsi_tx_rings_ppn("Confirm Ring", rc->reqRingPPNs[i]);
740 }
741}
742
743static uint64_t
744pvscsi_on_cmd_config(PVSCSIState *s)
745{
746 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_CONFIG");
747 return PVSCSI_COMMAND_PROCESSING_FAILED;
748}
749
750static uint64_t
751pvscsi_on_cmd_unplug(PVSCSIState *s)
752{
753 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_DEVICE_UNPLUG");
754 return PVSCSI_COMMAND_PROCESSING_FAILED;
755}
756
757static uint64_t
758pvscsi_on_issue_scsi(PVSCSIState *s)
759{
760 trace_pvscsi_on_cmd_noimpl("PVSCSI_CMD_ISSUE_SCSI");
761 return PVSCSI_COMMAND_PROCESSING_FAILED;
762}
763
764static uint64_t
765pvscsi_on_cmd_setup_rings(PVSCSIState *s)
766{
767 PVSCSICmdDescSetupRings *rc =
768 (PVSCSICmdDescSetupRings *) s->curr_cmd_data;
769
770 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_RINGS");
771
772 pvscsi_dbg_dump_tx_rings_config(rc);
773 pvscsi_ring_init_data(&s->rings, rc);
774 s->rings_info_valid = TRUE;
775 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
776}
777
778static uint64_t
779pvscsi_on_cmd_abort(PVSCSIState *s)
780{
781 PVSCSICmdDescAbortCmd *cmd = (PVSCSICmdDescAbortCmd *) s->curr_cmd_data;
782 PVSCSIRequest *r, *next;
783
784 trace_pvscsi_on_cmd_abort(cmd->context, cmd->target);
785
786 QTAILQ_FOREACH_SAFE(r, &s->pending_queue, next, next) {
787 if (r->req.context == cmd->context) {
788 break;
789 }
790 }
791 if (r) {
792 assert(!r->completed);
793 r->cmp.hostStatus = BTSTAT_ABORTQUEUE;
794 scsi_req_cancel(r->sreq);
795 }
796
797 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
798}
799
800static uint64_t
801pvscsi_on_cmd_unknown(PVSCSIState *s)
802{
803 trace_pvscsi_on_cmd_unknown_data(s->curr_cmd_data[0]);
804 return PVSCSI_COMMAND_PROCESSING_FAILED;
805}
806
807static uint64_t
808pvscsi_on_cmd_reset_device(PVSCSIState *s)
809{
810 uint8_t target_lun = 0;
811 struct PVSCSICmdDescResetDevice *cmd =
812 (struct PVSCSICmdDescResetDevice *) s->curr_cmd_data;
813 SCSIDevice *sdev;
814
815 sdev = pvscsi_device_find(s, 0, cmd->target, cmd->lun, &target_lun);
816
817 trace_pvscsi_on_cmd_reset_dev(cmd->target, (int) target_lun, sdev);
818
819 if (sdev != NULL) {
820 s->resetting++;
821 device_reset(&sdev->qdev);
822 s->resetting--;
823 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
824 }
825
826 return PVSCSI_COMMAND_PROCESSING_FAILED;
827}
828
829static uint64_t
830pvscsi_on_cmd_reset_bus(PVSCSIState *s)
831{
832 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_RESET_BUS");
833
834 s->resetting++;
835 qbus_reset_all_fn(&s->bus);
836 s->resetting--;
837 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
838}
839
840static uint64_t
841pvscsi_on_cmd_setup_msg_ring(PVSCSIState *s)
842{
843 PVSCSICmdDescSetupMsgRing *rc =
844 (PVSCSICmdDescSetupMsgRing *) s->curr_cmd_data;
845
846 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_SETUP_MSG_RING");
847
848 if (!s->use_msg) {
849 return PVSCSI_COMMAND_PROCESSING_FAILED;
850 }
851
852 if (s->rings_info_valid) {
853 pvscsi_ring_init_msg(&s->rings, rc);
854 s->msg_ring_info_valid = TRUE;
855 }
856 return sizeof(PVSCSICmdDescSetupMsgRing) / sizeof(uint32_t);
857}
858
859static uint64_t
860pvscsi_on_cmd_adapter_reset(PVSCSIState *s)
861{
862 trace_pvscsi_on_cmd_arrived("PVSCSI_CMD_ADAPTER_RESET");
863
864 pvscsi_reset_adapter(s);
865 return PVSCSI_COMMAND_PROCESSING_SUCCEEDED;
866}
867
868static const struct {
869 int data_size;
870 uint64_t (*handler_fn)(PVSCSIState *s);
871} pvscsi_commands[] = {
872 [PVSCSI_CMD_FIRST] = {
873 .data_size = 0,
874 .handler_fn = pvscsi_on_cmd_unknown,
875 },
876
877
878 [PVSCSI_CMD_CONFIG] = {
879 .data_size = 6 * sizeof(uint32_t),
880 .handler_fn = pvscsi_on_cmd_config,
881 },
882
883
884 [PVSCSI_CMD_ISSUE_SCSI] = {
885 .data_size = 0,
886 .handler_fn = pvscsi_on_issue_scsi,
887 },
888
889
890 [PVSCSI_CMD_DEVICE_UNPLUG] = {
891 .data_size = 0,
892 .handler_fn = pvscsi_on_cmd_unplug,
893 },
894
895 [PVSCSI_CMD_SETUP_RINGS] = {
896 .data_size = sizeof(PVSCSICmdDescSetupRings),
897 .handler_fn = pvscsi_on_cmd_setup_rings,
898 },
899
900 [PVSCSI_CMD_RESET_DEVICE] = {
901 .data_size = sizeof(struct PVSCSICmdDescResetDevice),
902 .handler_fn = pvscsi_on_cmd_reset_device,
903 },
904
905 [PVSCSI_CMD_RESET_BUS] = {
906 .data_size = 0,
907 .handler_fn = pvscsi_on_cmd_reset_bus,
908 },
909
910 [PVSCSI_CMD_SETUP_MSG_RING] = {
911 .data_size = sizeof(PVSCSICmdDescSetupMsgRing),
912 .handler_fn = pvscsi_on_cmd_setup_msg_ring,
913 },
914
915 [PVSCSI_CMD_ADAPTER_RESET] = {
916 .data_size = 0,
917 .handler_fn = pvscsi_on_cmd_adapter_reset,
918 },
919
920 [PVSCSI_CMD_ABORT_CMD] = {
921 .data_size = sizeof(struct PVSCSICmdDescAbortCmd),
922 .handler_fn = pvscsi_on_cmd_abort,
923 },
924};
925
926static void
927pvscsi_do_command_processing(PVSCSIState *s)
928{
929 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
930
931 assert(s->curr_cmd < PVSCSI_CMD_LAST);
932 if (bytes_arrived >= pvscsi_commands[s->curr_cmd].data_size) {
933 s->reg_command_status = pvscsi_commands[s->curr_cmd].handler_fn(s);
934 s->curr_cmd = PVSCSI_CMD_FIRST;
935 s->curr_cmd_data_cntr = 0;
936 }
937}
938
939static void
940pvscsi_on_command_data(PVSCSIState *s, uint32_t value)
941{
942 size_t bytes_arrived = s->curr_cmd_data_cntr * sizeof(uint32_t);
943
944 assert(bytes_arrived < sizeof(s->curr_cmd_data));
945 s->curr_cmd_data[s->curr_cmd_data_cntr++] = value;
946
947 pvscsi_do_command_processing(s);
948}
949
950static void
951pvscsi_on_command(PVSCSIState *s, uint64_t cmd_id)
952{
953 if ((cmd_id > PVSCSI_CMD_FIRST) && (cmd_id < PVSCSI_CMD_LAST)) {
954 s->curr_cmd = cmd_id;
955 } else {
956 s->curr_cmd = PVSCSI_CMD_FIRST;
957 trace_pvscsi_on_cmd_unknown(cmd_id);
958 }
959
960 s->curr_cmd_data_cntr = 0;
961 s->reg_command_status = PVSCSI_COMMAND_NOT_ENOUGH_DATA;
962
963 pvscsi_do_command_processing(s);
964}
965
966static void
967pvscsi_io_write(void *opaque, hwaddr addr,
968 uint64_t val, unsigned size)
969{
970 PVSCSIState *s = opaque;
971
972 switch (addr) {
973 case PVSCSI_REG_OFFSET_COMMAND:
974 pvscsi_on_command(s, val);
975 break;
976
977 case PVSCSI_REG_OFFSET_COMMAND_DATA:
978 pvscsi_on_command_data(s, (uint32_t) val);
979 break;
980
981 case PVSCSI_REG_OFFSET_INTR_STATUS:
982 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_STATUS", val);
983 s->reg_interrupt_status &= ~val;
984 pvscsi_update_irq_status(s);
985 pvscsi_schedule_completion_processing(s);
986 break;
987
988 case PVSCSI_REG_OFFSET_INTR_MASK:
989 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_INTR_MASK", val);
990 s->reg_interrupt_enabled = val;
991 pvscsi_update_irq_status(s);
992 break;
993
994 case PVSCSI_REG_OFFSET_KICK_NON_RW_IO:
995 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_NON_RW_IO", val);
996 pvscsi_process_io(s);
997 break;
998
999 case PVSCSI_REG_OFFSET_KICK_RW_IO:
1000 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_KICK_RW_IO", val);
1001 pvscsi_process_io(s);
1002 break;
1003
1004 case PVSCSI_REG_OFFSET_DEBUG:
1005 trace_pvscsi_io_write("PVSCSI_REG_OFFSET_DEBUG", val);
1006 break;
1007
1008 default:
1009 trace_pvscsi_io_write_unknown(addr, size, val);
1010 break;
1011 }
1012
1013}
1014
1015static uint64_t
1016pvscsi_io_read(void *opaque, hwaddr addr, unsigned size)
1017{
1018 PVSCSIState *s = opaque;
1019
1020 switch (addr) {
1021 case PVSCSI_REG_OFFSET_INTR_STATUS:
1022 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_STATUS",
1023 s->reg_interrupt_status);
1024 return s->reg_interrupt_status;
1025
1026 case PVSCSI_REG_OFFSET_INTR_MASK:
1027 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_INTR_MASK",
1028 s->reg_interrupt_status);
1029 return s->reg_interrupt_enabled;
1030
1031 case PVSCSI_REG_OFFSET_COMMAND_STATUS:
1032 trace_pvscsi_io_read("PVSCSI_REG_OFFSET_COMMAND_STATUS",
1033 s->reg_interrupt_status);
1034 return s->reg_command_status;
1035
1036 default:
1037 trace_pvscsi_io_read_unknown(addr, size);
1038 return 0;
1039 }
1040}
1041
1042
1043static bool
1044pvscsi_init_msi(PVSCSIState *s)
1045{
1046 int res;
1047 PCIDevice *d = PCI_DEVICE(s);
1048
1049 res = msi_init(d, PVSCSI_MSI_OFFSET(s), PVSCSI_MSIX_NUM_VECTORS,
1050 PVSCSI_USE_64BIT, PVSCSI_PER_VECTOR_MASK);
1051 if (res < 0) {
1052 trace_pvscsi_init_msi_fail(res);
1053 s->msi_used = false;
1054 } else {
1055 s->msi_used = true;
1056 }
1057
1058 return s->msi_used;
1059}
1060
1061static void
1062pvscsi_cleanup_msi(PVSCSIState *s)
1063{
1064 PCIDevice *d = PCI_DEVICE(s);
1065
1066 if (s->msi_used) {
1067 msi_uninit(d);
1068 }
1069}
1070
1071static const MemoryRegionOps pvscsi_ops = {
1072 .read = pvscsi_io_read,
1073 .write = pvscsi_io_write,
1074 .endianness = DEVICE_LITTLE_ENDIAN,
1075 .impl = {
1076 .min_access_size = 4,
1077 .max_access_size = 4,
1078 },
1079};
1080
1081static const struct SCSIBusInfo pvscsi_scsi_info = {
1082 .tcq = true,
1083 .max_target = PVSCSI_MAX_DEVS,
1084 .max_channel = 0,
1085 .max_lun = 0,
1086
1087 .get_sg_list = pvscsi_get_sg_list,
1088 .complete = pvscsi_command_complete,
1089 .cancel = pvscsi_request_cancelled,
1090};
1091
1092static int
1093pvscsi_init(PCIDevice *pci_dev)
1094{
1095 PVSCSIState *s = PVSCSI(pci_dev);
1096
1097 trace_pvscsi_state("init");
1098
1099
1100 if (PVSCSI_USE_OLD_PCI_CONFIGURATION(s)) {
1101 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, 0x1000);
1102 } else {
1103 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
1104 PCI_VENDOR_ID_VMWARE);
1105 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
1106 PCI_DEVICE_ID_VMWARE_PVSCSI);
1107 pci_config_set_revision(pci_dev->config, 0x2);
1108 }
1109
1110
1111 pci_dev->config[PCI_LATENCY_TIMER] = 0xff;
1112
1113
1114 pci_config_set_interrupt_pin(pci_dev->config, 1);
1115
1116 memory_region_init_io(&s->io_space, OBJECT(s), &pvscsi_ops, s,
1117 "pvscsi-io", PVSCSI_MEM_SPACE_SIZE);
1118 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->io_space);
1119
1120 pvscsi_init_msi(s);
1121
1122 if (pci_is_express(pci_dev) && pci_bus_is_express(pci_dev->bus)) {
1123 pcie_endpoint_cap_init(pci_dev, PVSCSI_EXP_EP_OFFSET);
1124 }
1125
1126 s->completion_worker = qemu_bh_new(pvscsi_process_completion_queue, s);
1127 if (!s->completion_worker) {
1128 pvscsi_cleanup_msi(s);
1129 return -ENOMEM;
1130 }
1131
1132 scsi_bus_new(&s->bus, sizeof(s->bus), DEVICE(pci_dev),
1133 &pvscsi_scsi_info, NULL);
1134
1135 qbus_set_hotplug_handler(BUS(&s->bus), DEVICE(s), &error_abort);
1136 pvscsi_reset_state(s);
1137
1138 return 0;
1139}
1140
1141static void
1142pvscsi_uninit(PCIDevice *pci_dev)
1143{
1144 PVSCSIState *s = PVSCSI(pci_dev);
1145
1146 trace_pvscsi_state("uninit");
1147 qemu_bh_delete(s->completion_worker);
1148
1149 pvscsi_cleanup_msi(s);
1150}
1151
1152static void
1153pvscsi_reset(DeviceState *dev)
1154{
1155 PCIDevice *d = PCI_DEVICE(dev);
1156 PVSCSIState *s = PVSCSI(d);
1157
1158 trace_pvscsi_state("reset");
1159 pvscsi_reset_adapter(s);
1160}
1161
1162static void
1163pvscsi_pre_save(void *opaque)
1164{
1165 PVSCSIState *s = (PVSCSIState *) opaque;
1166
1167 trace_pvscsi_state("presave");
1168
1169 assert(QTAILQ_EMPTY(&s->pending_queue));
1170 assert(QTAILQ_EMPTY(&s->completion_queue));
1171}
1172
1173static int
1174pvscsi_post_load(void *opaque, int version_id)
1175{
1176 trace_pvscsi_state("postload");
1177 return 0;
1178}
1179
1180static bool pvscsi_vmstate_need_pcie_device(void *opaque)
1181{
1182 PVSCSIState *s = PVSCSI(opaque);
1183
1184 return !(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE);
1185}
1186
1187static bool pvscsi_vmstate_test_pci_device(void *opaque, int version_id)
1188{
1189 return !pvscsi_vmstate_need_pcie_device(opaque);
1190}
1191
1192static const VMStateDescription vmstate_pvscsi_pcie_device = {
1193 .name = "pvscsi/pcie",
1194 .needed = pvscsi_vmstate_need_pcie_device,
1195 .fields = (VMStateField[]) {
1196 VMSTATE_PCIE_DEVICE(parent_obj, PVSCSIState),
1197 VMSTATE_END_OF_LIST()
1198 }
1199};
1200
1201static const VMStateDescription vmstate_pvscsi = {
1202 .name = "pvscsi",
1203 .version_id = 0,
1204 .minimum_version_id = 0,
1205 .pre_save = pvscsi_pre_save,
1206 .post_load = pvscsi_post_load,
1207 .fields = (VMStateField[]) {
1208 VMSTATE_STRUCT_TEST(parent_obj, PVSCSIState,
1209 pvscsi_vmstate_test_pci_device, 0,
1210 vmstate_pci_device, PCIDevice),
1211 VMSTATE_UINT8(msi_used, PVSCSIState),
1212 VMSTATE_UINT32(resetting, PVSCSIState),
1213 VMSTATE_UINT64(reg_interrupt_status, PVSCSIState),
1214 VMSTATE_UINT64(reg_interrupt_enabled, PVSCSIState),
1215 VMSTATE_UINT64(reg_command_status, PVSCSIState),
1216 VMSTATE_UINT64(curr_cmd, PVSCSIState),
1217 VMSTATE_UINT32(curr_cmd_data_cntr, PVSCSIState),
1218 VMSTATE_UINT32_ARRAY(curr_cmd_data, PVSCSIState,
1219 ARRAY_SIZE(((PVSCSIState *)NULL)->curr_cmd_data)),
1220 VMSTATE_UINT8(rings_info_valid, PVSCSIState),
1221 VMSTATE_UINT8(msg_ring_info_valid, PVSCSIState),
1222 VMSTATE_UINT8(use_msg, PVSCSIState),
1223
1224 VMSTATE_UINT64(rings.rs_pa, PVSCSIState),
1225 VMSTATE_UINT32(rings.txr_len_mask, PVSCSIState),
1226 VMSTATE_UINT32(rings.rxr_len_mask, PVSCSIState),
1227 VMSTATE_UINT64_ARRAY(rings.req_ring_pages_pa, PVSCSIState,
1228 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1229 VMSTATE_UINT64_ARRAY(rings.cmp_ring_pages_pa, PVSCSIState,
1230 PVSCSI_SETUP_RINGS_MAX_NUM_PAGES),
1231 VMSTATE_UINT64(rings.consumed_ptr, PVSCSIState),
1232 VMSTATE_UINT64(rings.filled_cmp_ptr, PVSCSIState),
1233
1234 VMSTATE_END_OF_LIST()
1235 },
1236 .subsections = (const VMStateDescription*[]) {
1237 &vmstate_pvscsi_pcie_device,
1238 NULL
1239 }
1240};
1241
1242static Property pvscsi_properties[] = {
1243 DEFINE_PROP_UINT8("use_msg", PVSCSIState, use_msg, 1),
1244 DEFINE_PROP_BIT("x-old-pci-configuration", PVSCSIState, compat_flags,
1245 PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false),
1246 DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags,
1247 PVSCSI_COMPAT_DISABLE_PCIE_BIT, false),
1248 DEFINE_PROP_END_OF_LIST(),
1249};
1250
1251static void pvscsi_realize(DeviceState *qdev, Error **errp)
1252{
1253 PVSCSIClass *pvs_c = PVSCSI_DEVICE_GET_CLASS(qdev);
1254 PCIDevice *pci_dev = PCI_DEVICE(qdev);
1255 PVSCSIState *s = PVSCSI(qdev);
1256
1257 if (!(s->compat_flags & PVSCSI_COMPAT_DISABLE_PCIE)) {
1258 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1259 }
1260
1261 pvs_c->parent_dc_realize(qdev, errp);
1262}
1263
1264static void pvscsi_class_init(ObjectClass *klass, void *data)
1265{
1266 DeviceClass *dc = DEVICE_CLASS(klass);
1267 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1268 PVSCSIClass *pvs_k = PVSCSI_DEVICE_CLASS(klass);
1269 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
1270
1271 k->init = pvscsi_init;
1272 k->exit = pvscsi_uninit;
1273 k->vendor_id = PCI_VENDOR_ID_VMWARE;
1274 k->device_id = PCI_DEVICE_ID_VMWARE_PVSCSI;
1275 k->class_id = PCI_CLASS_STORAGE_SCSI;
1276 k->subsystem_id = 0x1000;
1277 pvs_k->parent_dc_realize = dc->realize;
1278 dc->realize = pvscsi_realize;
1279 dc->reset = pvscsi_reset;
1280 dc->vmsd = &vmstate_pvscsi;
1281 dc->props = pvscsi_properties;
1282 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
1283 hc->unplug = pvscsi_hot_unplug;
1284 hc->plug = pvscsi_hotplug;
1285}
1286
1287static const TypeInfo pvscsi_info = {
1288 .name = TYPE_PVSCSI,
1289 .parent = TYPE_PCI_DEVICE,
1290 .class_size = sizeof(PVSCSIClass),
1291 .instance_size = sizeof(PVSCSIState),
1292 .class_init = pvscsi_class_init,
1293 .interfaces = (InterfaceInfo[]) {
1294 { TYPE_HOTPLUG_HANDLER },
1295 { }
1296 }
1297};
1298
1299static void
1300pvscsi_register_types(void)
1301{
1302 type_register_static(&pvscsi_info);
1303}
1304
1305type_init(pvscsi_register_types);
1306
