1
2
3
4
5
6
7
8
9
10
11
12
13#include "qemu/osdep.h"
14#include "qapi/error.h"
15#include "hw/hw.h"
16#include "hw/sysbus.h"
17#include "hw/arm/pxa.h"
18#include "hw/sd/sd.h"
19#include "hw/qdev.h"
20#include "hw/qdev-properties.h"
21#include "qemu/error-report.h"
22
23#define TYPE_PXA2XX_MMCI "pxa2xx-mmci"
24#define PXA2XX_MMCI(obj) OBJECT_CHECK(PXA2xxMMCIState, (obj), TYPE_PXA2XX_MMCI)
25
26#define TYPE_PXA2XX_MMCI_BUS "pxa2xx-mmci-bus"
27#define PXA2XX_MMCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_PXA2XX_MMCI_BUS)
28
29struct PXA2xxMMCIState {
30 SysBusDevice parent_obj;
31
32 MemoryRegion iomem;
33 qemu_irq irq;
34 qemu_irq rx_dma;
35 qemu_irq tx_dma;
36 qemu_irq inserted;
37 qemu_irq readonly;
38
39 BlockBackend *blk;
40 SDBus sdbus;
41
42 uint32_t status;
43 uint32_t clkrt;
44 uint32_t spi;
45 uint32_t cmdat;
46 uint32_t resp_tout;
47 uint32_t read_tout;
48 int32_t blklen;
49 int32_t numblk;
50 uint32_t intmask;
51 uint32_t intreq;
52 int32_t cmd;
53 uint32_t arg;
54
55 int32_t active;
56 int32_t bytesleft;
57 uint8_t tx_fifo[64];
58 uint32_t tx_start;
59 uint32_t tx_len;
60 uint8_t rx_fifo[32];
61 uint32_t rx_start;
62 uint32_t rx_len;
63 uint16_t resp_fifo[9];
64 uint32_t resp_len;
65
66 int32_t cmdreq;
67};
68
69static bool pxa2xx_mmci_vmstate_validate(void *opaque, int version_id)
70{
71 PXA2xxMMCIState *s = opaque;
72
73 return s->tx_start < ARRAY_SIZE(s->tx_fifo)
74 && s->rx_start < ARRAY_SIZE(s->rx_fifo)
75 && s->tx_len <= ARRAY_SIZE(s->tx_fifo)
76 && s->rx_len <= ARRAY_SIZE(s->rx_fifo)
77 && s->resp_len <= ARRAY_SIZE(s->resp_fifo);
78}
79
80
81static const VMStateDescription vmstate_pxa2xx_mmci = {
82 .name = "pxa2xx-mmci",
83 .version_id = 2,
84 .minimum_version_id = 2,
85 .fields = (VMStateField[]) {
86 VMSTATE_UINT32(status, PXA2xxMMCIState),
87 VMSTATE_UINT32(clkrt, PXA2xxMMCIState),
88 VMSTATE_UINT32(spi, PXA2xxMMCIState),
89 VMSTATE_UINT32(cmdat, PXA2xxMMCIState),
90 VMSTATE_UINT32(resp_tout, PXA2xxMMCIState),
91 VMSTATE_UINT32(read_tout, PXA2xxMMCIState),
92 VMSTATE_INT32(blklen, PXA2xxMMCIState),
93 VMSTATE_INT32(numblk, PXA2xxMMCIState),
94 VMSTATE_UINT32(intmask, PXA2xxMMCIState),
95 VMSTATE_UINT32(intreq, PXA2xxMMCIState),
96 VMSTATE_INT32(cmd, PXA2xxMMCIState),
97 VMSTATE_UINT32(arg, PXA2xxMMCIState),
98 VMSTATE_INT32(cmdreq, PXA2xxMMCIState),
99 VMSTATE_INT32(active, PXA2xxMMCIState),
100 VMSTATE_INT32(bytesleft, PXA2xxMMCIState),
101 VMSTATE_UINT32(tx_start, PXA2xxMMCIState),
102 VMSTATE_UINT32(tx_len, PXA2xxMMCIState),
103 VMSTATE_UINT32(rx_start, PXA2xxMMCIState),
104 VMSTATE_UINT32(rx_len, PXA2xxMMCIState),
105 VMSTATE_UINT32(resp_len, PXA2xxMMCIState),
106 VMSTATE_VALIDATE("fifo size incorrect", pxa2xx_mmci_vmstate_validate),
107 VMSTATE_UINT8_ARRAY(tx_fifo, PXA2xxMMCIState, 64),
108 VMSTATE_UINT8_ARRAY(rx_fifo, PXA2xxMMCIState, 32),
109 VMSTATE_UINT16_ARRAY(resp_fifo, PXA2xxMMCIState, 9),
110 VMSTATE_END_OF_LIST()
111 }
112};
113
114#define MMC_STRPCL 0x00
115#define MMC_STAT 0x04
116#define MMC_CLKRT 0x08
117#define MMC_SPI 0x0c
118#define MMC_CMDAT 0x10
119#define MMC_RESTO 0x14
120#define MMC_RDTO 0x18
121#define MMC_BLKLEN 0x1c
122#define MMC_NUMBLK 0x20
123#define MMC_PRTBUF 0x24
124#define MMC_I_MASK 0x28
125#define MMC_I_REG 0x2c
126#define MMC_CMD 0x30
127#define MMC_ARGH 0x34
128#define MMC_ARGL 0x38
129#define MMC_RES 0x3c
130#define MMC_RXFIFO 0x40
131#define MMC_TXFIFO 0x44
132#define MMC_RDWAIT 0x48
133#define MMC_BLKS_REM 0x4c
134
135
136#define STRPCL_STOP_CLK (1 << 0)
137#define STRPCL_STRT_CLK (1 << 1)
138#define STAT_TOUT_RES (1 << 1)
139#define STAT_CLK_EN (1 << 8)
140#define STAT_DATA_DONE (1 << 11)
141#define STAT_PRG_DONE (1 << 12)
142#define STAT_END_CMDRES (1 << 13)
143#define SPI_SPI_MODE (1 << 0)
144#define CMDAT_RES_TYPE (3 << 0)
145#define CMDAT_DATA_EN (1 << 2)
146#define CMDAT_WR_RD (1 << 3)
147#define CMDAT_DMA_EN (1 << 7)
148#define CMDAT_STOP_TRAN (1 << 10)
149#define INT_DATA_DONE (1 << 0)
150#define INT_PRG_DONE (1 << 1)
151#define INT_END_CMD (1 << 2)
152#define INT_STOP_CMD (1 << 3)
153#define INT_CLK_OFF (1 << 4)
154#define INT_RXFIFO_REQ (1 << 5)
155#define INT_TXFIFO_REQ (1 << 6)
156#define INT_TINT (1 << 7)
157#define INT_DAT_ERR (1 << 8)
158#define INT_RES_ERR (1 << 9)
159#define INT_RD_STALLED (1 << 10)
160#define INT_SDIO_INT (1 << 11)
161#define INT_SDIO_SACK (1 << 12)
162#define PRTBUF_PRT_BUF (1 << 0)
163
164
165static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
166{
167 uint32_t mask = s->intmask;
168 if (s->cmdat & CMDAT_DMA_EN) {
169 mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
170
171 qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
172 qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
173 }
174
175 qemu_set_irq(s->irq, !!(s->intreq & ~mask));
176}
177
178static void pxa2xx_mmci_fifo_update(PXA2xxMMCIState *s)
179{
180 if (!s->active)
181 return;
182
183 if (s->cmdat & CMDAT_WR_RD) {
184 while (s->bytesleft && s->tx_len) {
185 sdbus_write_data(&s->sdbus, s->tx_fifo[s->tx_start++]);
186 s->tx_start &= 0x1f;
187 s->tx_len --;
188 s->bytesleft --;
189 }
190 if (s->bytesleft)
191 s->intreq |= INT_TXFIFO_REQ;
192 } else
193 while (s->bytesleft && s->rx_len < 32) {
194 s->rx_fifo[(s->rx_start + (s->rx_len ++)) & 0x1f] =
195 sdbus_read_data(&s->sdbus);
196 s->bytesleft --;
197 s->intreq |= INT_RXFIFO_REQ;
198 }
199
200 if (!s->bytesleft) {
201 s->active = 0;
202 s->intreq |= INT_DATA_DONE;
203 s->status |= STAT_DATA_DONE;
204
205 if (s->cmdat & CMDAT_WR_RD) {
206 s->intreq |= INT_PRG_DONE;
207 s->status |= STAT_PRG_DONE;
208 }
209 }
210
211 pxa2xx_mmci_int_update(s);
212}
213
214static void pxa2xx_mmci_wakequeues(PXA2xxMMCIState *s)
215{
216 int rsplen, i;
217 SDRequest request;
218 uint8_t response[16];
219
220 s->active = 1;
221 s->rx_len = 0;
222 s->tx_len = 0;
223 s->cmdreq = 0;
224
225 request.cmd = s->cmd;
226 request.arg = s->arg;
227 request.crc = 0;
228
229 rsplen = sdbus_do_command(&s->sdbus, &request, response);
230 s->intreq |= INT_END_CMD;
231
232 memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
233 switch (s->cmdat & CMDAT_RES_TYPE) {
234#define PXAMMCI_RESP(wd, value0, value1) \
235 s->resp_fifo[(wd) + 0] |= (value0); \
236 s->resp_fifo[(wd) + 1] |= (value1) << 8;
237 case 0:
238 goto complete;
239
240 case 1:
241 if (rsplen < 4)
242 goto timeout;
243 goto complete;
244
245 case 2:
246 if (rsplen < 16)
247 goto timeout;
248 goto complete;
249
250 case 3:
251 if (rsplen < 4)
252 goto timeout;
253 goto complete;
254
255 complete:
256 for (i = 0; rsplen > 0; i ++, rsplen -= 2) {
257 PXAMMCI_RESP(i, response[i * 2], response[i * 2 + 1]);
258 }
259 s->status |= STAT_END_CMDRES;
260
261 if (!(s->cmdat & CMDAT_DATA_EN))
262 s->active = 0;
263 else
264 s->bytesleft = s->numblk * s->blklen;
265
266 s->resp_len = 0;
267 break;
268
269 timeout:
270 s->active = 0;
271 s->status |= STAT_TOUT_RES;
272 break;
273 }
274
275 pxa2xx_mmci_fifo_update(s);
276}
277
278static uint64_t pxa2xx_mmci_read(void *opaque, hwaddr offset, unsigned size)
279{
280 PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
281 uint32_t ret;
282
283 switch (offset) {
284 case MMC_STRPCL:
285 return 0;
286 case MMC_STAT:
287 return s->status;
288 case MMC_CLKRT:
289 return s->clkrt;
290 case MMC_SPI:
291 return s->spi;
292 case MMC_CMDAT:
293 return s->cmdat;
294 case MMC_RESTO:
295 return s->resp_tout;
296 case MMC_RDTO:
297 return s->read_tout;
298 case MMC_BLKLEN:
299 return s->blklen;
300 case MMC_NUMBLK:
301 return s->numblk;
302 case MMC_PRTBUF:
303 return 0;
304 case MMC_I_MASK:
305 return s->intmask;
306 case MMC_I_REG:
307 return s->intreq;
308 case MMC_CMD:
309 return s->cmd | 0x40;
310 case MMC_ARGH:
311 return s->arg >> 16;
312 case MMC_ARGL:
313 return s->arg & 0xffff;
314 case MMC_RES:
315 if (s->resp_len < 9)
316 return s->resp_fifo[s->resp_len ++];
317 return 0;
318 case MMC_RXFIFO:
319 ret = 0;
320 while (size-- && s->rx_len) {
321 ret |= s->rx_fifo[s->rx_start++] << (size << 3);
322 s->rx_start &= 0x1f;
323 s->rx_len --;
324 }
325 s->intreq &= ~INT_RXFIFO_REQ;
326 pxa2xx_mmci_fifo_update(s);
327 return ret;
328 case MMC_RDWAIT:
329 return 0;
330 case MMC_BLKS_REM:
331 return s->numblk;
332 default:
333 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
334 }
335
336 return 0;
337}
338
339static void pxa2xx_mmci_write(void *opaque,
340 hwaddr offset, uint64_t value, unsigned size)
341{
342 PXA2xxMMCIState *s = (PXA2xxMMCIState *) opaque;
343
344 switch (offset) {
345 case MMC_STRPCL:
346 if (value & STRPCL_STRT_CLK) {
347 s->status |= STAT_CLK_EN;
348 s->intreq &= ~INT_CLK_OFF;
349
350 if (s->cmdreq && !(s->cmdat & CMDAT_STOP_TRAN)) {
351 s->status &= STAT_CLK_EN;
352 pxa2xx_mmci_wakequeues(s);
353 }
354 }
355
356 if (value & STRPCL_STOP_CLK) {
357 s->status &= ~STAT_CLK_EN;
358 s->intreq |= INT_CLK_OFF;
359 s->active = 0;
360 }
361
362 pxa2xx_mmci_int_update(s);
363 break;
364
365 case MMC_CLKRT:
366 s->clkrt = value & 7;
367 break;
368
369 case MMC_SPI:
370 s->spi = value & 0xf;
371 if (value & SPI_SPI_MODE)
372 printf("%s: attempted to use card in SPI mode\n", __FUNCTION__);
373 break;
374
375 case MMC_CMDAT:
376 s->cmdat = value & 0x3dff;
377 s->active = 0;
378 s->cmdreq = 1;
379 if (!(value & CMDAT_STOP_TRAN)) {
380 s->status &= STAT_CLK_EN;
381
382 if (s->status & STAT_CLK_EN)
383 pxa2xx_mmci_wakequeues(s);
384 }
385
386 pxa2xx_mmci_int_update(s);
387 break;
388
389 case MMC_RESTO:
390 s->resp_tout = value & 0x7f;
391 break;
392
393 case MMC_RDTO:
394 s->read_tout = value & 0xffff;
395 break;
396
397 case MMC_BLKLEN:
398 s->blklen = value & 0xfff;
399 break;
400
401 case MMC_NUMBLK:
402 s->numblk = value & 0xffff;
403 break;
404
405 case MMC_PRTBUF:
406 if (value & PRTBUF_PRT_BUF) {
407 s->tx_start ^= 32;
408 s->tx_len = 0;
409 }
410 pxa2xx_mmci_fifo_update(s);
411 break;
412
413 case MMC_I_MASK:
414 s->intmask = value & 0x1fff;
415 pxa2xx_mmci_int_update(s);
416 break;
417
418 case MMC_CMD:
419 s->cmd = value & 0x3f;
420 break;
421
422 case MMC_ARGH:
423 s->arg &= 0x0000ffff;
424 s->arg |= value << 16;
425 break;
426
427 case MMC_ARGL:
428 s->arg &= 0xffff0000;
429 s->arg |= value & 0x0000ffff;
430 break;
431
432 case MMC_TXFIFO:
433 while (size-- && s->tx_len < 0x20)
434 s->tx_fifo[(s->tx_start + (s->tx_len ++)) & 0x1f] =
435 (value >> (size << 3)) & 0xff;
436 s->intreq &= ~INT_TXFIFO_REQ;
437 pxa2xx_mmci_fifo_update(s);
438 break;
439
440 case MMC_RDWAIT:
441 case MMC_BLKS_REM:
442 break;
443
444 default:
445 hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
446 }
447}
448
449static const MemoryRegionOps pxa2xx_mmci_ops = {
450 .read = pxa2xx_mmci_read,
451 .write = pxa2xx_mmci_write,
452 .endianness = DEVICE_NATIVE_ENDIAN,
453};
454
455PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
456 hwaddr base,
457 BlockBackend *blk, qemu_irq irq,
458 qemu_irq rx_dma, qemu_irq tx_dma)
459{
460 DeviceState *dev, *carddev;
461 SysBusDevice *sbd;
462 PXA2xxMMCIState *s;
463 Error *err = NULL;
464
465 dev = qdev_create(NULL, TYPE_PXA2XX_MMCI);
466 s = PXA2XX_MMCI(dev);
467 sbd = SYS_BUS_DEVICE(dev);
468 sysbus_mmio_map(sbd, 0, base);
469 sysbus_connect_irq(sbd, 0, irq);
470 qdev_connect_gpio_out_named(dev, "rx-dma", 0, rx_dma);
471 qdev_connect_gpio_out_named(dev, "tx-dma", 0, tx_dma);
472
473
474 carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
475 qdev_prop_set_drive(carddev, "drive", blk, &err);
476 if (err) {
477 error_report("failed to init SD card: %s", error_get_pretty(err));
478 return NULL;
479 }
480 object_property_set_bool(OBJECT(carddev), true, "realized", &err);
481 if (err) {
482 error_report("failed to init SD card: %s", error_get_pretty(err));
483 return NULL;
484 }
485
486 return s;
487}
488
489static void pxa2xx_mmci_set_inserted(DeviceState *dev, bool inserted)
490{
491 PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
492
493 qemu_set_irq(s->inserted, inserted);
494}
495
496static void pxa2xx_mmci_set_readonly(DeviceState *dev, bool readonly)
497{
498 PXA2xxMMCIState *s = PXA2XX_MMCI(dev);
499
500 qemu_set_irq(s->readonly, readonly);
501}
502
503void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
504 qemu_irq coverswitch)
505{
506 DeviceState *dev = DEVICE(s);
507
508 s->readonly = readonly;
509 s->inserted = coverswitch;
510
511 pxa2xx_mmci_set_inserted(dev, sdbus_get_inserted(&s->sdbus));
512 pxa2xx_mmci_set_readonly(dev, sdbus_get_readonly(&s->sdbus));
513}
514
515static void pxa2xx_mmci_reset(DeviceState *d)
516{
517 PXA2xxMMCIState *s = PXA2XX_MMCI(d);
518
519 s->status = 0;
520 s->clkrt = 0;
521 s->spi = 0;
522 s->cmdat = 0;
523 s->resp_tout = 0;
524 s->read_tout = 0;
525 s->blklen = 0;
526 s->numblk = 0;
527 s->intmask = 0;
528 s->intreq = 0;
529 s->cmd = 0;
530 s->arg = 0;
531 s->active = 0;
532 s->bytesleft = 0;
533 s->tx_start = 0;
534 s->tx_len = 0;
535 s->rx_start = 0;
536 s->rx_len = 0;
537 s->resp_len = 0;
538 s->cmdreq = 0;
539 memset(s->tx_fifo, 0, sizeof(s->tx_fifo));
540 memset(s->rx_fifo, 0, sizeof(s->rx_fifo));
541 memset(s->resp_fifo, 0, sizeof(s->resp_fifo));
542}
543
544static void pxa2xx_mmci_instance_init(Object *obj)
545{
546 PXA2xxMMCIState *s = PXA2XX_MMCI(obj);
547 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
548 DeviceState *dev = DEVICE(obj);
549
550 memory_region_init_io(&s->iomem, obj, &pxa2xx_mmci_ops, s,
551 "pxa2xx-mmci", 0x00100000);
552 sysbus_init_mmio(sbd, &s->iomem);
553 sysbus_init_irq(sbd, &s->irq);
554 qdev_init_gpio_out_named(dev, &s->rx_dma, "rx-dma", 1);
555 qdev_init_gpio_out_named(dev, &s->tx_dma, "tx-dma", 1);
556
557 qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
558 TYPE_PXA2XX_MMCI_BUS, DEVICE(obj), "sd-bus");
559}
560
561static void pxa2xx_mmci_class_init(ObjectClass *klass, void *data)
562{
563 DeviceClass *dc = DEVICE_CLASS(klass);
564
565 dc->vmsd = &vmstate_pxa2xx_mmci;
566 dc->reset = pxa2xx_mmci_reset;
567}
568
569static void pxa2xx_mmci_bus_class_init(ObjectClass *klass, void *data)
570{
571 SDBusClass *sbc = SD_BUS_CLASS(klass);
572
573 sbc->set_inserted = pxa2xx_mmci_set_inserted;
574 sbc->set_readonly = pxa2xx_mmci_set_readonly;
575}
576
577static const TypeInfo pxa2xx_mmci_info = {
578 .name = TYPE_PXA2XX_MMCI,
579 .parent = TYPE_SYS_BUS_DEVICE,
580 .instance_size = sizeof(PXA2xxMMCIState),
581 .instance_init = pxa2xx_mmci_instance_init,
582 .class_init = pxa2xx_mmci_class_init,
583};
584
585static const TypeInfo pxa2xx_mmci_bus_info = {
586 .name = TYPE_PXA2XX_MMCI_BUS,
587 .parent = TYPE_SD_BUS,
588 .instance_size = sizeof(SDBus),
589 .class_init = pxa2xx_mmci_bus_class_init,
590};
591
592static void pxa2xx_mmci_register_types(void)
593{
594 type_register_static(&pxa2xx_mmci_info);
595 type_register_static(&pxa2xx_mmci_bus_info);
596}
597
598type_init(pxa2xx_mmci_register_types)
599
