1/* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24#ifndef SDHCI_INTERNAL_H 25#define SDHCI_INTERNAL_H 26 27#include "hw/sd/sdhci.h" 28 29/* R/W SDMA System Address register 0x0 */ 30#define SDHC_SYSAD 0x00 31 32/* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */ 33#define SDHC_BLKSIZE 0x04 34 35/* R/W Blocks count for current transfer 0x0 */ 36#define SDHC_BLKCNT 0x06 37 38/* R/W Command Argument Register 0x0 */ 39#define SDHC_ARGUMENT 0x08 40 41/* R/W Transfer Mode Setting Register 0x0 */ 42#define SDHC_TRNMOD 0x0C 43#define SDHC_TRNS_DMA 0x0001 44#define SDHC_TRNS_BLK_CNT_EN 0x0002 45#define SDHC_TRNS_ACMD12 0x0004 46#define SDHC_TRNS_READ 0x0010 47#define SDHC_TRNS_MULTI 0x0020 48 49/* R/W Command Register 0x0 */ 50#define SDHC_CMDREG 0x0E 51#define SDHC_CMD_RSP_WITH_BUSY (3 << 0) 52#define SDHC_CMD_DATA_PRESENT (1 << 5) 53#define SDHC_CMD_SUSPEND (1 << 6) 54#define SDHC_CMD_RESUME (1 << 7) 55#define SDHC_CMD_ABORT ((1 << 6)|(1 << 7)) 56#define SDHC_CMD_TYPE_MASK ((1 << 6)|(1 << 7)) 57#define SDHC_COMMAND_TYPE(x) ((x) & SDHC_CMD_TYPE_MASK) 58 59/* ROC Response Register 0 0x0 */ 60#define SDHC_RSPREG0 0x10 61/* ROC Response Register 1 0x0 */ 62#define SDHC_RSPREG1 0x14 63/* ROC Response Register 2 0x0 */ 64#define SDHC_RSPREG2 0x18 65/* ROC Response Register 3 0x0 */ 66#define SDHC_RSPREG3 0x1C 67 68/* R/W Buffer Data Register 0x0 */ 69#define SDHC_BDATA 0x20 70 71/* R/ROC Present State Register 0x000A0000 */ 72#define SDHC_PRNSTS 0x24 73#define SDHC_CMD_INHIBIT 0x00000001 74#define SDHC_DATA_INHIBIT 0x00000002 75#define SDHC_DAT_LINE_ACTIVE 0x00000004 76#define SDHC_DOING_WRITE 0x00000100 77#define SDHC_DOING_READ 0x00000200 78#define SDHC_SPACE_AVAILABLE 0x00000400 79#define SDHC_DATA_AVAILABLE 0x00000800 80#define SDHC_CARD_PRESENT 0x00010000 81#define SDHC_CARD_DETECT 0x00040000 82#define SDHC_WRITE_PROTECT 0x00080000 83#define TRANSFERRING_DATA(x) \ 84 ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) 85 86/* R/W Host control Register 0x0 */ 87#define SDHC_HOSTCTL 0x28 88#define SDHC_CTRL_DMA_CHECK_MASK 0x18 89#define SDHC_CTRL_SDMA 0x00 90#define SDHC_CTRL_ADMA1_32 0x08 91#define SDHC_CTRL_ADMA2_32 0x10 92#define SDHC_CTRL_ADMA2_64 0x18 93#define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK) 94 95/* R/W Power Control Register 0x0 */ 96#define SDHC_PWRCON 0x29 97#define SDHC_POWER_ON (1 << 0) 98 99/* R/W Block Gap Control Register 0x0 */ 100#define SDHC_BLKGAP 0x2A 101#define SDHC_STOP_AT_GAP_REQ 0x01 102#define SDHC_CONTINUE_REQ 0x02 103 104/* R/W WakeUp Control Register 0x0 */ 105#define SDHC_WAKCON 0x2B 106#define SDHC_WKUP_ON_INS (1 << 1) 107#define SDHC_WKUP_ON_RMV (1 << 2) 108 109/* CLKCON */ 110#define SDHC_CLKCON 0x2C 111#define SDHC_CLOCK_INT_STABLE 0x0002 112#define SDHC_CLOCK_INT_EN 0x0001 113#define SDHC_CLOCK_SDCLK_EN (1 << 2) 114#define SDHC_CLOCK_CHK_MASK 0x0007 115#define SDHC_CLOCK_IS_ON(x) \ 116 (((x) & SDHC_CLOCK_CHK_MASK) == SDHC_CLOCK_CHK_MASK) 117 118/* R/W Timeout Control Register 0x0 */ 119#define SDHC_TIMEOUTCON 0x2E 120 121/* R/W Software Reset Register 0x0 */ 122#define SDHC_SWRST 0x2F 123#define SDHC_RESET_ALL 0x01 124#define SDHC_RESET_CMD 0x02 125#define SDHC_RESET_DATA 0x04 126 127/* ROC/RW1C Normal Interrupt Status Register 0x0 */ 128#define SDHC_NORINTSTS 0x30 129#define SDHC_NIS_ERR 0x8000 130#define SDHC_NIS_CMDCMP 0x0001 131#define SDHC_NIS_TRSCMP 0x0002 132#define SDHC_NIS_BLKGAP 0x0004 133#define SDHC_NIS_DMA 0x0008 134#define SDHC_NIS_WBUFRDY 0x0010 135#define SDHC_NIS_RBUFRDY 0x0020 136#define SDHC_NIS_INSERT 0x0040 137#define SDHC_NIS_REMOVE 0x0080 138#define SDHC_NIS_CARDINT 0x0100 139 140/* ROC/RW1C Error Interrupt Status Register 0x0 */ 141#define SDHC_ERRINTSTS 0x32 142#define SDHC_EIS_CMDTIMEOUT 0x0001 143#define SDHC_EIS_BLKGAP 0x0004 144#define SDHC_EIS_CMDIDX 0x0008 145#define SDHC_EIS_CMD12ERR 0x0100 146#define SDHC_EIS_ADMAERR 0x0200 147 148/* R/W Normal Interrupt Status Enable Register 0x0 */ 149#define SDHC_NORINTSTSEN 0x34 150#define SDHC_NISEN_CMDCMP 0x0001 151#define SDHC_NISEN_TRSCMP 0x0002 152#define SDHC_NISEN_DMA 0x0008 153#define SDHC_NISEN_WBUFRDY 0x0010 154#define SDHC_NISEN_RBUFRDY 0x0020 155#define SDHC_NISEN_INSERT 0x0040 156#define SDHC_NISEN_REMOVE 0x0080 157#define SDHC_NISEN_CARDINT 0x0100 158 159/* R/W Error Interrupt Status Enable Register 0x0 */ 160#define SDHC_ERRINTSTSEN 0x36 161#define SDHC_EISEN_CMDTIMEOUT 0x0001 162#define SDHC_EISEN_BLKGAP 0x0004 163#define SDHC_EISEN_CMDIDX 0x0008 164#define SDHC_EISEN_ADMAERR 0x0200 165 166/* R/W Normal Interrupt Signal Enable Register 0x0 */ 167#define SDHC_NORINTSIGEN 0x38 168#define SDHC_NORINTSIG_INSERT (1 << 6) 169#define SDHC_NORINTSIG_REMOVE (1 << 7) 170 171/* R/W Error Interrupt Signal Enable Register 0x0 */ 172#define SDHC_ERRINTSIGEN 0x3A 173 174/* ROC Auto CMD12 error status register 0x0 */ 175#define SDHC_ACMD12ERRSTS 0x3C 176 177/* HWInit Capabilities Register 0x05E80080 */ 178#define SDHC_CAPAREG 0x40 179#define SDHC_CAN_DO_DMA 0x00400000 180#define SDHC_CAN_DO_ADMA2 0x00080000 181#define SDHC_CAN_DO_ADMA1 0x00100000 182#define SDHC_64_BIT_BUS_SUPPORT (1 << 28) 183#define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) 184 185/* HWInit Maximum Current Capabilities Register 0x0 */ 186#define SDHC_MAXCURR 0x48 187 188/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ 189#define SDHC_FEAER 0x50 190/* W Force Event Error Interrupt Register Error Interrupt 0x0000 */ 191#define SDHC_FEERR 0x52 192 193/* R/W ADMA Error Status Register 0x00 */ 194#define SDHC_ADMAERR 0x54 195#define SDHC_ADMAERR_LENGTH_MISMATCH (1 << 2) 196#define SDHC_ADMAERR_STATE_ST_STOP (0 << 0) 197#define SDHC_ADMAERR_STATE_ST_FDS (1 << 0) 198#define SDHC_ADMAERR_STATE_ST_TFR (3 << 0) 199#define SDHC_ADMAERR_STATE_MASK (3 << 0) 200 201/* R/W ADMA System Address Register 0x00 */ 202#define SDHC_ADMASYSADDR 0x58 203#define SDHC_ADMA_ATTR_SET_LEN (1 << 4) 204#define SDHC_ADMA_ATTR_ACT_TRAN (1 << 5) 205#define SDHC_ADMA_ATTR_ACT_LINK (3 << 4) 206#define SDHC_ADMA_ATTR_INT (1 << 2) 207#define SDHC_ADMA_ATTR_END (1 << 1) 208#define SDHC_ADMA_ATTR_VALID (1 << 0) 209#define SDHC_ADMA_ATTR_ACT_MASK ((1 << 4)|(1 << 5)) 210 211/* Slot interrupt status */ 212#define SDHC_SLOT_INT_STATUS 0xFC 213 214/* HWInit Host Controller Version Register 0x0401 */ 215#define SDHC_HCVER 0xFE 216#define SD_HOST_SPECv2_VERS 0x2402 217 218#define SDHC_REGISTERS_MAP_SIZE 0x100 219#define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND) 220#define SDHC_TRANSFER_DELAY 100 221#define SDHC_ADMA_DESCS_PER_DELAY 5 222#define SDHC_CMD_RESPONSE (3 << 0) 223 224/* ROC Auto CMD12 error status register 0x0 */ 225/* 16 MSB are the Host Control Register 2. */ 226#define SDHC_ACMD12ERRSTS 0x3C 227#define SDHC_HOSTCTL2 0x3E 228#define SDHC_CTRL2_VOLTAGE_SWITCH (1 << 3) 229#define SDHC_CTRL2_SAMPLING_CLKSEL (1 << 23) 230#define SDHC_CTRL2_EXECUTE_TUNING (1 << 22) 231 232/* R/ROC Present State Register 0x000A0000 */ 233#define SDHC_PRNSTS 0x24 234#define SDHC_CMD_LVL_SHIFT 24 235#define SDHC_CMD_INHIBIT 0x00000001 236#define SDHC_DATA_INHIBIT 0x00000002 237#define SDHC_DAT_LINE_ACTIVE 0x00000004 238#define SDHC_DOING_WRITE 0x00000100 239#define SDHC_DOING_READ 0x00000200 240#define SDHC_SPACE_AVAILABLE 0x00000400 241#define SDHC_DATA_AVAILABLE 0x00000800 242#define SDHC_CARD_PRESENT 0x00010000 243#define SDHC_CARD_DETECT 0x00040000 244#define SDHC_WRITE_PROTECT 0x00080000 245#define SDHC_DAT_LVL_SHIFT 20 246#define SDHC_DAT_LVL_LENGTH 4 247#define TRANSFERRING_DATA(x) \ 248 ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) 249 250/* HWInit Capabilities Register 0x05E80080 */ 251#define SDHC_CAPAREG 0x40 252#define SDHC_CAPAREG_HI 0x44 253#define SDHC_CAN_DO_DMA 0x00400000 254#define SDHC_CAN_DO_ADMA2 0x00080000 255#define SDHC_CAN_DO_ADMA1 0x00100000 256#define SDHC_64_BIT_BUS_SUPPORT (1 << 28) 257#define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) 258 259enum { 260 sdhc_not_stopped = 0, /* normal SDHC state */ 261 sdhc_gap_read = 1, /* SDHC stopped at block gap during read operation */ 262 sdhc_gap_write = 2 /* SDHC stopped at block gap during write operation */ 263}; 264 265extern const VMStateDescription sdhci_vmstate; 266 267#endif 268