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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "qemu-common.h"
27#include "cpu.h"
28#include "hw/sysbus.h"
29#include "qemu/error-report.h"
30#include "qemu/timer.h"
31#include "hw/sparc/sun4m.h"
32#include "hw/timer/m48t59.h"
33#include "hw/sparc/sparc32_dma.h"
34#include "hw/block/fdc.h"
35#include "sysemu/sysemu.h"
36#include "net/net.h"
37#include "hw/boards.h"
38#include "hw/nvram/openbios_firmware_abi.h"
39#include "hw/scsi/esp.h"
40#include "hw/i386/pc.h"
41#include "hw/isa/isa.h"
42#include "hw/nvram/fw_cfg.h"
43#include "hw/char/escc.h"
44#include "hw/empty_slot.h"
45#include "hw/loader.h"
46#include "elf.h"
47#include "sysemu/block-backend.h"
48#include "trace.h"
49#include "qemu/cutils.h"
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67#define KERNEL_LOAD_ADDR 0x00004000
68#define CMDLINE_ADDR 0x007ff000
69#define INITRD_LOAD_ADDR 0x00800000
70#define PROM_SIZE_MAX (1024 * 1024)
71#define PROM_VADDR 0xffd00000
72#define PROM_FILENAME "openbios-sparc32"
73#define CFG_ADDR 0xd00000510ULL
74#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
75#define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
76#define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
77
78#define MAX_CPUS 16
79#define MAX_PILS 16
80#define MAX_VSIMMS 4
81
82#define ESCC_CLOCK 4915200
83
84struct sun4m_hwdef {
85 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
86 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
87 hwaddr serial_base, fd_base;
88 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
89 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
90 hwaddr bpp_base, dbri_base, sx_base;
91 struct {
92 hwaddr reg_base, vram_base;
93 } vsimm[MAX_VSIMMS];
94 hwaddr ecc_base;
95 uint64_t max_mem;
96 const char * const default_cpu_model;
97 uint32_t ecc_version;
98 uint32_t iommu_version;
99 uint16_t machine_id;
100 uint8_t nvram_machine_id;
101};
102
103void DMA_init(ISABus *bus, int high_page_enable)
104{
105}
106
107static void fw_cfg_boot_set(void *opaque, const char *boot_device,
108 Error **errp)
109{
110 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
111}
112
113static void nvram_init(Nvram *nvram, uint8_t *macaddr,
114 const char *cmdline, const char *boot_devices,
115 ram_addr_t RAM_size, uint32_t kernel_size,
116 int width, int height, int depth,
117 int nvram_machine_id, const char *arch)
118{
119 unsigned int i;
120 uint32_t start, end;
121 uint8_t image[0x1ff0];
122 struct OpenBIOS_nvpart_v1 *part_header;
123 NvramClass *k = NVRAM_GET_CLASS(nvram);
124
125 memset(image, '\0', sizeof(image));
126
127 start = 0;
128
129
130
131 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
132 part_header->signature = OPENBIOS_PART_SYSTEM;
133 pstrcpy(part_header->name, sizeof(part_header->name), "system");
134
135 end = start + sizeof(struct OpenBIOS_nvpart_v1);
136 for (i = 0; i < nb_prom_envs; i++)
137 end = OpenBIOS_set_var(image, end, prom_envs[i]);
138
139
140 image[end++] = '\0';
141
142 end = start + ((end - start + 15) & ~15);
143 OpenBIOS_finish_partition(part_header, end - start);
144
145
146 start = end;
147 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
148 part_header->signature = OPENBIOS_PART_FREE;
149 pstrcpy(part_header->name, sizeof(part_header->name), "free");
150
151 end = 0x1fd0;
152 OpenBIOS_finish_partition(part_header, end - start);
153
154 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
155 nvram_machine_id);
156
157 for (i = 0; i < sizeof(image); i++) {
158 (k->write)(nvram, i, image[i]);
159 }
160}
161
162static DeviceState *slavio_intctl;
163
164void sun4m_hmp_info_pic(Monitor *mon, const QDict *qdict)
165{
166 if (slavio_intctl)
167 slavio_pic_info(mon, slavio_intctl);
168}
169
170void sun4m_hmp_info_irq(Monitor *mon, const QDict *qdict)
171{
172 if (slavio_intctl)
173 slavio_irq_info(mon, slavio_intctl);
174}
175
176void cpu_check_irqs(CPUSPARCState *env)
177{
178 CPUState *cs;
179
180 if (env->pil_in && (env->interrupt_index == 0 ||
181 (env->interrupt_index & ~15) == TT_EXTINT)) {
182 unsigned int i;
183
184 for (i = 15; i > 0; i--) {
185 if (env->pil_in & (1 << i)) {
186 int old_interrupt = env->interrupt_index;
187
188 env->interrupt_index = TT_EXTINT | i;
189 if (old_interrupt != env->interrupt_index) {
190 cs = CPU(sparc_env_get_cpu(env));
191 trace_sun4m_cpu_interrupt(i);
192 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
193 }
194 break;
195 }
196 }
197 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
198 cs = CPU(sparc_env_get_cpu(env));
199 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
200 env->interrupt_index = 0;
201 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
202 }
203}
204
205static void cpu_kick_irq(SPARCCPU *cpu)
206{
207 CPUSPARCState *env = &cpu->env;
208 CPUState *cs = CPU(cpu);
209
210 cs->halted = 0;
211 cpu_check_irqs(env);
212 qemu_cpu_kick(cs);
213}
214
215static void cpu_set_irq(void *opaque, int irq, int level)
216{
217 SPARCCPU *cpu = opaque;
218 CPUSPARCState *env = &cpu->env;
219
220 if (level) {
221 trace_sun4m_cpu_set_irq_raise(irq);
222 env->pil_in |= 1 << irq;
223 cpu_kick_irq(cpu);
224 } else {
225 trace_sun4m_cpu_set_irq_lower(irq);
226 env->pil_in &= ~(1 << irq);
227 cpu_check_irqs(env);
228 }
229}
230
231static void dummy_cpu_set_irq(void *opaque, int irq, int level)
232{
233}
234
235static void main_cpu_reset(void *opaque)
236{
237 SPARCCPU *cpu = opaque;
238 CPUState *cs = CPU(cpu);
239
240 cpu_reset(cs);
241 cs->halted = 0;
242}
243
244static void secondary_cpu_reset(void *opaque)
245{
246 SPARCCPU *cpu = opaque;
247 CPUState *cs = CPU(cpu);
248
249 cpu_reset(cs);
250 cs->halted = 1;
251}
252
253static void cpu_halt_signal(void *opaque, int irq, int level)
254{
255 if (level && current_cpu) {
256 cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT);
257 }
258}
259
260static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
261{
262 return addr - 0xf0000000ULL;
263}
264
265static unsigned long sun4m_load_kernel(const char *kernel_filename,
266 const char *initrd_filename,
267 ram_addr_t RAM_size)
268{
269 int linux_boot;
270 unsigned int i;
271 long initrd_size, kernel_size;
272 uint8_t *ptr;
273
274 linux_boot = (kernel_filename != NULL);
275
276 kernel_size = 0;
277 if (linux_boot) {
278 int bswap_needed;
279
280#ifdef BSWAP_NEEDED
281 bswap_needed = 1;
282#else
283 bswap_needed = 0;
284#endif
285 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
286 NULL, NULL, NULL, 1, EM_SPARC, 0, 0);
287 if (kernel_size < 0)
288 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
289 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
290 TARGET_PAGE_SIZE);
291 if (kernel_size < 0)
292 kernel_size = load_image_targphys(kernel_filename,
293 KERNEL_LOAD_ADDR,
294 RAM_size - KERNEL_LOAD_ADDR);
295 if (kernel_size < 0) {
296 fprintf(stderr, "qemu: could not load kernel '%s'\n",
297 kernel_filename);
298 exit(1);
299 }
300
301
302 initrd_size = 0;
303 if (initrd_filename) {
304 initrd_size = load_image_targphys(initrd_filename,
305 INITRD_LOAD_ADDR,
306 RAM_size - INITRD_LOAD_ADDR);
307 if (initrd_size < 0) {
308 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
309 initrd_filename);
310 exit(1);
311 }
312 }
313 if (initrd_size > 0) {
314 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
315 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
316 if (ldl_p(ptr) == 0x48647253) {
317 stl_p(ptr + 16, INITRD_LOAD_ADDR);
318 stl_p(ptr + 20, initrd_size);
319 break;
320 }
321 }
322 }
323 }
324 return kernel_size;
325}
326
327static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
328{
329 DeviceState *dev;
330 SysBusDevice *s;
331
332 dev = qdev_create(NULL, "iommu");
333 qdev_prop_set_uint32(dev, "version", version);
334 qdev_init_nofail(dev);
335 s = SYS_BUS_DEVICE(dev);
336 sysbus_connect_irq(s, 0, irq);
337 sysbus_mmio_map(s, 0, addr);
338
339 return s;
340}
341
342static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
343 void *iommu, qemu_irq *dev_irq, int is_ledma)
344{
345 DeviceState *dev;
346 SysBusDevice *s;
347
348 dev = qdev_create(NULL, "sparc32_dma");
349 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
350 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
351 qdev_init_nofail(dev);
352 s = SYS_BUS_DEVICE(dev);
353 sysbus_connect_irq(s, 0, parent_irq);
354 *dev_irq = qdev_get_gpio_in(dev, 0);
355 sysbus_mmio_map(s, 0, daddr);
356
357 return s;
358}
359
360static void lance_init(NICInfo *nd, hwaddr leaddr,
361 void *dma_opaque, qemu_irq irq)
362{
363 DeviceState *dev;
364 SysBusDevice *s;
365 qemu_irq reset;
366
367 qemu_check_nic_model(&nd_table[0], "lance");
368
369 dev = qdev_create(NULL, "lance");
370 qdev_set_nic_properties(dev, nd);
371 qdev_prop_set_ptr(dev, "dma", dma_opaque);
372 qdev_init_nofail(dev);
373 s = SYS_BUS_DEVICE(dev);
374 sysbus_mmio_map(s, 0, leaddr);
375 sysbus_connect_irq(s, 0, irq);
376 reset = qdev_get_gpio_in(dev, 0);
377 qdev_connect_gpio_out(dma_opaque, 0, reset);
378}
379
380static DeviceState *slavio_intctl_init(hwaddr addr,
381 hwaddr addrg,
382 qemu_irq **parent_irq)
383{
384 DeviceState *dev;
385 SysBusDevice *s;
386 unsigned int i, j;
387
388 dev = qdev_create(NULL, "slavio_intctl");
389 qdev_init_nofail(dev);
390
391 s = SYS_BUS_DEVICE(dev);
392
393 for (i = 0; i < MAX_CPUS; i++) {
394 for (j = 0; j < MAX_PILS; j++) {
395 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
396 }
397 }
398 sysbus_mmio_map(s, 0, addrg);
399 for (i = 0; i < MAX_CPUS; i++) {
400 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
401 }
402
403 return dev;
404}
405
406#define SYS_TIMER_OFFSET 0x10000ULL
407#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
408
409static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
410 qemu_irq *cpu_irqs, unsigned int num_cpus)
411{
412 DeviceState *dev;
413 SysBusDevice *s;
414 unsigned int i;
415
416 dev = qdev_create(NULL, "slavio_timer");
417 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
418 qdev_init_nofail(dev);
419 s = SYS_BUS_DEVICE(dev);
420 sysbus_connect_irq(s, 0, master_irq);
421 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
422
423 for (i = 0; i < MAX_CPUS; i++) {
424 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
425 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
426 }
427}
428
429static qemu_irq slavio_system_powerdown;
430
431static void slavio_powerdown_req(Notifier *n, void *opaque)
432{
433 qemu_irq_raise(slavio_system_powerdown);
434}
435
436static Notifier slavio_system_powerdown_notifier = {
437 .notify = slavio_powerdown_req
438};
439
440#define MISC_LEDS 0x01600000
441#define MISC_CFG 0x01800000
442#define MISC_DIAG 0x01a00000
443#define MISC_MDM 0x01b00000
444#define MISC_SYS 0x01f00000
445
446static void slavio_misc_init(hwaddr base,
447 hwaddr aux1_base,
448 hwaddr aux2_base, qemu_irq irq,
449 qemu_irq fdc_tc)
450{
451 DeviceState *dev;
452 SysBusDevice *s;
453
454 dev = qdev_create(NULL, "slavio_misc");
455 qdev_init_nofail(dev);
456 s = SYS_BUS_DEVICE(dev);
457 if (base) {
458
459
460 sysbus_mmio_map(s, 0, base + MISC_CFG);
461
462 sysbus_mmio_map(s, 1, base + MISC_DIAG);
463
464 sysbus_mmio_map(s, 2, base + MISC_MDM);
465
466
467 sysbus_mmio_map(s, 3, base + MISC_LEDS);
468
469
470 sysbus_mmio_map(s, 4, base + MISC_SYS);
471 }
472 if (aux1_base) {
473
474 sysbus_mmio_map(s, 5, aux1_base);
475 }
476 if (aux2_base) {
477
478 sysbus_mmio_map(s, 6, aux2_base);
479 }
480 sysbus_connect_irq(s, 0, irq);
481 sysbus_connect_irq(s, 1, fdc_tc);
482 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
483 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
484}
485
486static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
487{
488 DeviceState *dev;
489 SysBusDevice *s;
490
491 dev = qdev_create(NULL, "eccmemctl");
492 qdev_prop_set_uint32(dev, "version", version);
493 qdev_init_nofail(dev);
494 s = SYS_BUS_DEVICE(dev);
495 sysbus_connect_irq(s, 0, irq);
496 sysbus_mmio_map(s, 0, base);
497 if (version == 0) {
498 sysbus_mmio_map(s, 1, base + 0x1000);
499 }
500}
501
502static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
503{
504 DeviceState *dev;
505 SysBusDevice *s;
506
507 dev = qdev_create(NULL, "apc");
508 qdev_init_nofail(dev);
509 s = SYS_BUS_DEVICE(dev);
510
511 sysbus_mmio_map(s, 0, power_base);
512 sysbus_connect_irq(s, 0, cpu_halt);
513}
514
515static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
516 int height, int depth)
517{
518 DeviceState *dev;
519 SysBusDevice *s;
520
521 dev = qdev_create(NULL, "SUNW,tcx");
522 qdev_prop_set_uint32(dev, "vram_size", vram_size);
523 qdev_prop_set_uint16(dev, "width", width);
524 qdev_prop_set_uint16(dev, "height", height);
525 qdev_prop_set_uint16(dev, "depth", depth);
526 qdev_prop_set_uint64(dev, "prom_addr", addr);
527 qdev_init_nofail(dev);
528 s = SYS_BUS_DEVICE(dev);
529
530
531 sysbus_mmio_map(s, 0, addr);
532
533 sysbus_mmio_map(s, 1, addr + 0x04000000ULL);
534
535 sysbus_mmio_map(s, 2, addr + 0x06000000ULL);
536
537 sysbus_mmio_map(s, 3, addr + 0x0c000000ULL);
538
539 sysbus_mmio_map(s, 4, addr + 0x0e000000ULL);
540
541 sysbus_mmio_map(s, 5, addr + 0x00700000ULL);
542
543 sysbus_mmio_map(s, 6, addr + 0x00200000ULL);
544
545 if (depth == 8) {
546 sysbus_mmio_map(s, 7, addr + 0x00300000ULL);
547 } else {
548 sysbus_mmio_map(s, 7, addr + 0x00301000ULL);
549 }
550
551 sysbus_mmio_map(s, 8, addr + 0x00240000ULL);
552
553 sysbus_mmio_map(s, 9, addr + 0x00280000ULL);
554
555 sysbus_mmio_map(s, 10, addr + 0x00800000ULL);
556
557 sysbus_mmio_map(s, 11, addr + 0x02000000ULL);
558
559 sysbus_mmio_map(s, 12, addr + 0x0a000000ULL);
560
561 if (depth == 8) {
562 sysbus_mmio_map(s, 13, addr + 0x00301000ULL);
563 }
564
565 sysbus_connect_irq(s, 0, irq);
566}
567
568static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width,
569 int height, int depth)
570{
571 DeviceState *dev;
572 SysBusDevice *s;
573
574 dev = qdev_create(NULL, "cgthree");
575 qdev_prop_set_uint32(dev, "vram-size", vram_size);
576 qdev_prop_set_uint16(dev, "width", width);
577 qdev_prop_set_uint16(dev, "height", height);
578 qdev_prop_set_uint16(dev, "depth", depth);
579 qdev_prop_set_uint64(dev, "prom-addr", addr);
580 qdev_init_nofail(dev);
581 s = SYS_BUS_DEVICE(dev);
582
583
584 sysbus_mmio_map(s, 0, addr);
585
586 sysbus_mmio_map(s, 1, addr + 0x400000ULL);
587
588 sysbus_mmio_map(s, 2, addr + 0x800000ULL);
589
590 sysbus_connect_irq(s, 0, irq);
591}
592
593
594
595#define TYPE_MACIO_ID_REGISTER "macio_idreg"
596
597static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
598
599static void idreg_init(hwaddr addr)
600{
601 DeviceState *dev;
602 SysBusDevice *s;
603
604 dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER);
605 qdev_init_nofail(dev);
606 s = SYS_BUS_DEVICE(dev);
607
608 sysbus_mmio_map(s, 0, addr);
609 cpu_physical_memory_write_rom(&address_space_memory,
610 addr, idreg_data, sizeof(idreg_data));
611}
612
613#define MACIO_ID_REGISTER(obj) \
614 OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER)
615
616typedef struct IDRegState {
617 SysBusDevice parent_obj;
618
619 MemoryRegion mem;
620} IDRegState;
621
622static int idreg_init1(SysBusDevice *dev)
623{
624 IDRegState *s = MACIO_ID_REGISTER(dev);
625
626 memory_region_init_ram(&s->mem, OBJECT(s),
627 "sun4m.idreg", sizeof(idreg_data), &error_fatal);
628 vmstate_register_ram_global(&s->mem);
629 memory_region_set_readonly(&s->mem, true);
630 sysbus_init_mmio(dev, &s->mem);
631 return 0;
632}
633
634static void idreg_class_init(ObjectClass *klass, void *data)
635{
636 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
637
638 k->init = idreg_init1;
639}
640
641static const TypeInfo idreg_info = {
642 .name = TYPE_MACIO_ID_REGISTER,
643 .parent = TYPE_SYS_BUS_DEVICE,
644 .instance_size = sizeof(IDRegState),
645 .class_init = idreg_class_init,
646};
647
648#define TYPE_TCX_AFX "tcx_afx"
649#define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX)
650
651typedef struct AFXState {
652 SysBusDevice parent_obj;
653
654 MemoryRegion mem;
655} AFXState;
656
657
658static void afx_init(hwaddr addr)
659{
660 DeviceState *dev;
661 SysBusDevice *s;
662
663 dev = qdev_create(NULL, TYPE_TCX_AFX);
664 qdev_init_nofail(dev);
665 s = SYS_BUS_DEVICE(dev);
666
667 sysbus_mmio_map(s, 0, addr);
668}
669
670static int afx_init1(SysBusDevice *dev)
671{
672 AFXState *s = TCX_AFX(dev);
673
674 memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
675 vmstate_register_ram_global(&s->mem);
676 sysbus_init_mmio(dev, &s->mem);
677 return 0;
678}
679
680static void afx_class_init(ObjectClass *klass, void *data)
681{
682 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
683
684 k->init = afx_init1;
685}
686
687static const TypeInfo afx_info = {
688 .name = TYPE_TCX_AFX,
689 .parent = TYPE_SYS_BUS_DEVICE,
690 .instance_size = sizeof(AFXState),
691 .class_init = afx_class_init,
692};
693
694#define TYPE_OPENPROM "openprom"
695#define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM)
696
697typedef struct PROMState {
698 SysBusDevice parent_obj;
699
700 MemoryRegion prom;
701} PROMState;
702
703
704static uint64_t translate_prom_address(void *opaque, uint64_t addr)
705{
706 hwaddr *base_addr = (hwaddr *)opaque;
707 return addr + *base_addr - PROM_VADDR;
708}
709
710static void prom_init(hwaddr addr, const char *bios_name)
711{
712 DeviceState *dev;
713 SysBusDevice *s;
714 char *filename;
715 int ret;
716
717 dev = qdev_create(NULL, TYPE_OPENPROM);
718 qdev_init_nofail(dev);
719 s = SYS_BUS_DEVICE(dev);
720
721 sysbus_mmio_map(s, 0, addr);
722
723
724 if (bios_name == NULL) {
725 bios_name = PROM_FILENAME;
726 }
727 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
728 if (filename) {
729 ret = load_elf(filename, translate_prom_address, &addr, NULL,
730 NULL, NULL, 1, EM_SPARC, 0, 0);
731 if (ret < 0 || ret > PROM_SIZE_MAX) {
732 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
733 }
734 g_free(filename);
735 } else {
736 ret = -1;
737 }
738 if (ret < 0 || ret > PROM_SIZE_MAX) {
739 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
740 exit(1);
741 }
742}
743
744static int prom_init1(SysBusDevice *dev)
745{
746 PROMState *s = OPENPROM(dev);
747
748 memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
749 &error_fatal);
750 vmstate_register_ram_global(&s->prom);
751 memory_region_set_readonly(&s->prom, true);
752 sysbus_init_mmio(dev, &s->prom);
753 return 0;
754}
755
756static Property prom_properties[] = {
757 {},
758};
759
760static void prom_class_init(ObjectClass *klass, void *data)
761{
762 DeviceClass *dc = DEVICE_CLASS(klass);
763 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
764
765 k->init = prom_init1;
766 dc->props = prom_properties;
767}
768
769static const TypeInfo prom_info = {
770 .name = TYPE_OPENPROM,
771 .parent = TYPE_SYS_BUS_DEVICE,
772 .instance_size = sizeof(PROMState),
773 .class_init = prom_class_init,
774};
775
776#define TYPE_SUN4M_MEMORY "memory"
777#define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY)
778
779typedef struct RamDevice {
780 SysBusDevice parent_obj;
781
782 MemoryRegion ram;
783 uint64_t size;
784} RamDevice;
785
786
787static int ram_init1(SysBusDevice *dev)
788{
789 RamDevice *d = SUN4M_RAM(dev);
790
791 memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
792 d->size);
793 sysbus_init_mmio(dev, &d->ram);
794 return 0;
795}
796
797static void ram_init(hwaddr addr, ram_addr_t RAM_size,
798 uint64_t max_mem)
799{
800 DeviceState *dev;
801 SysBusDevice *s;
802 RamDevice *d;
803
804
805 if ((uint64_t)RAM_size > max_mem) {
806 fprintf(stderr,
807 "qemu: Too much memory for this machine: %d, maximum %d\n",
808 (unsigned int)(RAM_size / (1024 * 1024)),
809 (unsigned int)(max_mem / (1024 * 1024)));
810 exit(1);
811 }
812 dev = qdev_create(NULL, "memory");
813 s = SYS_BUS_DEVICE(dev);
814
815 d = SUN4M_RAM(dev);
816 d->size = RAM_size;
817 qdev_init_nofail(dev);
818
819 sysbus_mmio_map(s, 0, addr);
820}
821
822static Property ram_properties[] = {
823 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
824 DEFINE_PROP_END_OF_LIST(),
825};
826
827static void ram_class_init(ObjectClass *klass, void *data)
828{
829 DeviceClass *dc = DEVICE_CLASS(klass);
830 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
831
832 k->init = ram_init1;
833 dc->props = ram_properties;
834}
835
836static const TypeInfo ram_info = {
837 .name = TYPE_SUN4M_MEMORY,
838 .parent = TYPE_SYS_BUS_DEVICE,
839 .instance_size = sizeof(RamDevice),
840 .class_init = ram_class_init,
841};
842
843static void cpu_devinit(const char *cpu_model, unsigned int id,
844 uint64_t prom_addr, qemu_irq **cpu_irqs)
845{
846 CPUState *cs;
847 SPARCCPU *cpu;
848 CPUSPARCState *env;
849
850 cpu = cpu_sparc_init(cpu_model);
851 if (cpu == NULL) {
852 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
853 exit(1);
854 }
855 env = &cpu->env;
856
857 cpu_sparc_set_id(env, id);
858 if (id == 0) {
859 qemu_register_reset(main_cpu_reset, cpu);
860 } else {
861 qemu_register_reset(secondary_cpu_reset, cpu);
862 cs = CPU(cpu);
863 cs->halted = 1;
864 }
865 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
866 env->prom_addr = prom_addr;
867}
868
869static void dummy_fdc_tc(void *opaque, int irq, int level)
870{
871}
872
873static void sun4m_hw_init(const struct sun4m_hwdef *hwdef,
874 MachineState *machine)
875{
876 const char *cpu_model = machine->cpu_model;
877 unsigned int i;
878 void *iommu, *espdma, *ledma, *nvram;
879 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
880 espdma_irq, ledma_irq;
881 qemu_irq esp_reset, dma_enable;
882 qemu_irq fdc_tc;
883 unsigned long kernel_size;
884 DriveInfo *fd[MAX_FD];
885 FWCfgState *fw_cfg;
886 unsigned int num_vsimms;
887
888
889 if (!cpu_model)
890 cpu_model = hwdef->default_cpu_model;
891
892 for(i = 0; i < smp_cpus; i++) {
893 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
894 }
895
896 for (i = smp_cpus; i < MAX_CPUS; i++)
897 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
898
899
900
901 ram_init(0, machine->ram_size, hwdef->max_mem);
902
903 if (!hwdef->ecc_base) {
904 empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size);
905 }
906
907 prom_init(hwdef->slavio_base, bios_name);
908
909 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
910 hwdef->intctl_base + 0x10000ULL,
911 cpu_irqs);
912
913 for (i = 0; i < 32; i++) {
914 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
915 }
916 for (i = 0; i < MAX_CPUS; i++) {
917 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
918 }
919
920 if (hwdef->idreg_base) {
921 idreg_init(hwdef->idreg_base);
922 }
923
924 if (hwdef->afx_base) {
925 afx_init(hwdef->afx_base);
926 }
927
928 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
929 slavio_irq[30]);
930
931 if (hwdef->iommu_pad_base) {
932
933
934
935
936 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
937 }
938
939 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
940 iommu, &espdma_irq, 0);
941
942 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
943 slavio_irq[16], iommu, &ledma_irq, 1);
944
945 if (graphic_depth != 8 && graphic_depth != 24) {
946 error_report("Unsupported depth: %d", graphic_depth);
947 exit (1);
948 }
949 num_vsimms = 0;
950 if (num_vsimms == 0) {
951 if (vga_interface_type == VGA_CG3) {
952 if (graphic_depth != 8) {
953 error_report("Unsupported depth: %d", graphic_depth);
954 exit(1);
955 }
956
957 if (!(graphic_width == 1024 && graphic_height == 768) &&
958 !(graphic_width == 1152 && graphic_height == 900)) {
959 error_report("Unsupported resolution: %d x %d", graphic_width,
960 graphic_height);
961 exit(1);
962 }
963
964
965 cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
966 graphic_width, graphic_height, graphic_depth);
967 } else {
968
969 if (graphic_depth != 8 && graphic_depth != 24) {
970 error_report("Unsupported depth: %d", graphic_depth);
971 exit(1);
972 }
973
974 if (!(graphic_width == 1024 && graphic_height == 768)) {
975 error_report("Unsupported resolution: %d x %d",
976 graphic_width, graphic_height);
977 exit(1);
978 }
979
980 tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000,
981 graphic_width, graphic_height, graphic_depth);
982 }
983 }
984
985 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
986
987 if (hwdef->vsimm[i].reg_base) {
988 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
989 }
990 }
991
992 if (hwdef->sx_base) {
993 empty_slot_init(hwdef->sx_base, 0x2000);
994 }
995
996 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
997
998 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8);
999
1000 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
1001
1002 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
1003 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1004
1005
1006 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
1007 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1008
1009 if (hwdef->apc_base) {
1010 apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0));
1011 }
1012
1013 if (hwdef->fd_base) {
1014
1015 memset(fd, 0, sizeof(fd));
1016 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1017 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
1018 &fdc_tc);
1019 } else {
1020 fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0);
1021 }
1022
1023 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
1024 slavio_irq[30], fdc_tc);
1025
1026 if (drive_get_max_bus(IF_SCSI) > 0) {
1027 fprintf(stderr, "qemu: too many SCSI bus\n");
1028 exit(1);
1029 }
1030
1031 esp_init(hwdef->esp_base, 2,
1032 espdma_memory_read, espdma_memory_write,
1033 espdma, espdma_irq, &esp_reset, &dma_enable);
1034
1035 qdev_connect_gpio_out(espdma, 0, esp_reset);
1036 qdev_connect_gpio_out(espdma, 1, dma_enable);
1037
1038 if (hwdef->cs_base) {
1039 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1040 slavio_irq[5]);
1041 }
1042
1043 if (hwdef->dbri_base) {
1044
1045
1046 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1047
1048 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1049 }
1050
1051 if (hwdef->bpp_base) {
1052
1053 empty_slot_init(hwdef->bpp_base, 0x20);
1054 }
1055
1056 kernel_size = sun4m_load_kernel(machine->kernel_filename,
1057 machine->initrd_filename,
1058 machine->ram_size);
1059
1060 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline,
1061 machine->boot_order, machine->ram_size, kernel_size,
1062 graphic_width, graphic_height, graphic_depth,
1063 hwdef->nvram_machine_id, "Sun4m");
1064
1065 if (hwdef->ecc_base)
1066 ecc_init(hwdef->ecc_base, slavio_irq[28],
1067 hwdef->ecc_version);
1068
1069 fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2);
1070 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1071 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1072 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1073 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1074 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width);
1075 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height);
1076 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1077 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1078 if (machine->kernel_cmdline) {
1079 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1080 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
1081 machine->kernel_cmdline);
1082 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
1083 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1084 strlen(machine->kernel_cmdline) + 1);
1085 } else {
1086 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1087 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1088 }
1089 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1090 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0);
1091 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]);
1092 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1093}
1094
1095enum {
1096 ss5_id = 32,
1097 vger_id,
1098 lx_id,
1099 ss4_id,
1100 scls_id,
1101 sbook_id,
1102 ss10_id = 64,
1103 ss20_id,
1104 ss600mp_id,
1105};
1106
1107static const struct sun4m_hwdef sun4m_hwdefs[] = {
1108
1109 {
1110 .iommu_base = 0x10000000,
1111 .iommu_pad_base = 0x10004000,
1112 .iommu_pad_len = 0x0fffb000,
1113 .tcx_base = 0x50000000,
1114 .cs_base = 0x6c000000,
1115 .slavio_base = 0x70000000,
1116 .ms_kb_base = 0x71000000,
1117 .serial_base = 0x71100000,
1118 .nvram_base = 0x71200000,
1119 .fd_base = 0x71400000,
1120 .counter_base = 0x71d00000,
1121 .intctl_base = 0x71e00000,
1122 .idreg_base = 0x78000000,
1123 .dma_base = 0x78400000,
1124 .esp_base = 0x78800000,
1125 .le_base = 0x78c00000,
1126 .apc_base = 0x6a000000,
1127 .afx_base = 0x6e000000,
1128 .aux1_base = 0x71900000,
1129 .aux2_base = 0x71910000,
1130 .nvram_machine_id = 0x80,
1131 .machine_id = ss5_id,
1132 .iommu_version = 0x05000000,
1133 .max_mem = 0x10000000,
1134 .default_cpu_model = "Fujitsu MB86904",
1135 },
1136
1137 {
1138 .iommu_base = 0xfe0000000ULL,
1139 .tcx_base = 0xe20000000ULL,
1140 .slavio_base = 0xff0000000ULL,
1141 .ms_kb_base = 0xff1000000ULL,
1142 .serial_base = 0xff1100000ULL,
1143 .nvram_base = 0xff1200000ULL,
1144 .fd_base = 0xff1700000ULL,
1145 .counter_base = 0xff1300000ULL,
1146 .intctl_base = 0xff1400000ULL,
1147 .idreg_base = 0xef0000000ULL,
1148 .dma_base = 0xef0400000ULL,
1149 .esp_base = 0xef0800000ULL,
1150 .le_base = 0xef0c00000ULL,
1151 .apc_base = 0xefa000000ULL,
1152 .aux1_base = 0xff1800000ULL,
1153 .aux2_base = 0xff1a01000ULL,
1154 .ecc_base = 0xf00000000ULL,
1155 .ecc_version = 0x10000000,
1156 .nvram_machine_id = 0x72,
1157 .machine_id = ss10_id,
1158 .iommu_version = 0x03000000,
1159 .max_mem = 0xf00000000ULL,
1160 .default_cpu_model = "TI SuperSparc II",
1161 },
1162
1163 {
1164 .iommu_base = 0xfe0000000ULL,
1165 .tcx_base = 0xe20000000ULL,
1166 .slavio_base = 0xff0000000ULL,
1167 .ms_kb_base = 0xff1000000ULL,
1168 .serial_base = 0xff1100000ULL,
1169 .nvram_base = 0xff1200000ULL,
1170 .counter_base = 0xff1300000ULL,
1171 .intctl_base = 0xff1400000ULL,
1172 .dma_base = 0xef0081000ULL,
1173 .esp_base = 0xef0080000ULL,
1174 .le_base = 0xef0060000ULL,
1175 .apc_base = 0xefa000000ULL,
1176 .aux1_base = 0xff1800000ULL,
1177 .aux2_base = 0xff1a01000ULL,
1178 .ecc_base = 0xf00000000ULL,
1179 .ecc_version = 0x00000000,
1180 .nvram_machine_id = 0x71,
1181 .machine_id = ss600mp_id,
1182 .iommu_version = 0x01000000,
1183 .max_mem = 0xf00000000ULL,
1184 .default_cpu_model = "TI SuperSparc II",
1185 },
1186
1187 {
1188 .iommu_base = 0xfe0000000ULL,
1189 .tcx_base = 0xe20000000ULL,
1190 .slavio_base = 0xff0000000ULL,
1191 .ms_kb_base = 0xff1000000ULL,
1192 .serial_base = 0xff1100000ULL,
1193 .nvram_base = 0xff1200000ULL,
1194 .fd_base = 0xff1700000ULL,
1195 .counter_base = 0xff1300000ULL,
1196 .intctl_base = 0xff1400000ULL,
1197 .idreg_base = 0xef0000000ULL,
1198 .dma_base = 0xef0400000ULL,
1199 .esp_base = 0xef0800000ULL,
1200 .le_base = 0xef0c00000ULL,
1201 .bpp_base = 0xef4800000ULL,
1202 .apc_base = 0xefa000000ULL,
1203 .aux1_base = 0xff1800000ULL,
1204 .aux2_base = 0xff1a01000ULL,
1205 .dbri_base = 0xee0000000ULL,
1206 .sx_base = 0xf80000000ULL,
1207 .vsimm = {
1208 {
1209 .reg_base = 0x9c000000ULL,
1210 .vram_base = 0xfc000000ULL
1211 }, {
1212 .reg_base = 0x90000000ULL,
1213 .vram_base = 0xf0000000ULL
1214 }, {
1215 .reg_base = 0x94000000ULL
1216 }, {
1217 .reg_base = 0x98000000ULL
1218 }
1219 },
1220 .ecc_base = 0xf00000000ULL,
1221 .ecc_version = 0x20000000,
1222 .nvram_machine_id = 0x72,
1223 .machine_id = ss20_id,
1224 .iommu_version = 0x13000000,
1225 .max_mem = 0xf00000000ULL,
1226 .default_cpu_model = "TI SuperSparc II",
1227 },
1228
1229 {
1230 .iommu_base = 0x10000000,
1231 .tcx_base = 0x50000000,
1232 .slavio_base = 0x70000000,
1233 .ms_kb_base = 0x71000000,
1234 .serial_base = 0x71100000,
1235 .nvram_base = 0x71200000,
1236 .fd_base = 0x71400000,
1237 .counter_base = 0x71d00000,
1238 .intctl_base = 0x71e00000,
1239 .idreg_base = 0x78000000,
1240 .dma_base = 0x78400000,
1241 .esp_base = 0x78800000,
1242 .le_base = 0x78c00000,
1243 .apc_base = 0x71300000,
1244 .aux1_base = 0x71900000,
1245 .aux2_base = 0x71910000,
1246 .nvram_machine_id = 0x80,
1247 .machine_id = vger_id,
1248 .iommu_version = 0x05000000,
1249 .max_mem = 0x10000000,
1250 .default_cpu_model = "Fujitsu MB86904",
1251 },
1252
1253 {
1254 .iommu_base = 0x10000000,
1255 .iommu_pad_base = 0x10004000,
1256 .iommu_pad_len = 0x0fffb000,
1257 .tcx_base = 0x50000000,
1258 .slavio_base = 0x70000000,
1259 .ms_kb_base = 0x71000000,
1260 .serial_base = 0x71100000,
1261 .nvram_base = 0x71200000,
1262 .fd_base = 0x71400000,
1263 .counter_base = 0x71d00000,
1264 .intctl_base = 0x71e00000,
1265 .idreg_base = 0x78000000,
1266 .dma_base = 0x78400000,
1267 .esp_base = 0x78800000,
1268 .le_base = 0x78c00000,
1269 .aux1_base = 0x71900000,
1270 .aux2_base = 0x71910000,
1271 .nvram_machine_id = 0x80,
1272 .machine_id = lx_id,
1273 .iommu_version = 0x04000000,
1274 .max_mem = 0x10000000,
1275 .default_cpu_model = "TI MicroSparc I",
1276 },
1277
1278 {
1279 .iommu_base = 0x10000000,
1280 .tcx_base = 0x50000000,
1281 .cs_base = 0x6c000000,
1282 .slavio_base = 0x70000000,
1283 .ms_kb_base = 0x71000000,
1284 .serial_base = 0x71100000,
1285 .nvram_base = 0x71200000,
1286 .fd_base = 0x71400000,
1287 .counter_base = 0x71d00000,
1288 .intctl_base = 0x71e00000,
1289 .idreg_base = 0x78000000,
1290 .dma_base = 0x78400000,
1291 .esp_base = 0x78800000,
1292 .le_base = 0x78c00000,
1293 .apc_base = 0x6a000000,
1294 .aux1_base = 0x71900000,
1295 .aux2_base = 0x71910000,
1296 .nvram_machine_id = 0x80,
1297 .machine_id = ss4_id,
1298 .iommu_version = 0x05000000,
1299 .max_mem = 0x10000000,
1300 .default_cpu_model = "Fujitsu MB86904",
1301 },
1302
1303 {
1304 .iommu_base = 0x10000000,
1305 .tcx_base = 0x50000000,
1306 .slavio_base = 0x70000000,
1307 .ms_kb_base = 0x71000000,
1308 .serial_base = 0x71100000,
1309 .nvram_base = 0x71200000,
1310 .fd_base = 0x71400000,
1311 .counter_base = 0x71d00000,
1312 .intctl_base = 0x71e00000,
1313 .idreg_base = 0x78000000,
1314 .dma_base = 0x78400000,
1315 .esp_base = 0x78800000,
1316 .le_base = 0x78c00000,
1317 .apc_base = 0x6a000000,
1318 .aux1_base = 0x71900000,
1319 .aux2_base = 0x71910000,
1320 .nvram_machine_id = 0x80,
1321 .machine_id = scls_id,
1322 .iommu_version = 0x05000000,
1323 .max_mem = 0x10000000,
1324 .default_cpu_model = "TI MicroSparc I",
1325 },
1326
1327 {
1328 .iommu_base = 0x10000000,
1329 .tcx_base = 0x50000000,
1330 .slavio_base = 0x70000000,
1331 .ms_kb_base = 0x71000000,
1332 .serial_base = 0x71100000,
1333 .nvram_base = 0x71200000,
1334 .fd_base = 0x71400000,
1335 .counter_base = 0x71d00000,
1336 .intctl_base = 0x71e00000,
1337 .idreg_base = 0x78000000,
1338 .dma_base = 0x78400000,
1339 .esp_base = 0x78800000,
1340 .le_base = 0x78c00000,
1341 .apc_base = 0x6a000000,
1342 .aux1_base = 0x71900000,
1343 .aux2_base = 0x71910000,
1344 .nvram_machine_id = 0x80,
1345 .machine_id = sbook_id,
1346 .iommu_version = 0x05000000,
1347 .max_mem = 0x10000000,
1348 .default_cpu_model = "TI MicroSparc I",
1349 },
1350};
1351
1352
1353static void ss5_init(MachineState *machine)
1354{
1355 sun4m_hw_init(&sun4m_hwdefs[0], machine);
1356}
1357
1358
1359static void ss10_init(MachineState *machine)
1360{
1361 sun4m_hw_init(&sun4m_hwdefs[1], machine);
1362}
1363
1364
1365static void ss600mp_init(MachineState *machine)
1366{
1367 sun4m_hw_init(&sun4m_hwdefs[2], machine);
1368}
1369
1370
1371static void ss20_init(MachineState *machine)
1372{
1373 sun4m_hw_init(&sun4m_hwdefs[3], machine);
1374}
1375
1376
1377static void vger_init(MachineState *machine)
1378{
1379 sun4m_hw_init(&sun4m_hwdefs[4], machine);
1380}
1381
1382
1383static void ss_lx_init(MachineState *machine)
1384{
1385 sun4m_hw_init(&sun4m_hwdefs[5], machine);
1386}
1387
1388
1389static void ss4_init(MachineState *machine)
1390{
1391 sun4m_hw_init(&sun4m_hwdefs[6], machine);
1392}
1393
1394
1395static void scls_init(MachineState *machine)
1396{
1397 sun4m_hw_init(&sun4m_hwdefs[7], machine);
1398}
1399
1400
1401static void sbook_init(MachineState *machine)
1402{
1403 sun4m_hw_init(&sun4m_hwdefs[8], machine);
1404}
1405
1406static void ss5_class_init(ObjectClass *oc, void *data)
1407{
1408 MachineClass *mc = MACHINE_CLASS(oc);
1409
1410 mc->desc = "Sun4m platform, SPARCstation 5";
1411 mc->init = ss5_init;
1412 mc->block_default_type = IF_SCSI;
1413 mc->is_default = 1;
1414 mc->default_boot_order = "c";
1415}
1416
1417static const TypeInfo ss5_type = {
1418 .name = MACHINE_TYPE_NAME("SS-5"),
1419 .parent = TYPE_MACHINE,
1420 .class_init = ss5_class_init,
1421};
1422
1423static void ss10_class_init(ObjectClass *oc, void *data)
1424{
1425 MachineClass *mc = MACHINE_CLASS(oc);
1426
1427 mc->desc = "Sun4m platform, SPARCstation 10";
1428 mc->init = ss10_init;
1429 mc->block_default_type = IF_SCSI;
1430 mc->max_cpus = 4;
1431 mc->default_boot_order = "c";
1432}
1433
1434static const TypeInfo ss10_type = {
1435 .name = MACHINE_TYPE_NAME("SS-10"),
1436 .parent = TYPE_MACHINE,
1437 .class_init = ss10_class_init,
1438};
1439
1440static void ss600mp_class_init(ObjectClass *oc, void *data)
1441{
1442 MachineClass *mc = MACHINE_CLASS(oc);
1443
1444 mc->desc = "Sun4m platform, SPARCserver 600MP";
1445 mc->init = ss600mp_init;
1446 mc->block_default_type = IF_SCSI;
1447 mc->max_cpus = 4;
1448 mc->default_boot_order = "c";
1449}
1450
1451static const TypeInfo ss600mp_type = {
1452 .name = MACHINE_TYPE_NAME("SS-600MP"),
1453 .parent = TYPE_MACHINE,
1454 .class_init = ss600mp_class_init,
1455};
1456
1457static void ss20_class_init(ObjectClass *oc, void *data)
1458{
1459 MachineClass *mc = MACHINE_CLASS(oc);
1460
1461 mc->desc = "Sun4m platform, SPARCstation 20";
1462 mc->init = ss20_init;
1463 mc->block_default_type = IF_SCSI;
1464 mc->max_cpus = 4;
1465 mc->default_boot_order = "c";
1466}
1467
1468static const TypeInfo ss20_type = {
1469 .name = MACHINE_TYPE_NAME("SS-20"),
1470 .parent = TYPE_MACHINE,
1471 .class_init = ss20_class_init,
1472};
1473
1474static void voyager_class_init(ObjectClass *oc, void *data)
1475{
1476 MachineClass *mc = MACHINE_CLASS(oc);
1477
1478 mc->desc = "Sun4m platform, SPARCstation Voyager";
1479 mc->init = vger_init;
1480 mc->block_default_type = IF_SCSI;
1481 mc->default_boot_order = "c";
1482}
1483
1484static const TypeInfo voyager_type = {
1485 .name = MACHINE_TYPE_NAME("Voyager"),
1486 .parent = TYPE_MACHINE,
1487 .class_init = voyager_class_init,
1488};
1489
1490static void ss_lx_class_init(ObjectClass *oc, void *data)
1491{
1492 MachineClass *mc = MACHINE_CLASS(oc);
1493
1494 mc->desc = "Sun4m platform, SPARCstation LX";
1495 mc->init = ss_lx_init;
1496 mc->block_default_type = IF_SCSI;
1497 mc->default_boot_order = "c";
1498}
1499
1500static const TypeInfo ss_lx_type = {
1501 .name = MACHINE_TYPE_NAME("LX"),
1502 .parent = TYPE_MACHINE,
1503 .class_init = ss_lx_class_init,
1504};
1505
1506static void ss4_class_init(ObjectClass *oc, void *data)
1507{
1508 MachineClass *mc = MACHINE_CLASS(oc);
1509
1510 mc->desc = "Sun4m platform, SPARCstation 4";
1511 mc->init = ss4_init;
1512 mc->block_default_type = IF_SCSI;
1513 mc->default_boot_order = "c";
1514}
1515
1516static const TypeInfo ss4_type = {
1517 .name = MACHINE_TYPE_NAME("SS-4"),
1518 .parent = TYPE_MACHINE,
1519 .class_init = ss4_class_init,
1520};
1521
1522static void scls_class_init(ObjectClass *oc, void *data)
1523{
1524 MachineClass *mc = MACHINE_CLASS(oc);
1525
1526 mc->desc = "Sun4m platform, SPARCClassic";
1527 mc->init = scls_init;
1528 mc->block_default_type = IF_SCSI;
1529 mc->default_boot_order = "c";
1530}
1531
1532static const TypeInfo scls_type = {
1533 .name = MACHINE_TYPE_NAME("SPARCClassic"),
1534 .parent = TYPE_MACHINE,
1535 .class_init = scls_class_init,
1536};
1537
1538static void sbook_class_init(ObjectClass *oc, void *data)
1539{
1540 MachineClass *mc = MACHINE_CLASS(oc);
1541
1542 mc->desc = "Sun4m platform, SPARCbook";
1543 mc->init = sbook_init;
1544 mc->block_default_type = IF_SCSI;
1545 mc->default_boot_order = "c";
1546}
1547
1548static const TypeInfo sbook_type = {
1549 .name = MACHINE_TYPE_NAME("SPARCbook"),
1550 .parent = TYPE_MACHINE,
1551 .class_init = sbook_class_init,
1552};
1553
1554static void sun4m_register_types(void)
1555{
1556 type_register_static(&idreg_info);
1557 type_register_static(&afx_info);
1558 type_register_static(&prom_info);
1559 type_register_static(&ram_info);
1560
1561 type_register_static(&ss5_type);
1562 type_register_static(&ss10_type);
1563 type_register_static(&ss600mp_type);
1564 type_register_static(&ss20_type);
1565 type_register_static(&voyager_type);
1566 type_register_static(&ss_lx_type);
1567 type_register_static(&ss4_type);
1568 type_register_static(&scls_type);
1569 type_register_static(&sbook_type);
1570}
1571
1572type_init(sun4m_register_types)
1573
