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19#include "qemu/osdep.h"
20#include "hw/sysbus.h"
21#include "qemu/timer.h"
22
23#ifdef CADENCE_TTC_ERR_DEBUG
24#define DB_PRINT(...) do { \
25 fprintf(stderr, ": %s: ", __func__); \
26 fprintf(stderr, ## __VA_ARGS__); \
27 } while (0);
28#else
29 #define DB_PRINT(...)
30#endif
31
32#define COUNTER_INTR_IV 0x00000001
33#define COUNTER_INTR_M1 0x00000002
34#define COUNTER_INTR_M2 0x00000004
35#define COUNTER_INTR_M3 0x00000008
36#define COUNTER_INTR_OV 0x00000010
37#define COUNTER_INTR_EV 0x00000020
38
39#define COUNTER_CTRL_DIS 0x00000001
40#define COUNTER_CTRL_INT 0x00000002
41#define COUNTER_CTRL_DEC 0x00000004
42#define COUNTER_CTRL_MATCH 0x00000008
43#define COUNTER_CTRL_RST 0x00000010
44
45#define CLOCK_CTRL_PS_EN 0x00000001
46#define CLOCK_CTRL_PS_V 0x0000001e
47
48typedef struct {
49 QEMUTimer *timer;
50 int freq;
51
52 uint32_t reg_clock;
53 uint32_t reg_count;
54 uint32_t reg_value;
55 uint16_t reg_interval;
56 uint16_t reg_match[3];
57 uint32_t reg_intr;
58 uint32_t reg_intr_en;
59 uint32_t reg_event_ctrl;
60 uint32_t reg_event;
61
62 uint64_t cpu_time;
63 unsigned int cpu_time_valid;
64
65 qemu_irq irq;
66} CadenceTimerState;
67
68#define TYPE_CADENCE_TTC "cadence_ttc"
69#define CADENCE_TTC(obj) \
70 OBJECT_CHECK(CadenceTTCState, (obj), TYPE_CADENCE_TTC)
71
72typedef struct CadenceTTCState {
73 SysBusDevice parent_obj;
74
75 MemoryRegion iomem;
76 CadenceTimerState timer[3];
77} CadenceTTCState;
78
79static void cadence_timer_update(CadenceTimerState *s)
80{
81 qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
82}
83
84static CadenceTimerState *cadence_timer_from_addr(void *opaque,
85 hwaddr offset)
86{
87 unsigned int index;
88 CadenceTTCState *s = (CadenceTTCState *)opaque;
89
90 index = (offset >> 2) % 3;
91
92 return &s->timer[index];
93}
94
95static uint64_t cadence_timer_get_ns(CadenceTimerState *s, uint64_t timer_steps)
96{
97
98
99 assert(timer_steps <= 1ULL << 32);
100
101 uint64_t r = timer_steps * 1000000000ULL;
102 if (s->reg_clock & CLOCK_CTRL_PS_EN) {
103 r >>= 16 - (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
104 } else {
105 r >>= 16;
106 }
107 r /= (uint64_t)s->freq;
108
109 r = MAX(r, 1);
110 return r;
111}
112
113static uint64_t cadence_timer_get_steps(CadenceTimerState *s, uint64_t ns)
114{
115 uint64_t to_divide = 1000000000ULL;
116
117 uint64_t r = ns;
118
119
120 while (r >= 8ULL << 30 && to_divide > 1) {
121 r /= 1000;
122 to_divide /= 1000;
123 }
124 r <<= 16;
125
126 while (r >= 8ULL << 30 && to_divide > 1) {
127 r /= 1000;
128 to_divide /= 1000;
129 }
130 r *= (uint64_t)s->freq;
131 if (s->reg_clock & CLOCK_CTRL_PS_EN) {
132 r /= 1 << (((s->reg_clock & CLOCK_CTRL_PS_V) >> 1) + 1);
133 }
134
135 r /= to_divide;
136 return r;
137}
138
139
140
141static inline int64_t is_between(int64_t x, int64_t a, int64_t b)
142{
143 if (a < b) {
144 return x > a && x <= b;
145 }
146 return x < a && x >= b;
147}
148
149static void cadence_timer_run(CadenceTimerState *s)
150{
151 int i;
152 int64_t event_interval, next_value;
153
154 assert(s->cpu_time_valid);
155
156 if (s->reg_count & COUNTER_CTRL_DIS) {
157 s->cpu_time_valid = 0;
158 return;
159 }
160
161 {
162 int64_t interval = (uint64_t)((s->reg_count & COUNTER_CTRL_INT) ?
163 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
164 next_value = (s->reg_count & COUNTER_CTRL_DEC) ? -1ULL : interval;
165 for (i = 0; i < 3; ++i) {
166 int64_t cand = (uint64_t)s->reg_match[i] << 16;
167 if (is_between(cand, (uint64_t)s->reg_value, next_value)) {
168 next_value = cand;
169 }
170 }
171 }
172 DB_PRINT("next timer event value: %09llx\n",
173 (unsigned long long)next_value);
174
175 event_interval = next_value - (int64_t)s->reg_value;
176 event_interval = (event_interval < 0) ? -event_interval : event_interval;
177
178 timer_mod(s->timer, s->cpu_time +
179 cadence_timer_get_ns(s, event_interval));
180}
181
182static void cadence_timer_sync(CadenceTimerState *s)
183{
184 int i;
185 int64_t r, x;
186 int64_t interval = ((s->reg_count & COUNTER_CTRL_INT) ?
187 (int64_t)s->reg_interval + 1 : 0x10000ULL) << 16;
188 uint64_t old_time = s->cpu_time;
189
190 s->cpu_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
191 DB_PRINT("cpu time: %lld ns\n", (long long)old_time);
192
193 if (!s->cpu_time_valid || old_time == s->cpu_time) {
194 s->cpu_time_valid = 1;
195 return;
196 }
197
198 r = (int64_t)cadence_timer_get_steps(s, s->cpu_time - old_time);
199 x = (int64_t)s->reg_value + ((s->reg_count & COUNTER_CTRL_DEC) ? -r : r);
200
201 for (i = 0; i < 3; ++i) {
202 int64_t m = (int64_t)s->reg_match[i] << 16;
203 if (m > interval) {
204 continue;
205 }
206
207
208 if (is_between(m, s->reg_value, x) ||
209 is_between(m + interval, s->reg_value, x) ||
210 is_between(m - interval, s->reg_value, x)) {
211 s->reg_intr |= (2 << i);
212 }
213 }
214 if ((x < 0) || (x >= interval)) {
215 s->reg_intr |= (s->reg_count & COUNTER_CTRL_INT) ?
216 COUNTER_INTR_IV : COUNTER_INTR_OV;
217 }
218 while (x < 0) {
219 x += interval;
220 }
221 s->reg_value = (uint32_t)(x % interval);
222 cadence_timer_update(s);
223}
224
225static void cadence_timer_tick(void *opaque)
226{
227 CadenceTimerState *s = opaque;
228
229 DB_PRINT("\n");
230 cadence_timer_sync(s);
231 cadence_timer_run(s);
232}
233
234static uint32_t cadence_ttc_read_imp(void *opaque, hwaddr offset)
235{
236 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
237 uint32_t value;
238
239 cadence_timer_sync(s);
240 cadence_timer_run(s);
241
242 switch (offset) {
243 case 0x00:
244 case 0x04:
245 case 0x08:
246 return s->reg_clock;
247
248 case 0x0c:
249 case 0x10:
250 case 0x14:
251 return s->reg_count;
252
253 case 0x18:
254 case 0x1c:
255 case 0x20:
256 return (uint16_t)(s->reg_value >> 16);
257
258 case 0x24:
259 case 0x28:
260 case 0x2c:
261 return s->reg_interval;
262
263 case 0x30:
264 case 0x34:
265 case 0x38:
266 return s->reg_match[0];
267
268 case 0x3c:
269 case 0x40:
270 case 0x44:
271 return s->reg_match[1];
272
273 case 0x48:
274 case 0x4c:
275 case 0x50:
276 return s->reg_match[2];
277
278 case 0x54:
279 case 0x58:
280 case 0x5c:
281
282 value = s->reg_intr;
283 s->reg_intr = 0;
284 cadence_timer_update(s);
285 return value;
286
287 case 0x60:
288 case 0x64:
289 case 0x68:
290 return s->reg_intr_en;
291
292 case 0x6c:
293 case 0x70:
294 case 0x74:
295 return s->reg_event_ctrl;
296
297 case 0x78:
298 case 0x7c:
299 case 0x80:
300 return s->reg_event;
301
302 default:
303 return 0;
304 }
305}
306
307static uint64_t cadence_ttc_read(void *opaque, hwaddr offset,
308 unsigned size)
309{
310 uint32_t ret = cadence_ttc_read_imp(opaque, offset);
311
312 DB_PRINT("addr: %08x data: %08x\n", (unsigned)offset, (unsigned)ret);
313 return ret;
314}
315
316static void cadence_ttc_write(void *opaque, hwaddr offset,
317 uint64_t value, unsigned size)
318{
319 CadenceTimerState *s = cadence_timer_from_addr(opaque, offset);
320
321 DB_PRINT("addr: %08x data %08x\n", (unsigned)offset, (unsigned)value);
322
323 cadence_timer_sync(s);
324
325 switch (offset) {
326 case 0x00:
327 case 0x04:
328 case 0x08:
329 s->reg_clock = value & 0x3F;
330 break;
331
332 case 0x0c:
333 case 0x10:
334 case 0x14:
335 if (value & COUNTER_CTRL_RST) {
336 s->reg_value = 0;
337 }
338 s->reg_count = value & 0x3f & ~COUNTER_CTRL_RST;
339 break;
340
341 case 0x24:
342 case 0x28:
343 case 0x2c:
344 s->reg_interval = value & 0xffff;
345 break;
346
347 case 0x30:
348 case 0x34:
349 case 0x38:
350 s->reg_match[0] = value & 0xffff;
351 break;
352
353 case 0x3c:
354 case 0x40:
355 case 0x44:
356 s->reg_match[1] = value & 0xffff;
357 break;
358
359 case 0x48:
360 case 0x4c:
361 case 0x50:
362 s->reg_match[2] = value & 0xffff;
363 break;
364
365 case 0x54:
366 case 0x58:
367 case 0x5c:
368 break;
369
370 case 0x60:
371 case 0x64:
372 case 0x68:
373 s->reg_intr_en = value & 0x3f;
374 break;
375
376 case 0x6c:
377 case 0x70:
378 case 0x74:
379 s->reg_event_ctrl = value & 0x07;
380 break;
381
382 default:
383 return;
384 }
385
386 cadence_timer_run(s);
387 cadence_timer_update(s);
388}
389
390static const MemoryRegionOps cadence_ttc_ops = {
391 .read = cadence_ttc_read,
392 .write = cadence_ttc_write,
393 .endianness = DEVICE_NATIVE_ENDIAN,
394};
395
396static void cadence_timer_reset(CadenceTimerState *s)
397{
398 s->reg_count = 0x21;
399}
400
401static void cadence_timer_init(uint32_t freq, CadenceTimerState *s)
402{
403 memset(s, 0, sizeof(CadenceTimerState));
404 s->freq = freq;
405
406 cadence_timer_reset(s);
407
408 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cadence_timer_tick, s);
409}
410
411static void cadence_ttc_init(Object *obj)
412{
413 CadenceTTCState *s = CADENCE_TTC(obj);
414 int i;
415
416 for (i = 0; i < 3; ++i) {
417 cadence_timer_init(133000000, &s->timer[i]);
418 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->timer[i].irq);
419 }
420
421 memory_region_init_io(&s->iomem, obj, &cadence_ttc_ops, s,
422 "timer", 0x1000);
423 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
424}
425
426static void cadence_timer_pre_save(void *opaque)
427{
428 cadence_timer_sync((CadenceTimerState *)opaque);
429}
430
431static int cadence_timer_post_load(void *opaque, int version_id)
432{
433 CadenceTimerState *s = opaque;
434
435 s->cpu_time_valid = 0;
436 cadence_timer_sync(s);
437 cadence_timer_run(s);
438 cadence_timer_update(s);
439 return 0;
440}
441
442static const VMStateDescription vmstate_cadence_timer = {
443 .name = "cadence_timer",
444 .version_id = 1,
445 .minimum_version_id = 1,
446 .pre_save = cadence_timer_pre_save,
447 .post_load = cadence_timer_post_load,
448 .fields = (VMStateField[]) {
449 VMSTATE_UINT32(reg_clock, CadenceTimerState),
450 VMSTATE_UINT32(reg_count, CadenceTimerState),
451 VMSTATE_UINT32(reg_value, CadenceTimerState),
452 VMSTATE_UINT16(reg_interval, CadenceTimerState),
453 VMSTATE_UINT16_ARRAY(reg_match, CadenceTimerState, 3),
454 VMSTATE_UINT32(reg_intr, CadenceTimerState),
455 VMSTATE_UINT32(reg_intr_en, CadenceTimerState),
456 VMSTATE_UINT32(reg_event_ctrl, CadenceTimerState),
457 VMSTATE_UINT32(reg_event, CadenceTimerState),
458 VMSTATE_END_OF_LIST()
459 }
460};
461
462static const VMStateDescription vmstate_cadence_ttc = {
463 .name = "cadence_TTC",
464 .version_id = 1,
465 .minimum_version_id = 1,
466 .fields = (VMStateField[]) {
467 VMSTATE_STRUCT_ARRAY(timer, CadenceTTCState, 3, 0,
468 vmstate_cadence_timer,
469 CadenceTimerState),
470 VMSTATE_END_OF_LIST()
471 }
472};
473
474static void cadence_ttc_class_init(ObjectClass *klass, void *data)
475{
476 DeviceClass *dc = DEVICE_CLASS(klass);
477
478 dc->vmsd = &vmstate_cadence_ttc;
479}
480
481static const TypeInfo cadence_ttc_info = {
482 .name = TYPE_CADENCE_TTC,
483 .parent = TYPE_SYS_BUS_DEVICE,
484 .instance_size = sizeof(CadenceTTCState),
485 .instance_init = cadence_ttc_init,
486 .class_init = cadence_ttc_class_init,
487};
488
489static void cadence_ttc_register_types(void)
490{
491 type_register_static(&cadence_ttc_info);
492}
493
494type_init(cadence_ttc_register_types)
495