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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "qemu/timer.h"
31#include "qemu-common.h"
32#include "qemu/bcd.h"
33#include "hw/ptimer.h"
34
35#include "hw/hw.h"
36#include "sysemu/sysemu.h"
37
38#include "hw/arm/exynos4210.h"
39
40#define DEBUG_RTC 0
41
42#if DEBUG_RTC
43#define DPRINTF(fmt, ...) \
44 do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \
45 ## __VA_ARGS__); } while (0)
46#else
47#define DPRINTF(fmt, ...) do {} while (0)
48#endif
49
50#define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100
51
52#define INTP 0x0030
53#define RTCCON 0x0040
54#define TICCNT 0x0044
55#define RTCALM 0x0050
56#define ALMSEC 0x0054
57#define ALMMIN 0x0058
58#define ALMHOUR 0x005C
59#define ALMDAY 0x0060
60#define ALMMON 0x0064
61#define ALMYEAR 0x0068
62#define BCDSEC 0x0070
63#define BCDMIN 0x0074
64#define BCDHOUR 0x0078
65#define BCDDAY 0x007C
66#define BCDDAYWEEK 0x0080
67#define BCDMON 0x0084
68#define BCDYEAR 0x0088
69#define CURTICNT 0x0090
70
71#define TICK_TIMER_ENABLE 0x0100
72#define TICNT_THRESHOLD 2
73
74
75#define RTC_ENABLE 0x0001
76
77#define INTP_TICK_ENABLE 0x0001
78#define INTP_ALM_ENABLE 0x0002
79
80#define ALARM_INT_ENABLE 0x0040
81
82#define RTC_BASE_FREQ 32768
83
84#define TYPE_EXYNOS4210_RTC "exynos4210.rtc"
85#define EXYNOS4210_RTC(obj) \
86 OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC)
87
88typedef struct Exynos4210RTCState {
89 SysBusDevice parent_obj;
90
91 MemoryRegion iomem;
92
93
94 uint32_t reg_intp;
95 uint32_t reg_rtccon;
96 uint32_t reg_ticcnt;
97 uint32_t reg_rtcalm;
98 uint32_t reg_almsec;
99 uint32_t reg_almmin;
100 uint32_t reg_almhour;
101 uint32_t reg_almday;
102 uint32_t reg_almmon;
103 uint32_t reg_almyear;
104 uint32_t reg_curticcnt;
105
106 ptimer_state *ptimer;
107 ptimer_state *ptimer_1Hz;
108 uint32_t freq;
109
110 qemu_irq tick_irq;
111 qemu_irq alm_irq;
112
113 struct tm current_tm;
114} Exynos4210RTCState;
115
116#define TICCKSEL(value) ((value & (0x0F << 4)) >> 4)
117
118
119static const VMStateDescription vmstate_exynos4210_rtc_state = {
120 .name = "exynos4210.rtc",
121 .version_id = 1,
122 .minimum_version_id = 1,
123 .fields = (VMStateField[]) {
124 VMSTATE_UINT32(reg_intp, Exynos4210RTCState),
125 VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState),
126 VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState),
127 VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState),
128 VMSTATE_UINT32(reg_almsec, Exynos4210RTCState),
129 VMSTATE_UINT32(reg_almmin, Exynos4210RTCState),
130 VMSTATE_UINT32(reg_almhour, Exynos4210RTCState),
131 VMSTATE_UINT32(reg_almday, Exynos4210RTCState),
132 VMSTATE_UINT32(reg_almmon, Exynos4210RTCState),
133 VMSTATE_UINT32(reg_almyear, Exynos4210RTCState),
134 VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState),
135 VMSTATE_PTIMER(ptimer, Exynos4210RTCState),
136 VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState),
137 VMSTATE_UINT32(freq, Exynos4210RTCState),
138 VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState),
139 VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState),
140 VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState),
141 VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState),
142 VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState),
143 VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState),
144 VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState),
145 VMSTATE_END_OF_LIST()
146 }
147};
148
149#define BCD3DIGITS(x) \
150 ((uint32_t)to_bcd((uint8_t)(x % 100)) + \
151 ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8))
152
153static void check_alarm_raise(Exynos4210RTCState *s)
154{
155 unsigned int alarm_raise = 0;
156 struct tm stm = s->current_tm;
157
158 if ((s->reg_rtcalm & 0x01) &&
159 (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) {
160 alarm_raise = 1;
161 }
162 if ((s->reg_rtcalm & 0x02) &&
163 (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) {
164 alarm_raise = 1;
165 }
166 if ((s->reg_rtcalm & 0x04) &&
167 (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) {
168 alarm_raise = 1;
169 }
170 if ((s->reg_rtcalm & 0x08) &&
171 (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) {
172 alarm_raise = 1;
173 }
174 if ((s->reg_rtcalm & 0x10) &&
175 (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) {
176 alarm_raise = 1;
177 }
178 if ((s->reg_rtcalm & 0x20) &&
179 (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) {
180 alarm_raise = 1;
181 }
182
183 if (alarm_raise) {
184 DPRINTF("ALARM IRQ\n");
185
186 s->reg_intp |= INTP_ALM_ENABLE;
187 qemu_irq_raise(s->alm_irq);
188 }
189}
190
191
192
193
194
195
196static void exynos4210_rtc_update_freq(Exynos4210RTCState *s,
197 uint32_t reg_value)
198{
199 uint32_t freq;
200
201 freq = s->freq;
202
203 s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value));
204
205 if (freq != s->freq) {
206 ptimer_set_freq(s->ptimer, s->freq);
207 DPRINTF("freq=%dHz\n", s->freq);
208 }
209}
210
211
212static int get_days_in_month(int month, int year)
213{
214 static const int days_tab[12] = {
215 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
216 };
217 int d;
218 if ((unsigned)month >= 12) {
219 return 31;
220 }
221 d = days_tab[month];
222 if (month == 1) {
223 if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) {
224 d++;
225 }
226 }
227 return d;
228}
229
230
231static void rtc_next_second(struct tm *tm)
232{
233 int days_in_month;
234
235 tm->tm_sec++;
236 if ((unsigned)tm->tm_sec >= 60) {
237 tm->tm_sec = 0;
238 tm->tm_min++;
239 if ((unsigned)tm->tm_min >= 60) {
240 tm->tm_min = 0;
241 tm->tm_hour++;
242 if ((unsigned)tm->tm_hour >= 24) {
243 tm->tm_hour = 0;
244
245 tm->tm_wday++;
246 if ((unsigned)tm->tm_wday >= 7) {
247 tm->tm_wday = 0;
248 }
249 days_in_month = get_days_in_month(tm->tm_mon,
250 tm->tm_year + 1900);
251 tm->tm_mday++;
252 if (tm->tm_mday < 1) {
253 tm->tm_mday = 1;
254 } else if (tm->tm_mday > days_in_month) {
255 tm->tm_mday = 1;
256 tm->tm_mon++;
257 if (tm->tm_mon >= 12) {
258 tm->tm_mon = 0;
259 tm->tm_year++;
260 }
261 }
262 }
263 }
264 }
265}
266
267
268
269
270static void exynos4210_rtc_tick(void *opaque)
271{
272 Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
273
274 DPRINTF("TICK IRQ\n");
275
276 s->reg_intp |= INTP_TICK_ENABLE;
277
278 qemu_irq_raise(s->tick_irq);
279
280
281 ptimer_set_count(s->ptimer, s->reg_ticcnt);
282 ptimer_run(s->ptimer, 1);
283}
284
285
286
287
288static void exynos4210_rtc_1Hz_tick(void *opaque)
289{
290 Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
291
292 rtc_next_second(&s->current_tm);
293
294
295
296 if (s->reg_rtcalm & ALARM_INT_ENABLE) {
297 check_alarm_raise(s);
298 }
299
300 ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
301 ptimer_run(s->ptimer_1Hz, 1);
302}
303
304
305
306
307static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset,
308 unsigned size)
309{
310 uint32_t value = 0;
311 Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
312
313 switch (offset) {
314 case INTP:
315 value = s->reg_intp;
316 break;
317 case RTCCON:
318 value = s->reg_rtccon;
319 break;
320 case TICCNT:
321 value = s->reg_ticcnt;
322 break;
323 case RTCALM:
324 value = s->reg_rtcalm;
325 break;
326 case ALMSEC:
327 value = s->reg_almsec;
328 break;
329 case ALMMIN:
330 value = s->reg_almmin;
331 break;
332 case ALMHOUR:
333 value = s->reg_almhour;
334 break;
335 case ALMDAY:
336 value = s->reg_almday;
337 break;
338 case ALMMON:
339 value = s->reg_almmon;
340 break;
341 case ALMYEAR:
342 value = s->reg_almyear;
343 break;
344
345 case BCDSEC:
346 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec);
347 break;
348 case BCDMIN:
349 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min);
350 break;
351 case BCDHOUR:
352 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour);
353 break;
354 case BCDDAYWEEK:
355 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday);
356 break;
357 case BCDDAY:
358 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday);
359 break;
360 case BCDMON:
361 value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1);
362 break;
363 case BCDYEAR:
364 value = BCD3DIGITS(s->current_tm.tm_year);
365 break;
366
367 case CURTICNT:
368 s->reg_curticcnt = ptimer_get_count(s->ptimer);
369 value = s->reg_curticcnt;
370 break;
371
372 default:
373 fprintf(stderr,
374 "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n",
375 offset);
376 break;
377 }
378 return value;
379}
380
381
382
383
384static void exynos4210_rtc_write(void *opaque, hwaddr offset,
385 uint64_t value, unsigned size)
386{
387 Exynos4210RTCState *s = (Exynos4210RTCState *)opaque;
388
389 switch (offset) {
390 case INTP:
391 if (value & INTP_ALM_ENABLE) {
392 qemu_irq_lower(s->alm_irq);
393 s->reg_intp &= (~INTP_ALM_ENABLE);
394 }
395 if (value & INTP_TICK_ENABLE) {
396 qemu_irq_lower(s->tick_irq);
397 s->reg_intp &= (~INTP_TICK_ENABLE);
398 }
399 break;
400 case RTCCON:
401 if (value & RTC_ENABLE) {
402 exynos4210_rtc_update_freq(s, value);
403 }
404 if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) {
405
406 ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ);
407 ptimer_run(s->ptimer_1Hz, 1);
408 DPRINTF("run clock timer\n");
409 }
410 if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) {
411
412 ptimer_stop(s->ptimer);
413
414 ptimer_stop(s->ptimer_1Hz);
415 DPRINTF("stop all timers\n");
416 }
417 if (value & RTC_ENABLE) {
418 if ((value & TICK_TIMER_ENABLE) >
419 (s->reg_rtccon & TICK_TIMER_ENABLE) &&
420 (s->reg_ticcnt)) {
421 ptimer_set_count(s->ptimer, s->reg_ticcnt);
422 ptimer_run(s->ptimer, 1);
423 DPRINTF("run tick timer\n");
424 }
425 if ((value & TICK_TIMER_ENABLE) <
426 (s->reg_rtccon & TICK_TIMER_ENABLE)) {
427 ptimer_stop(s->ptimer);
428 }
429 }
430 s->reg_rtccon = value;
431 break;
432 case TICCNT:
433 if (value > TICNT_THRESHOLD) {
434 s->reg_ticcnt = value;
435 } else {
436 fprintf(stderr,
437 "[exynos4210.rtc: bad TICNT value %u ]\n",
438 (uint32_t)value);
439 }
440 break;
441
442 case RTCALM:
443 s->reg_rtcalm = value;
444 break;
445 case ALMSEC:
446 s->reg_almsec = (value & 0x7f);
447 break;
448 case ALMMIN:
449 s->reg_almmin = (value & 0x7f);
450 break;
451 case ALMHOUR:
452 s->reg_almhour = (value & 0x3f);
453 break;
454 case ALMDAY:
455 s->reg_almday = (value & 0x3f);
456 break;
457 case ALMMON:
458 s->reg_almmon = (value & 0x1f);
459 break;
460 case ALMYEAR:
461 s->reg_almyear = (value & 0x0fff);
462 break;
463
464 case BCDSEC:
465 if (s->reg_rtccon & RTC_ENABLE) {
466 s->current_tm.tm_sec = (int)from_bcd((uint8_t)value);
467 }
468 break;
469 case BCDMIN:
470 if (s->reg_rtccon & RTC_ENABLE) {
471 s->current_tm.tm_min = (int)from_bcd((uint8_t)value);
472 }
473 break;
474 case BCDHOUR:
475 if (s->reg_rtccon & RTC_ENABLE) {
476 s->current_tm.tm_hour = (int)from_bcd((uint8_t)value);
477 }
478 break;
479 case BCDDAYWEEK:
480 if (s->reg_rtccon & RTC_ENABLE) {
481 s->current_tm.tm_wday = (int)from_bcd((uint8_t)value);
482 }
483 break;
484 case BCDDAY:
485 if (s->reg_rtccon & RTC_ENABLE) {
486 s->current_tm.tm_mday = (int)from_bcd((uint8_t)value);
487 }
488 break;
489 case BCDMON:
490 if (s->reg_rtccon & RTC_ENABLE) {
491 s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1;
492 }
493 break;
494 case BCDYEAR:
495 if (s->reg_rtccon & RTC_ENABLE) {
496
497 s->current_tm.tm_year = (int)from_bcd((uint8_t)value) +
498 (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100;
499 }
500 break;
501
502 default:
503 fprintf(stderr,
504 "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n",
505 offset);
506 break;
507
508 }
509}
510
511
512
513
514static void exynos4210_rtc_reset(DeviceState *d)
515{
516 Exynos4210RTCState *s = EXYNOS4210_RTC(d);
517
518 qemu_get_timedate(&s->current_tm, 0);
519
520 DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n",
521 s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday,
522 s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec);
523
524 s->reg_intp = 0;
525 s->reg_rtccon = 0;
526 s->reg_ticcnt = 0;
527 s->reg_rtcalm = 0;
528 s->reg_almsec = 0;
529 s->reg_almmin = 0;
530 s->reg_almhour = 0;
531 s->reg_almday = 0;
532 s->reg_almmon = 0;
533 s->reg_almyear = 0;
534
535 s->reg_curticcnt = 0;
536
537 exynos4210_rtc_update_freq(s, s->reg_rtccon);
538 ptimer_stop(s->ptimer);
539 ptimer_stop(s->ptimer_1Hz);
540}
541
542static const MemoryRegionOps exynos4210_rtc_ops = {
543 .read = exynos4210_rtc_read,
544 .write = exynos4210_rtc_write,
545 .endianness = DEVICE_NATIVE_ENDIAN,
546};
547
548
549
550
551static void exynos4210_rtc_init(Object *obj)
552{
553 Exynos4210RTCState *s = EXYNOS4210_RTC(obj);
554 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
555 QEMUBH *bh;
556
557 bh = qemu_bh_new(exynos4210_rtc_tick, s);
558 s->ptimer = ptimer_init(bh);
559 ptimer_set_freq(s->ptimer, RTC_BASE_FREQ);
560 exynos4210_rtc_update_freq(s, 0);
561
562 bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s);
563 s->ptimer_1Hz = ptimer_init(bh);
564 ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ);
565
566 sysbus_init_irq(dev, &s->alm_irq);
567 sysbus_init_irq(dev, &s->tick_irq);
568
569 memory_region_init_io(&s->iomem, obj, &exynos4210_rtc_ops, s,
570 "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE);
571 sysbus_init_mmio(dev, &s->iomem);
572}
573
574static void exynos4210_rtc_class_init(ObjectClass *klass, void *data)
575{
576 DeviceClass *dc = DEVICE_CLASS(klass);
577
578 dc->reset = exynos4210_rtc_reset;
579 dc->vmsd = &vmstate_exynos4210_rtc_state;
580}
581
582static const TypeInfo exynos4210_rtc_info = {
583 .name = TYPE_EXYNOS4210_RTC,
584 .parent = TYPE_SYS_BUS_DEVICE,
585 .instance_size = sizeof(Exynos4210RTCState),
586 .instance_init = exynos4210_rtc_init,
587 .class_init = exynos4210_rtc_class_init,
588};
589
590static void exynos4210_rtc_register_types(void)
591{
592 type_register_static(&exynos4210_rtc_info);
593}
594
595type_init(exynos4210_rtc_register_types)
596
