LXR qemu/hw/timer/puv3

   1/*
   2 * OSTimer device simulation in PKUnity SoC
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "qemu/osdep.h"
  12#include "hw/sysbus.h"
  13#include "hw/ptimer.h"
  14#include "qemu/main-loop.h"
  15
  16#undef DEBUG_PUV3
  17#include "hw/unicore32/puv3.h"
  18
  19#define TYPE_PUV3_OST "puv3_ost"
  20#define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
  21
  22/* puv3 ostimer implementation. */
  23typedef struct PUV3OSTState {
  24    SysBusDevice parent_obj;
  25
  26    MemoryRegion iomem;
  27    QEMUBH *bh;
  28    qemu_irq irq;
  29    ptimer_state *ptimer;
  30
  31    uint32_t reg_OSMR0;
  32    uint32_t reg_OSCR;
  33    uint32_t reg_OSSR;
  34    uint32_t reg_OIER;
  35} PUV3OSTState;
  36
  37static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  38        unsigned size)
  39{
  40    PUV3OSTState *s = opaque;
  41    uint32_t ret = 0;
  42
  43    switch (offset) {
  44    case 0x10: /* Counter Register */
  45        ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  46        break;
  47    case 0x14: /* Status Register */
  48        ret = s->reg_OSSR;
  49        break;
  50    case 0x1c: /* Interrupt Enable Register */
  51        ret = s->reg_OIER;
  52        break;
  53    default:
  54        DPRINTF("Bad offset %x\n", (int)offset);
  55    }
  56    DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  57    return ret;
  58}
  59
  60static void puv3_ost_write(void *opaque, hwaddr offset,
  61        uint64_t value, unsigned size)
  62{
  63    PUV3OSTState *s = opaque;
  64
  65    DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  66    switch (offset) {
  67    case 0x00: /* Match Register 0 */
  68        s->reg_OSMR0 = value;
  69        if (s->reg_OSMR0 > s->reg_OSCR) {
  70            ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  71        } else {
  72            ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  73                    (0xffffffff - s->reg_OSCR));
  74        }
  75        ptimer_run(s->ptimer, 2);
  76        break;
  77    case 0x14: /* Status Register */
  78        assert(value == 0);
  79        if (s->reg_OSSR) {
  80            s->reg_OSSR = value;
  81            qemu_irq_lower(s->irq);
  82        }
  83        break;
  84    case 0x1c: /* Interrupt Enable Register */
  85        s->reg_OIER = value;
  86        break;
  87    default:
  88        DPRINTF("Bad offset %x\n", (int)offset);
  89    }
  90}
  91
  92static const MemoryRegionOps puv3_ost_ops = {
  93    .read = puv3_ost_read,
  94    .write = puv3_ost_write,
  95    .impl = {
  96        .min_access_size = 4,
  97        .max_access_size = 4,
  98    },
  99    .endianness = DEVICE_NATIVE_ENDIAN,
 100};
 101
 102static void puv3_ost_tick(void *opaque)
 103{
 104    PUV3OSTState *s = opaque;
 105
 106    DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 107            s->reg_OSCR, s->reg_OSMR0);
 108
 109    s->reg_OSCR = s->reg_OSMR0;
 110    if (s->reg_OIER) {
 111        s->reg_OSSR = 1;
 112        qemu_irq_raise(s->irq);
 113    }
 114}
 115
 116static int puv3_ost_init(SysBusDevice *dev)
 117{
 118    PUV3OSTState *s = PUV3_OST(dev);
 119
 120    s->reg_OIER = 0;
 121    s->reg_OSSR = 0;
 122    s->reg_OSMR0 = 0;
 123    s->reg_OSCR = 0;
 124
 125    sysbus_init_irq(dev, &s->irq);
 126
 127    s->bh = qemu_bh_new(puv3_ost_tick, s);
 128    s->ptimer = ptimer_init(s->bh);
 129    ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 130
 131    memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 132            PUV3_REGS_OFFSET);
 133    sysbus_init_mmio(dev, &s->iomem);
 134
 135    return 0;
 136}
 137
 138static void puv3_ost_class_init(ObjectClass *klass, void *data)
 139{
 140    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 141
 142    sdc->init = puv3_ost_init;
 143}
 144
 145static const TypeInfo puv3_ost_info = {
 146    .name = TYPE_PUV3_OST,
 147    .parent = TYPE_SYS_BUS_DEVICE,
 148    .instance_size = sizeof(PUV3OSTState),
 149    .class_init = puv3_ost_class_init,
 150};
 151
 152static void puv3_ost_register_type(void)
 153{
 154    type_register_static(&puv3_ost_info);
 155}
 156
 157type_init(puv3_ost_register_type)
 158