1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#include "qemu/osdep.h"
29#include "hw/hw.h"
30#include "qemu/log.h"
31#include "qemu/timer.h"
32
33void xtensa_advance_ccount(CPUXtensaState *env, uint32_t d)
34{
35 uint32_t old_ccount = env->sregs[CCOUNT] + 1;
36
37 env->sregs[CCOUNT] += d;
38
39 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
40 int i;
41 for (i = 0; i < env->config->nccompare; ++i) {
42 if (env->sregs[CCOMPARE + i] - old_ccount < d) {
43 xtensa_timer_irq(env, i, 1);
44 }
45 }
46 }
47}
48
49void check_interrupts(CPUXtensaState *env)
50{
51 CPUState *cs = CPU(xtensa_env_get_cpu(env));
52 int minlevel = xtensa_get_cintlevel(env);
53 uint32_t int_set_enabled = env->sregs[INTSET] & env->sregs[INTENABLE];
54 int level;
55
56
57
58
59 if (cs->halted) {
60 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
61
62 xtensa_advance_ccount(env,
63 muldiv64(now - env->halt_clock,
64 env->config->clock_freq_khz, 1000000));
65 env->halt_clock = now;
66 }
67 for (level = env->config->nlevel; level > minlevel; --level) {
68 if (env->config->level_mask[level] & int_set_enabled) {
69 env->pending_irq_level = level;
70 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
71 qemu_log_mask(CPU_LOG_INT,
72 "%s level = %d, cintlevel = %d, "
73 "pc = %08x, a0 = %08x, ps = %08x, "
74 "intset = %08x, intenable = %08x, "
75 "ccount = %08x\n",
76 __func__, level, xtensa_get_cintlevel(env),
77 env->pc, env->regs[0], env->sregs[PS],
78 env->sregs[INTSET], env->sregs[INTENABLE],
79 env->sregs[CCOUNT]);
80 return;
81 }
82 }
83 env->pending_irq_level = 0;
84 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
85}
86
87static void xtensa_set_irq(void *opaque, int irq, int active)
88{
89 CPUXtensaState *env = opaque;
90
91 if (irq >= env->config->ninterrupt) {
92 qemu_log("%s: bad IRQ %d\n", __func__, irq);
93 } else {
94 uint32_t irq_bit = 1 << irq;
95
96 if (active) {
97 env->sregs[INTSET] |= irq_bit;
98 } else if (env->config->interrupt[irq].inttype == INTTYPE_LEVEL) {
99 env->sregs[INTSET] &= ~irq_bit;
100 }
101
102 check_interrupts(env);
103 }
104}
105
106void xtensa_timer_irq(CPUXtensaState *env, uint32_t id, uint32_t active)
107{
108 qemu_set_irq(env->irq_inputs[env->config->timerint[id]], active);
109}
110
111void xtensa_rearm_ccompare_timer(CPUXtensaState *env)
112{
113 int i;
114 uint32_t wake_ccount = env->sregs[CCOUNT] - 1;
115
116 for (i = 0; i < env->config->nccompare; ++i) {
117 if (env->sregs[CCOMPARE + i] - env->sregs[CCOUNT] <
118 wake_ccount - env->sregs[CCOUNT]) {
119 wake_ccount = env->sregs[CCOMPARE + i];
120 }
121 }
122 env->wake_ccount = wake_ccount;
123 timer_mod(env->ccompare_timer, env->halt_clock +
124 muldiv64(wake_ccount - env->sregs[CCOUNT],
125 1000000, env->config->clock_freq_khz));
126}
127
128static void xtensa_ccompare_cb(void *opaque)
129{
130 XtensaCPU *cpu = opaque;
131 CPUXtensaState *env = &cpu->env;
132 CPUState *cs = CPU(cpu);
133
134 if (cs->halted) {
135 env->halt_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
136 xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]);
137 if (!cpu_has_work(cs)) {
138 env->sregs[CCOUNT] = env->wake_ccount + 1;
139 xtensa_rearm_ccompare_timer(env);
140 }
141 }
142}
143
144void xtensa_irq_init(CPUXtensaState *env)
145{
146 XtensaCPU *cpu = xtensa_env_get_cpu(env);
147
148 env->irq_inputs = (void **)qemu_allocate_irqs(
149 xtensa_set_irq, env, env->config->ninterrupt);
150 if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) &&
151 env->config->nccompare > 0) {
152 env->ccompare_timer =
153 timer_new_ns(QEMU_CLOCK_VIRTUAL, &xtensa_ccompare_cb, cpu);
154 }
155}
156
157void *xtensa_get_extint(CPUXtensaState *env, unsigned extint)
158{
159 if (extint < env->config->nextint) {
160 unsigned irq = env->config->extint[extint];
161 return env->irq_inputs[irq];
162 } else {
163 qemu_log("%s: trying to acquire invalid external interrupt %d\n",
164 __func__, extint);
165 return NULL;
166 }
167}
168