1/* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19#ifndef CPU_DEFS_H 20#define CPU_DEFS_H 21 22#ifndef NEED_CPU_H 23#error cpu.h included from common code 24#endif 25 26#include "qemu/queue.h" 27#include "tcg-target.h" 28#ifndef CONFIG_USER_ONLY 29#include "exec/hwaddr.h" 30#endif 31#include "exec/memattrs.h" 32 33#ifndef TARGET_LONG_BITS 34#error TARGET_LONG_BITS must be defined before including this header 35#endif 36 37#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 38 39/* target_ulong is the type of a virtual address */ 40#if TARGET_LONG_SIZE == 4 41typedef int32_t target_long; 42typedef uint32_t target_ulong; 43#define TARGET_FMT_lx "%08x" 44#define TARGET_FMT_ld "%d" 45#define TARGET_FMT_lu "%u" 46#elif TARGET_LONG_SIZE == 8 47typedef int64_t target_long; 48typedef uint64_t target_ulong; 49#define TARGET_FMT_lx "%016" PRIx64 50#define TARGET_FMT_ld "%" PRId64 51#define TARGET_FMT_lu "%" PRIu64 52#else 53#error TARGET_LONG_SIZE undefined 54#endif 55 56#if !defined(CONFIG_USER_ONLY) 57/* use a fully associative victim tlb of 8 entries */ 58#define CPU_VTLB_SIZE 8 59 60#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 61#define CPU_TLB_ENTRY_BITS 4 62#else 63#define CPU_TLB_ENTRY_BITS 5 64#endif 65 66/* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that 67 * the TLB is not unnecessarily small, but still small enough for the 68 * TLB lookup instruction sequence used by the TCG target. 69 * 70 * TCG will have to generate an operand as large as the distance between 71 * env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity, 72 * the TCG targets just round everything up to the next power of two, and 73 * count bits. This works because: 1) the size of each TLB is a largish 74 * power of two, 2) and because the limit of the displacement is really close 75 * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller 76 * than the size of a TLB. 77 * 78 * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG 79 * just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS 80 * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily 81 * small": 2^15). The operand then will come up smaller than 0xFFF0 without 82 * any particular care, because the TLB for a single MMU mode is larger than 83 * 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand 84 * could be something like 0xC000 (the offset of the last TLB table) plus 85 * 0x18 (the offset of the addend field in each TLB entry) plus the offset 86 * of tlb_table inside env (which is non-trivial but not huge). 87 */ 88#define CPU_TLB_BITS \ 89 MIN(8, \ 90 TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ 91 (NB_MMU_MODES <= 1 ? 0 : \ 92 NB_MMU_MODES <= 2 ? 1 : \ 93 NB_MMU_MODES <= 4 ? 2 : \ 94 NB_MMU_MODES <= 8 ? 3 : 4)) 95 96#define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 97 98typedef struct CPUTLBEntry { 99 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 100 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 101 go directly to ram. 102 bit 3 : indicates that the entry is invalid 103 bit 2..0 : zero 104 */ 105 union { 106 struct { 107 target_ulong addr_read; 108 target_ulong addr_write; 109 target_ulong addr_code; 110 /* Addend to virtual address to get host address. IO accesses 111 use the corresponding iotlb value. */ 112 uintptr_t addend; 113 }; 114 /* padding to get a power of two size */ 115 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 116 }; 117} CPUTLBEntry; 118 119QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 120 121/* The IOTLB is not accessed directly inline by generated TCG code, 122 * so the CPUIOTLBEntry layout is not as critical as that of the 123 * CPUTLBEntry. (This is also why we don't want to combine the two 124 * structs into one.) 125 */ 126typedef struct CPUIOTLBEntry { 127 hwaddr addr; 128 MemTxAttrs attrs; 129} CPUIOTLBEntry; 130 131#ifndef NB_MEM_ATTR 132#define NB_MEM_ATTR 2 133#endif 134 135#define CPU_COMMON_TLB \ 136 /* The meaning of the MMU modes is defined in the target code. */ \ 137 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 138 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 139 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 140 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 141 CPUIOTLBEntry memattr[NB_MEM_ATTR]; \ 142 target_ulong tlb_flush_addr; \ 143 target_ulong tlb_flush_mask; \ 144 target_ulong vtlb_index; \ 145 146#else 147 148#define CPU_COMMON_TLB 149 150#endif 151 152 153#define CPU_COMMON \ 154 /* soft mmu support */ \ 155 CPU_COMMON_TLB \ 156 157#endif 158