LXR qemu/include/hw/arm/exynos4210.h

   1/*
   2 *  Samsung exynos4210 SoC emulation
   3 *
   4 *  Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
   5 *    Maksim Kozlov <m.kozlov@samsung.com>
   6 *    Evgeny Voevodin <e.voevodin@samsung.com>
   7 *    Igor Mitsyanko <i.mitsyanko@samsung.com>
   8 *
   9 *
  10 *  This program is free software; you can redistribute it and/or modify it
  11 *  under the terms of the GNU General Public License as published by the
  12 *  Free Software Foundation; either version 2 of the License, or
  13 *  (at your option) any later version.
  14 *
  15 *  This program is distributed in the hope that it will be useful, but WITHOUT
  16 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18 *  for more details.
  19 *
  20 *  You should have received a copy of the GNU General Public License along
  21 *  with this program; if not, see <http://www.gnu.org/licenses/>.
  22 *
  23 */
  24
  25
  26#ifndef EXYNOS4210_H_
  27#define EXYNOS4210_H_
  28
  29#include "qemu-common.h"
  30#include "exec/memory.h"
  31#include "target-arm/cpu-qom.h"
  32
  33#define EXYNOS4210_NCPUS                    2
  34
  35#define EXYNOS4210_DRAM0_BASE_ADDR          0x40000000
  36#define EXYNOS4210_DRAM1_BASE_ADDR          0xa0000000
  37#define EXYNOS4210_DRAM_MAX_SIZE            0x60000000  /* 1.5 GB */
  38
  39#define EXYNOS4210_IROM_BASE_ADDR           0x00000000
  40#define EXYNOS4210_IROM_SIZE                0x00010000  /* 64 KB */
  41#define EXYNOS4210_IROM_MIRROR_BASE_ADDR    0x02000000
  42#define EXYNOS4210_IROM_MIRROR_SIZE         0x00010000  /* 64 KB */
  43
  44#define EXYNOS4210_IRAM_BASE_ADDR           0x02020000
  45#define EXYNOS4210_IRAM_SIZE                0x00020000  /* 128 KB */
  46
  47/* Secondary CPU startup code is in IROM memory */
  48#define EXYNOS4210_SMP_BOOT_ADDR            EXYNOS4210_IROM_BASE_ADDR
  49#define EXYNOS4210_SMP_BOOT_SIZE            0x1000
  50#define EXYNOS4210_BASE_BOOT_ADDR           EXYNOS4210_DRAM0_BASE_ADDR
  51/* Secondary CPU polling address to get loader start from */
  52#define EXYNOS4210_SECOND_CPU_BOOTREG       0x10020814
  53
  54#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR    0x10500000
  55#define EXYNOS4210_L2X0_BASE_ADDR           0x10502000
  56
  57/*
  58 * exynos4210 IRQ subsystem stub definitions.
  59 */
  60#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
  61
  62#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ  64
  63#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ  16
  64#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ   \
  65    (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
  66#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ   \
  67    (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
  68
  69#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit)  ((grp)*8 + (bit))
  70#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq)       ((irq) / 8)
  71#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \
  72    ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq))
  73
  74/* IRQs number for external and internal GIC */
  75#define EXYNOS4210_EXT_GIC_NIRQ     (160-32)
  76#define EXYNOS4210_INT_GIC_NIRQ     64
  77
  78#define EXYNOS4210_I2C_NUMBER               9
  79
  80typedef struct Exynos4210Irq {
  81    qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
  82    qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ];
  83    qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ];
  84    qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ];
  85    qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
  86} Exynos4210Irq;
  87
  88typedef struct Exynos4210State {
  89    ARMCPU *cpu[EXYNOS4210_NCPUS];
  90    Exynos4210Irq irqs;
  91    qemu_irq *irq_table;
  92
  93    MemoryRegion chipid_mem;
  94    MemoryRegion iram_mem;
  95    MemoryRegion irom_mem;
  96    MemoryRegion irom_alias_mem;
  97    MemoryRegion dram0_mem;
  98    MemoryRegion dram1_mem;
  99    MemoryRegion boot_secondary;
 100    MemoryRegion bootreg_mem;
 101    I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 102} Exynos4210State;
 103
 104void exynos4210_write_secondary(ARMCPU *cpu,
 105        const struct arm_boot_info *info);
 106
 107Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
 108        unsigned long ram_size);
 109
 110/* Initialize exynos4210 IRQ subsystem stub */
 111qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 112
 113/* Initialize board IRQs.
 114 * These IRQs contain splitted Int/External Combiner and External Gic IRQs */
 115void exynos4210_init_board_irqs(Exynos4210Irq *s);
 116
 117/* Get IRQ number from exynos4210 IRQ subsystem stub.
 118 * To identify IRQ source use internal combiner group and bit number
 119 *  grp - group number
 120 *  bit - bit number inside group */
 121uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
 122
 123/*
 124 * Get Combiner input GPIO into irqs structure
 125 */
 126void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev,
 127        int ext);
 128
 129/*
 130 * exynos4210 UART
 131 */
 132DeviceState *exynos4210_uart_create(hwaddr addr,
 133                                    int fifo_size,
 134                                    int channel,
 135                                    CharDriverState *chr,
 136                                    qemu_irq irq);
 137
 138#endif /* EXYNOS4210_H_ */
 139