1/* 2 * ARM GIC support 3 * 4 * Copyright (c) 2012 Linaro Limited 5 * Written by Peter Maydell 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation, either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License along 18 * with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21#ifndef HW_ARM_GIC_COMMON_H 22#define HW_ARM_GIC_COMMON_H 23 24#include "hw/sysbus.h" 25 26/* Maximum number of possible interrupts, determined by the GIC architecture */ 27#define GIC_MAXIRQ 1020 28/* First 32 are private to each CPU (SGIs and PPIs). */ 29#define GIC_INTERNAL 32 30#define GIC_NR_SGIS 16 31/* Maximum number of possible CPU interfaces, determined by GIC architecture */ 32/* Include a vCPU interface per CPU. */ 33#define GIC_N_REALCPU 8 34#define GIC_NCPU (GIC_N_REALCPU * 2) 35 36#define MAX_NR_GROUP_PRIO 128 37#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) 38#define GICV_NR_LR 8 39 40typedef struct gic_irq_state { 41 /* The enable bits are only banked for per-cpu interrupts. */ 42 uint8_t enabled; 43 uint8_t pending; 44 uint8_t active; 45 uint8_t level; 46 bool model; /* 0 = N:N, 1 = 1:N */ 47 bool edge_trigger; /* true: edge-triggered, false: level-triggered */ 48 bool group; 49} gic_irq_state; 50 51typedef struct GICState { 52 /*< private >*/ 53 SysBusDevice parent_obj; 54 /*< public >*/ 55 56 qemu_irq parent_irq[GIC_NCPU]; 57 qemu_irq parent_fiq[GIC_NCPU]; 58 qemu_irq maint[GIC_N_REALCPU]; 59 60 bool enabled; 61 bool enabled_grp0; 62 63 struct { 64 bool enable_grp[2]; 65 bool ack_ctl; 66 bool fiq_en; 67 bool eoirmode; 68 bool eoirmode_ns; 69 } gicc_ctrl[GIC_NCPU]; 70 uint32_t ctrl[GIC_NCPU]; 71 72 gic_irq_state irq_state[GIC_MAXIRQ]; 73 uint8_t irq_target[GIC_MAXIRQ]; 74 uint8_t priority1[GIC_INTERNAL][GIC_NCPU]; 75 uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL]; 76 bool eoir[GIC_NCPU][GIC_MAXIRQ]; 77 uint16_t last_active[GIC_MAXIRQ][GIC_NCPU]; 78 /* For each SGI on the target CPU, we store 8 bits 79 * indicating which source CPUs have made this SGI 80 * pending on the target CPU. These correspond to 81 * the bytes in the GIC_SPENDSGIR* registers as 82 * read by the target CPU. 83 */ 84 uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU]; 85 86 uint16_t priority_mask[GIC_NCPU]; 87 uint16_t running_irq[GIC_NCPU]; 88 uint16_t running_priority[GIC_NCPU]; 89 uint16_t current_pending[GIC_NCPU]; 90 91 /* We present the GICv2 without security extensions to a guest and 92 * therefore the guest can configure the GICC_CTLR to configure group 1 93 * binary point in the abpr. 94 */ 95 uint8_t bpr[GIC_NCPU]; 96 uint8_t abpr[GIC_NCPU]; 97 98 /* The Interface Identification Register. 99 * This is implementation defined 100 */ 101 uint32_t c_iidr; 102 103 /* The APR is implementation defined, so we choose a layout identical to 104 * the KVM ABI layout for QEMU's implementation of the gic: 105 * If an interrupt for preemption level X is active, then 106 * APRn[X mod 32] == 0b1, where n = X / 32 107 * otherwise the bit is clear. 108 * 109 * TODO: rewrite the interrupt acknowlege/complete routines to use 110 * the APR registers to track the necessary information to update 111 * s->running_priority[] on interrupt completion (ie completely remove 112 * last_active[][] and running_irq[]). This will be necessary if we ever 113 * want to support TCG<->KVM migration, or TCG guests which can 114 * do power management involving powering down and restarting 115 * the GIC. 116 */ 117 uint32_t apr[GIC_NR_APRS][GIC_NCPU]; 118 119 struct { 120 uint32_t hcr[GIC_N_REALCPU]; 121 uint32_t vtr[GIC_N_REALCPU]; 122 uint32_t misr[GIC_N_REALCPU]; 123 uint64_t eisr[GIC_N_REALCPU]; 124 uint64_t elrsr[GIC_N_REALCPU]; 125 uint32_t apr[GIC_N_REALCPU]; 126 uint32_t lr[GIC_N_REALCPU][GICV_NR_LR]; 127 128 uint32_t pending_prio[GIC_N_REALCPU]; 129 uint8_t pending_lrn[GIC_N_REALCPU]; 130 } gich; 131 132 uint32_t num_cpu; 133 134 MemoryRegion iomem; /* Distributor */ 135 /* This is just so we can have an opaque pointer which identifies 136 * both this GIC and which CPU interface we should be accessing. 137 */ 138 struct GICState *backref[GIC_NCPU]; 139 MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */ 140 MemoryRegion hypiomem[GIC_NCPU + 1]; /* Virtual control interfaces */ 141 MemoryRegion vcpuiomem; /* Virtual CPU interface */ 142 uint32_t map_stride; 143 uint32_t num_irq; 144 uint32_t revision; 145 bool disable_linux_gic_init; 146 int dev_fd; /* kvm device fd if backed by kvm vgic support */ 147} GICState; 148 149#define TYPE_ARM_GIC_COMMON "arm_gic_common" 150#define ARM_GIC_COMMON(obj) \ 151 OBJECT_CHECK(GICState, (obj), TYPE_ARM_GIC_COMMON) 152#define ARM_GIC_COMMON_CLASS(klass) \ 153 OBJECT_CLASS_CHECK(ARMGICCommonClass, (klass), TYPE_ARM_GIC_COMMON) 154#define ARM_GIC_COMMON_GET_CLASS(obj) \ 155 OBJECT_GET_CLASS(ARMGICCommonClass, (obj), TYPE_ARM_GIC_COMMON) 156 157typedef struct ARMGICCommonClass { 158 /*< private >*/ 159 SysBusDeviceClass parent_class; 160 /*< public >*/ 161 162 void (*pre_save)(GICState *s); 163 void (*post_load)(GICState *s); 164} ARMGICCommonClass; 165 166#endif 167