1/* 2 * i.MX31 Vectored Interrupt Controller 3 * 4 * Note this is NOT the PL192 provided by ARM, but 5 * a custom implementation by Freescale. 6 * 7 * Copyright (c) 2008 OKL 8 * Copyright (c) 2011 NICTA Pty Ltd 9 * Originally written by Hans Jiang 10 * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> 11 * 12 * This code is licensed under the GPL version 2 or later. See 13 * the COPYING file in the top-level directory. 14 * 15 * TODO: implement vectors. 16 */ 17#ifndef IMX_AVIC_H 18#define IMX_AVIC_H 19 20#include "hw/sysbus.h" 21 22#define TYPE_IMX_AVIC "imx.avic" 23#define IMX_AVIC(obj) OBJECT_CHECK(IMXAVICState, (obj), TYPE_IMX_AVIC) 24 25#define IMX_AVIC_NUM_IRQS 64 26 27/* Interrupt Control Bits */ 28#define ABFLAG (1<<25) 29#define ABFEN (1<<24) 30#define NIDIS (1<<22) /* Normal Interrupt disable */ 31#define FIDIS (1<<21) /* Fast interrupt disable */ 32#define NIAD (1<<20) /* Normal Interrupt Arbiter Rise ARM level */ 33#define FIAD (1<<19) /* Fast Interrupt Arbiter Rise ARM level */ 34#define NM (1<<18) /* Normal interrupt mode */ 35 36#define PRIO_PER_WORD (sizeof(uint32_t) * 8 / 4) 37#define PRIO_WORDS (IMX_AVIC_NUM_IRQS/PRIO_PER_WORD) 38 39typedef struct IMXAVICState{ 40 /*< private >*/ 41 SysBusDevice parent_obj; 42 43 /*< public >*/ 44 MemoryRegion iomem; 45 uint64_t pending; 46 uint64_t enabled; 47 uint64_t is_fiq; 48 uint32_t intcntl; 49 uint32_t intmask; 50 qemu_irq irq; 51 qemu_irq fiq; 52 uint32_t prio[PRIO_WORDS]; /* Priorities are 4-bits each */ 53} IMXAVICState; 54 55#endif /* IMX_AVIC_H */ 56