LXR qemu/include/hw/net/imx

   1/*
   2 * i.MX Fast Ethernet Controller emulation.
   3 *
   4 * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
   5 *
   6 * Based on Coldfire Fast Ethernet Controller emulation.
   7 *
   8 * Copyright (c) 2007 CodeSourcery.
   9 *
  10 *  This program is free software; you can redistribute it and/or modify it
  11 *  under the terms of the GNU General Public License as published by the
  12 *  Free Software Foundation; either version 2 of the License, or
  13 *  (at your option) any later version.
  14 *
  15 *  This program is distributed in the hope that it will be useful, but WITHOUT
  16 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17 *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  18 *  for more details.
  19 *
  20 *  You should have received a copy of the GNU General Public License along
  21 *  with this program; if not, see <http://www.gnu.org/licenses/>.
  22 */
  23
  24#ifndef IMX_FEC_H
  25#define IMX_FEC_H
  26
  27#define TYPE_IMX_FEC "imx.fec"
  28#define IMX_FEC(obj) OBJECT_CHECK(IMXFECState, (obj), TYPE_IMX_FEC)
  29
  30#include "hw/sysbus.h"
  31#include "net/net.h"
  32
  33#define FEC_MAX_FRAME_SIZE 2032
  34
  35#define FEC_INT_HB      (1 << 31)
  36#define FEC_INT_BABR    (1 << 30)
  37#define FEC_INT_BABT    (1 << 29)
  38#define FEC_INT_GRA     (1 << 28)
  39#define FEC_INT_TXF     (1 << 27)
  40#define FEC_INT_TXB     (1 << 26)
  41#define FEC_INT_RXF     (1 << 25)
  42#define FEC_INT_RXB     (1 << 24)
  43#define FEC_INT_MII     (1 << 23)
  44#define FEC_INT_EBERR   (1 << 22)
  45#define FEC_INT_LC      (1 << 21)
  46#define FEC_INT_RL      (1 << 20)
  47#define FEC_INT_UN      (1 << 19)
  48
  49#define FEC_EN      2
  50#define FEC_RESET   1
  51
  52/* Buffer Descriptor.  */
  53typedef struct {
  54    uint16_t length;
  55    uint16_t flags;
  56    uint32_t data;
  57} IMXFECBufDesc;
  58
  59#define FEC_BD_R    (1 << 15)
  60#define FEC_BD_E    (1 << 15)
  61#define FEC_BD_O1   (1 << 14)
  62#define FEC_BD_W    (1 << 13)
  63#define FEC_BD_O2   (1 << 12)
  64#define FEC_BD_L    (1 << 11)
  65#define FEC_BD_TC   (1 << 10)
  66#define FEC_BD_ABC  (1 << 9)
  67#define FEC_BD_M    (1 << 8)
  68#define FEC_BD_BC   (1 << 7)
  69#define FEC_BD_MC   (1 << 6)
  70#define FEC_BD_LG   (1 << 5)
  71#define FEC_BD_NO   (1 << 4)
  72#define FEC_BD_CR   (1 << 2)
  73#define FEC_BD_OV   (1 << 1)
  74#define FEC_BD_TR   (1 << 0)
  75
  76typedef struct IMXFECState {
  77    /*< private >*/
  78    SysBusDevice parent_obj;
  79
  80    /*< public >*/
  81    NICState *nic;
  82    NICConf conf;
  83    qemu_irq irq;
  84    MemoryRegion iomem;
  85
  86    uint32_t irq_state;
  87    uint32_t eir;
  88    uint32_t eimr;
  89    uint32_t rx_enabled;
  90    uint32_t rx_descriptor;
  91    uint32_t tx_descriptor;
  92    uint32_t ecr;
  93    uint32_t mmfr;
  94    uint32_t mscr;
  95    uint32_t mibc;
  96    uint32_t rcr;
  97    uint32_t tcr;
  98    uint32_t tfwr;
  99    uint32_t frsr;
 100    uint32_t erdsr;
 101    uint32_t etdsr;
 102    uint32_t emrbr;
 103    uint32_t miigsk_cfgr;
 104    uint32_t miigsk_enr;
 105
 106    uint32_t phy_status;
 107    uint32_t phy_control;
 108    uint32_t phy_advertise;
 109    uint32_t phy_int;
 110    uint32_t phy_int_mask;
 111} IMXFECState;
 112
 113#endif
 114