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26#ifndef QEMU_PCI_BRIDGE_H
27#define QEMU_PCI_BRIDGE_H
28
29#include "hw/pci/pci.h"
30
31#define PCI_BRIDGE_DEV_PROP_CHASSIS_NR "chassis_nr"
32#define PCI_BRIDGE_DEV_PROP_MSI "msi"
33#define PCI_BRIDGE_DEV_PROP_SHPC "shpc"
34
35int pci_bridge_ssvid_init(PCIDevice *dev, uint8_t offset,
36 uint16_t svid, uint16_t ssid);
37
38PCIDevice *pci_bridge_get_device(PCIBus *bus);
39PCIBus *pci_bridge_get_sec_bus(PCIBridge *br);
40
41pcibus_t pci_bridge_get_base(const PCIDevice *bridge, uint8_t type);
42pcibus_t pci_bridge_get_limit(const PCIDevice *bridge, uint8_t type);
43
44void pci_bridge_update_mappings(PCIBridge *br);
45void pci_bridge_write_config(PCIDevice *d,
46 uint32_t address, uint32_t val, int len);
47void pci_bridge_disable_base_limit(PCIDevice *dev);
48void pci_bridge_reset_reg(PCIDevice *dev);
49void pci_bridge_reset(DeviceState *qdev);
50
51void pci_bridge_initfn(PCIDevice *pci_dev, const char *typename);
52void pci_bridge_exitfn(PCIDevice *pci_dev);
53
54
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58
59
60void pci_bridge_map_irq(PCIBridge *br, const char* bus_name,
61 pci_map_irq_fn map_irq);
62
63
64#define PCI_BRIDGE_CTL_VGA_16BIT 0x10
65#define PCI_BRIDGE_CTL_DISCARD 0x100
66#define PCI_BRIDGE_CTL_SEC_DISCARD 0x200
67#define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400
68#define PCI_BRIDGE_CTL_DISCARD_SERR 0x800
69
70#endif
71