LXR qemu/include/hw/ppc/ppc.h

   1#ifndef HW_PPC_H
   2#define HW_PPC_H 1
   3
   4#include "target-ppc/cpu-qom.h"
   5
   6void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
   7
   8/* PowerPC hardware exceptions management helpers */
   9typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
  10typedef struct clk_setup_t clk_setup_t;
  11struct clk_setup_t {
  12    clk_setup_cb cb;
  13    void *opaque;
  14};
  15static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
  16{
  17    if (clk->cb != NULL)
  18        (*clk->cb)(clk->opaque, freq);
  19}
  20
  21struct ppc_tb_t {
  22    /* Time base management */
  23    int64_t  tb_offset;    /* Compensation                    */
  24    int64_t  atb_offset;   /* Compensation                    */
  25    uint32_t tb_freq;      /* TB frequency                    */
  26    /* Decrementer management */
  27    uint64_t decr_next;    /* Tick for next decr interrupt    */
  28    uint32_t decr_freq;    /* decrementer frequency           */
  29    QEMUTimer *decr_timer;
  30    /* Hypervisor decrementer management */
  31    uint64_t hdecr_next;    /* Tick for next hdecr interrupt  */
  32    QEMUTimer *hdecr_timer;
  33    uint64_t purr_load;
  34    uint64_t purr_start;
  35    void *opaque;
  36    uint32_t flags;
  37};
  38
  39/* PPC Timers flags */
  40#define PPC_TIMER_BOOKE              (1 << 0) /* Enable Booke support */
  41#define PPC_TIMER_E500               (1 << 1) /* Enable e500 support */
  42#define PPC_DECR_UNDERFLOW_TRIGGERED (1 << 2) /* Decr interrupt triggered when
  43                                               * the most significant bit
  44                                               * changes from 0 to 1.
  45                                               */
  46#define PPC_DECR_ZERO_TRIGGERED      (1 << 3) /* Decr interrupt triggered when
  47                                               * the decrementer reaches zero.
  48                                               */
  49#define PPC_DECR_UNDERFLOW_LEVEL     (1 << 4) /* Decr interrupt active when
  50                                               * the most significant bit is 1.
  51                                               */
  52
  53uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
  54clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
  55/* Embedded PowerPC DCR management */
  56typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
  57typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
  58int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),
  59                  int (*dcr_write_error)(int dcrn));
  60int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,
  61                      dcr_read_cb drc_read, dcr_write_cb dcr_write);
  62clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,
  63                                  unsigned int decr_excp);
  64
  65/* Embedded PowerPC reset */
  66void ppc40x_core_reset(PowerPCCPU *cpu);
  67void ppc40x_chip_reset(PowerPCCPU *cpu);
  68void ppc40x_system_reset(PowerPCCPU *cpu);
  69void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
  70
  71#if defined(CONFIG_USER_ONLY)
  72static inline void ppc40x_irq_init(PowerPCCPU *cpu) {}
  73static inline void ppc6xx_irq_init(PowerPCCPU *cpu) {}
  74static inline void ppc970_irq_init(PowerPCCPU *cpu) {}
  75static inline void ppcPOWER7_irq_init(PowerPCCPU *cpu) {}
  76static inline void ppce500_irq_init(PowerPCCPU *cpu) {}
  77#else
  78void ppc40x_irq_init(PowerPCCPU *cpu);
  79void ppce500_irq_init(PowerPCCPU *cpu);
  80void ppc6xx_irq_init(PowerPCCPU *cpu);
  81void ppc970_irq_init(PowerPCCPU *cpu);
  82void ppcPOWER7_irq_init(PowerPCCPU *cpu);
  83#endif
  84
  85/* PPC machines for OpenBIOS */
  86enum {
  87    ARCH_PREP = 0,
  88    ARCH_MAC99,
  89    ARCH_HEATHROW,
  90    ARCH_MAC99_U3,
  91};
  92
  93#define FW_CFG_PPC_WIDTH        (FW_CFG_ARCH_LOCAL + 0x00)
  94#define FW_CFG_PPC_HEIGHT       (FW_CFG_ARCH_LOCAL + 0x01)
  95#define FW_CFG_PPC_DEPTH        (FW_CFG_ARCH_LOCAL + 0x02)
  96#define FW_CFG_PPC_TBFREQ       (FW_CFG_ARCH_LOCAL + 0x03)
  97#define FW_CFG_PPC_CLOCKFREQ    (FW_CFG_ARCH_LOCAL + 0x04)
  98#define FW_CFG_PPC_IS_KVM       (FW_CFG_ARCH_LOCAL + 0x05)
  99#define FW_CFG_PPC_KVM_HC       (FW_CFG_ARCH_LOCAL + 0x06)
 100#define FW_CFG_PPC_KVM_PID      (FW_CFG_ARCH_LOCAL + 0x07)
 101#define FW_CFG_PPC_NVRAM_ADDR   (FW_CFG_ARCH_LOCAL + 0x08)
 102#define FW_CFG_PPC_BUSFREQ      (FW_CFG_ARCH_LOCAL + 0x09)
 103
 104#define PPC_SERIAL_MM_BAUDBASE 399193
 105
 106/* ppc_booke.c */
 107void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags);
 108
 109#endif
 110