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19#ifndef __ARM_KVM_H__
20#define __ARM_KVM_H__
21
22#include <linux/types.h>
23#include <linux/psci.h>
24#include <asm/ptrace.h>
25
26#define __KVM_HAVE_GUEST_DEBUG
27#define __KVM_HAVE_IRQ_LINE
28#define __KVM_HAVE_READONLY_MEM
29
30#define KVM_REG_SIZE(id) \
31 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
32
33
34#define KVM_ARM_SVC_sp svc_regs[0]
35#define KVM_ARM_SVC_lr svc_regs[1]
36#define KVM_ARM_SVC_spsr svc_regs[2]
37#define KVM_ARM_ABT_sp abt_regs[0]
38#define KVM_ARM_ABT_lr abt_regs[1]
39#define KVM_ARM_ABT_spsr abt_regs[2]
40#define KVM_ARM_UND_sp und_regs[0]
41#define KVM_ARM_UND_lr und_regs[1]
42#define KVM_ARM_UND_spsr und_regs[2]
43#define KVM_ARM_IRQ_sp irq_regs[0]
44#define KVM_ARM_IRQ_lr irq_regs[1]
45#define KVM_ARM_IRQ_spsr irq_regs[2]
46
47
48#define KVM_ARM_FIQ_r8 fiq_regs[0]
49#define KVM_ARM_FIQ_r9 fiq_regs[1]
50#define KVM_ARM_FIQ_r10 fiq_regs[2]
51#define KVM_ARM_FIQ_fp fiq_regs[3]
52#define KVM_ARM_FIQ_ip fiq_regs[4]
53#define KVM_ARM_FIQ_sp fiq_regs[5]
54#define KVM_ARM_FIQ_lr fiq_regs[6]
55#define KVM_ARM_FIQ_spsr fiq_regs[7]
56
57struct kvm_regs {
58 struct pt_regs usr_regs;
59 unsigned long svc_regs[3];
60 unsigned long abt_regs[3];
61 unsigned long und_regs[3];
62 unsigned long irq_regs[3];
63 unsigned long fiq_regs[8];
64};
65
66
67#define KVM_ARM_TARGET_CORTEX_A15 0
68#define KVM_ARM_TARGET_CORTEX_A7 1
69#define KVM_ARM_NUM_TARGETS 2
70
71
72#define KVM_ARM_DEVICE_TYPE_SHIFT 0
73#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
74#define KVM_ARM_DEVICE_ID_SHIFT 16
75#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
76
77
78#define KVM_ARM_DEVICE_VGIC_V2 0
79
80
81#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
82#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
83
84#define KVM_VGIC_V2_DIST_SIZE 0x1000
85#define KVM_VGIC_V2_CPU_SIZE 0x2000
86
87#define KVM_ARM_VCPU_POWER_OFF 0
88#define KVM_ARM_VCPU_PSCI_0_2 1
89
90struct kvm_vcpu_init {
91 __u32 target;
92 __u32 features[7];
93};
94
95struct kvm_sregs {
96};
97
98struct kvm_fpu {
99};
100
101struct kvm_guest_debug_arch {
102};
103
104struct kvm_debug_exit_arch {
105};
106
107struct kvm_sync_regs {
108};
109
110struct kvm_arch_memory_slot {
111};
112
113
114#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
115#define KVM_REG_ARM_COPROC_SHIFT 16
116#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
117#define KVM_REG_ARM_32_OPC2_SHIFT 0
118#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
119#define KVM_REG_ARM_OPC1_SHIFT 3
120#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
121#define KVM_REG_ARM_CRM_SHIFT 7
122#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
123#define KVM_REG_ARM_32_CRN_SHIFT 11
124
125#define ARM_CP15_REG_SHIFT_MASK(x,n) \
126 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
127
128#define __ARM_CP15_REG(op1,crn,crm,op2) \
129 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
130 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
131 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
132 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
133 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
134
135#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
136
137#define __ARM_CP15_REG64(op1,crm) \
138 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
139#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
140
141#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
142#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
143#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
144
145
146#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
147#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
148
149
150#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
151#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
152#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
153#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
154#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
155#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
156
157
158#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
159#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
160#define KVM_REG_ARM_VFP_BASE_REG 0x0
161#define KVM_REG_ARM_VFP_FPSID 0x1000
162#define KVM_REG_ARM_VFP_FPSCR 0x1001
163#define KVM_REG_ARM_VFP_MVFR1 0x1006
164#define KVM_REG_ARM_VFP_MVFR0 0x1007
165#define KVM_REG_ARM_VFP_FPEXC 0x1008
166#define KVM_REG_ARM_VFP_FPINST 0x1009
167#define KVM_REG_ARM_VFP_FPINST2 0x100A
168
169
170#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
171#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
172#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
173#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
174#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
175#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
176#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
177#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
178#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
179#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
180
181
182#define KVM_ARM_IRQ_TYPE_SHIFT 24
183#define KVM_ARM_IRQ_TYPE_MASK 0xff
184#define KVM_ARM_IRQ_VCPU_SHIFT 16
185#define KVM_ARM_IRQ_VCPU_MASK 0xff
186#define KVM_ARM_IRQ_NUM_SHIFT 0
187#define KVM_ARM_IRQ_NUM_MASK 0xffff
188
189
190#define KVM_ARM_IRQ_TYPE_CPU 0
191#define KVM_ARM_IRQ_TYPE_SPI 1
192#define KVM_ARM_IRQ_TYPE_PPI 2
193
194
195#define KVM_ARM_IRQ_CPU_IRQ 0
196#define KVM_ARM_IRQ_CPU_FIQ 1
197
198
199
200
201
202
203#define KVM_ARM_IRQ_GIC_MAX 127
204
205
206#define KVM_NR_IRQCHIPS 1
207
208
209#define KVM_PSCI_FN_BASE 0x95c1ba5e
210#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
211
212#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
213#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
214#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
215#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
216
217#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
218#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
219#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
220#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
221
222#endif
223
