LXR qemu/linux-headers/asm-x86/kvm.h

   1#ifndef _ASM_X86_KVM_H
   2#define _ASM_X86_KVM_H
   3
   4/*
   5 * KVM x86 specific structures and definitions
   6 *
   7 */
   8
   9#include <linux/types.h>
  10#include <linux/ioctl.h>
  11
  12#define DE_VECTOR 0
  13#define DB_VECTOR 1
  14#define BP_VECTOR 3
  15#define OF_VECTOR 4
  16#define BR_VECTOR 5
  17#define UD_VECTOR 6
  18#define NM_VECTOR 7
  19#define DF_VECTOR 8
  20#define TS_VECTOR 10
  21#define NP_VECTOR 11
  22#define SS_VECTOR 12
  23#define GP_VECTOR 13
  24#define PF_VECTOR 14
  25#define MF_VECTOR 16
  26#define AC_VECTOR 17
  27#define MC_VECTOR 18
  28#define XM_VECTOR 19
  29#define VE_VECTOR 20
  30
  31/* Select x86 specific features in <linux/kvm.h> */
  32#define __KVM_HAVE_PIT
  33#define __KVM_HAVE_IOAPIC
  34#define __KVM_HAVE_IRQ_LINE
  35#define __KVM_HAVE_MSI
  36#define __KVM_HAVE_USER_NMI
  37#define __KVM_HAVE_GUEST_DEBUG
  38#define __KVM_HAVE_MSIX
  39#define __KVM_HAVE_MCE
  40#define __KVM_HAVE_PIT_STATE2
  41#define __KVM_HAVE_XEN_HVM
  42#define __KVM_HAVE_VCPU_EVENTS
  43#define __KVM_HAVE_DEBUGREGS
  44#define __KVM_HAVE_XSAVE
  45#define __KVM_HAVE_XCRS
  46#define __KVM_HAVE_READONLY_MEM
  47
  48/* Architectural interrupt line count. */
  49#define KVM_NR_INTERRUPTS 256
  50
  51struct kvm_memory_alias {
  52        __u32 slot;  /* this has a different namespace than memory slots */
  53        __u32 flags;
  54        __u64 guest_phys_addr;
  55        __u64 memory_size;
  56        __u64 target_phys_addr;
  57};
  58
  59/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
  60struct kvm_pic_state {
  61        __u8 last_irr;  /* edge detection */
  62        __u8 irr;               /* interrupt request register */
  63        __u8 imr;               /* interrupt mask register */
  64        __u8 isr;               /* interrupt service register */
  65        __u8 priority_add;      /* highest irq priority */
  66        __u8 irq_base;
  67        __u8 read_reg_select;
  68        __u8 poll;
  69        __u8 special_mask;
  70        __u8 init_state;
  71        __u8 auto_eoi;
  72        __u8 rotate_on_auto_eoi;
  73        __u8 special_fully_nested_mode;
  74        __u8 init4;             /* true if 4 byte init */
  75        __u8 elcr;              /* PIIX edge/trigger selection */
  76        __u8 elcr_mask;
  77};
  78
  79#define KVM_IOAPIC_NUM_PINS  24
  80struct kvm_ioapic_state {
  81        __u64 base_address;
  82        __u32 ioregsel;
  83        __u32 id;
  84        __u32 irr;
  85        __u32 pad;
  86        union {
  87                __u64 bits;
  88                struct {
  89                        __u8 vector;
  90                        __u8 delivery_mode:3;
  91                        __u8 dest_mode:1;
  92                        __u8 delivery_status:1;
  93                        __u8 polarity:1;
  94                        __u8 remote_irr:1;
  95                        __u8 trig_mode:1;
  96                        __u8 mask:1;
  97                        __u8 reserve:7;
  98                        __u8 reserved[4];
  99                        __u8 dest_id;
 100                } fields;
 101        } redirtbl[KVM_IOAPIC_NUM_PINS];
 102};
 103
 104#define KVM_IRQCHIP_PIC_MASTER   0
 105#define KVM_IRQCHIP_PIC_SLAVE    1
 106#define KVM_IRQCHIP_IOAPIC       2
 107#define KVM_NR_IRQCHIPS          3
 108
 109#define KVM_RUN_X86_SMM          (1 << 0)
 110
 111/* for KVM_GET_REGS and KVM_SET_REGS */
 112struct kvm_regs {
 113        /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
 114        __u64 rax, rbx, rcx, rdx;
 115        __u64 rsi, rdi, rsp, rbp;
 116        __u64 r8,  r9,  r10, r11;
 117        __u64 r12, r13, r14, r15;
 118        __u64 rip, rflags;
 119};
 120
 121/* for KVM_GET_LAPIC and KVM_SET_LAPIC */
 122#define KVM_APIC_REG_SIZE 0x400
 123struct kvm_lapic_state {
 124        char regs[KVM_APIC_REG_SIZE];
 125};
 126
 127struct kvm_segment {
 128        __u64 base;
 129        __u32 limit;
 130        __u16 selector;
 131        __u8  type;
 132        __u8  present, dpl, db, s, l, g, avl;
 133        __u8  unusable;
 134        __u8  padding;
 135};
 136
 137struct kvm_dtable {
 138        __u64 base;
 139        __u16 limit;
 140        __u16 padding[3];
 141};
 142
 143
 144/* for KVM_GET_SREGS and KVM_SET_SREGS */
 145struct kvm_sregs {
 146        /* out (KVM_GET_SREGS) / in (KVM_SET_SREGS) */
 147        struct kvm_segment cs, ds, es, fs, gs, ss;
 148        struct kvm_segment tr, ldt;
 149        struct kvm_dtable gdt, idt;
 150        __u64 cr0, cr2, cr3, cr4, cr8;
 151        __u64 efer;
 152        __u64 apic_base;
 153        __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
 154};
 155
 156/* for KVM_GET_FPU and KVM_SET_FPU */
 157struct kvm_fpu {
 158        __u8  fpr[8][16];
 159        __u16 fcw;
 160        __u16 fsw;
 161        __u8  ftwx;  /* in fxsave format */
 162        __u8  pad1;
 163        __u16 last_opcode;
 164        __u64 last_ip;
 165        __u64 last_dp;
 166        __u8  xmm[16][16];
 167        __u32 mxcsr;
 168        __u32 pad2;
 169};
 170
 171struct kvm_msr_entry {
 172        __u32 index;
 173        __u32 reserved;
 174        __u64 data;
 175};
 176
 177/* for KVM_GET_MSRS and KVM_SET_MSRS */
 178struct kvm_msrs {
 179        __u32 nmsrs; /* number of msrs in entries */
 180        __u32 pad;
 181
 182        struct kvm_msr_entry entries[0];
 183};
 184
 185/* for KVM_GET_MSR_INDEX_LIST */
 186struct kvm_msr_list {
 187        __u32 nmsrs; /* number of msrs in entries */
 188        __u32 indices[0];
 189};
 190
 191
 192struct kvm_cpuid_entry {
 193        __u32 function;
 194        __u32 eax;
 195        __u32 ebx;
 196        __u32 ecx;
 197        __u32 edx;
 198        __u32 padding;
 199};
 200
 201/* for KVM_SET_CPUID */
 202struct kvm_cpuid {
 203        __u32 nent;
 204        __u32 padding;
 205        struct kvm_cpuid_entry entries[0];
 206};
 207
 208struct kvm_cpuid_entry2 {
 209        __u32 function;
 210        __u32 index;
 211        __u32 flags;
 212        __u32 eax;
 213        __u32 ebx;
 214        __u32 ecx;
 215        __u32 edx;
 216        __u32 padding[3];
 217};
 218
 219#define KVM_CPUID_FLAG_SIGNIFCANT_INDEX         BIT(0)
 220#define KVM_CPUID_FLAG_STATEFUL_FUNC            BIT(1)
 221#define KVM_CPUID_FLAG_STATE_READ_NEXT          BIT(2)
 222
 223/* for KVM_SET_CPUID2 */
 224struct kvm_cpuid2 {
 225        __u32 nent;
 226        __u32 padding;
 227        struct kvm_cpuid_entry2 entries[0];
 228};
 229
 230/* for KVM_GET_PIT and KVM_SET_PIT */
 231struct kvm_pit_channel_state {
 232        __u32 count; /* can be 65536 */
 233        __u16 latched_count;
 234        __u8 count_latched;
 235        __u8 status_latched;
 236        __u8 status;
 237        __u8 read_state;
 238        __u8 write_state;
 239        __u8 write_latch;
 240        __u8 rw_mode;
 241        __u8 mode;
 242        __u8 bcd;
 243        __u8 gate;
 244        __s64 count_load_time;
 245};
 246
 247struct kvm_debug_exit_arch {
 248        __u32 exception;
 249        __u32 pad;
 250        __u64 pc;
 251        __u64 dr6;
 252        __u64 dr7;
 253};
 254
 255#define KVM_GUESTDBG_USE_SW_BP          0x00010000
 256#define KVM_GUESTDBG_USE_HW_BP          0x00020000
 257#define KVM_GUESTDBG_INJECT_DB          0x00040000
 258#define KVM_GUESTDBG_INJECT_BP          0x00080000
 259
 260/* for KVM_SET_GUEST_DEBUG */
 261struct kvm_guest_debug_arch {
 262        __u64 debugreg[8];
 263};
 264
 265struct kvm_pit_state {
 266        struct kvm_pit_channel_state channels[3];
 267};
 268
 269#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
 270
 271struct kvm_pit_state2 {
 272        struct kvm_pit_channel_state channels[3];
 273        __u32 flags;
 274        __u32 reserved[9];
 275};
 276
 277struct kvm_reinject_control {
 278        __u8 pit_reinject;
 279        __u8 reserved[31];
 280};
 281
 282/* When set in flags, include corresponding fields on KVM_SET_VCPU_EVENTS */
 283#define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
 284#define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
 285#define KVM_VCPUEVENT_VALID_SHADOW      0x00000004
 286#define KVM_VCPUEVENT_VALID_SMM         0x00000008
 287
 288/* Interrupt shadow states */
 289#define KVM_X86_SHADOW_INT_MOV_SS       0x01
 290#define KVM_X86_SHADOW_INT_STI          0x02
 291
 292/* for KVM_GET/SET_VCPU_EVENTS */
 293struct kvm_vcpu_events {
 294        struct {
 295                __u8 injected;
 296                __u8 nr;
 297                __u8 has_error_code;
 298                __u8 pad;
 299                __u32 error_code;
 300        } exception;
 301        struct {
 302                __u8 injected;
 303                __u8 nr;
 304                __u8 soft;
 305                __u8 shadow;
 306        } interrupt;
 307        struct {
 308                __u8 injected;
 309                __u8 pending;
 310                __u8 masked;
 311                __u8 pad;
 312        } nmi;
 313        __u32 sipi_vector;
 314        __u32 flags;
 315        struct {
 316                __u8 smm;
 317                __u8 pending;
 318                __u8 smm_inside_nmi;
 319                __u8 latched_init;
 320        } smi;
 321        __u32 reserved[9];
 322};
 323
 324/* for KVM_GET/SET_DEBUGREGS */
 325struct kvm_debugregs {
 326        __u64 db[4];
 327        __u64 dr6;
 328        __u64 dr7;
 329        __u64 flags;
 330        __u64 reserved[9];
 331};
 332
 333/* for KVM_CAP_XSAVE */
 334struct kvm_xsave {
 335        __u32 region[1024];
 336};
 337
 338#define KVM_MAX_XCRS    16
 339
 340struct kvm_xcr {
 341        __u32 xcr;
 342        __u32 reserved;
 343        __u64 value;
 344};
 345
 346struct kvm_xcrs {
 347        __u32 nr_xcrs;
 348        __u32 flags;
 349        struct kvm_xcr xcrs[KVM_MAX_XCRS];
 350        __u64 padding[16];
 351};
 352
 353/* definition of registers in kvm_run */
 354struct kvm_sync_regs {
 355};
 356
 357#define KVM_X86_QUIRK_LINT0_REENABLED   (1 << 0)
 358#define KVM_X86_QUIRK_CD_NW_CLEARED     (1 << 1)
 359
 360#endif /* _ASM_X86_KVM_H */
 361