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25#ifndef TARGET_ARM_INTERNALS_H
26#define TARGET_ARM_INTERNALS_H
27
28
29#define BANK_USRSYS 0
30#define BANK_SVC 1
31#define BANK_ABT 2
32#define BANK_UND 3
33#define BANK_IRQ 4
34#define BANK_FIQ 5
35#define BANK_HYP 6
36#define BANK_MON 7
37
38static inline bool excp_is_internal(int excp)
39{
40
41
42
43 return excp == EXCP_INTERRUPT
44 || excp == EXCP_HLT
45 || excp == EXCP_DEBUG
46 || excp == EXCP_HALTED
47 || excp == EXCP_EXCEPTION_EXIT
48 || excp == EXCP_KERNEL_TRAP
49 || excp == EXCP_SEMIHOST
50 || excp == EXCP_STREX;
51}
52
53
54
55
56static const char * const excnames[] = {
57 [EXCP_UDEF] = "Undefined Instruction",
58 [EXCP_SWI] = "SVC",
59 [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
60 [EXCP_DATA_ABORT] = "Data Abort",
61 [EXCP_IRQ] = "IRQ",
62 [EXCP_FIQ] = "FIQ",
63 [EXCP_BKPT] = "Breakpoint",
64 [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
65 [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
66 [EXCP_STREX] = "QEMU intercept of STREX",
67 [EXCP_HVC] = "Hypervisor Call",
68 [EXCP_HYP_TRAP] = "Hypervisor Trap",
69 [EXCP_SMC] = "Secure Monitor Call",
70 [EXCP_VIRQ] = "Virtual IRQ",
71 [EXCP_VFIQ] = "Virtual FIQ",
72 [EXCP_SEMIHOST] = "Semihosting call",
73 [EXCP_WFI] = "WFI",
74};
75
76static inline void arm_log_exception(int idx)
77{
78 if (qemu_loglevel_mask(CPU_LOG_INT)) {
79 const char *exc = NULL;
80
81 if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
82 exc = excnames[idx];
83 }
84 if (!exc) {
85 exc = "unknown";
86 }
87 qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
88 }
89}
90
91
92
93
94#define GTIMER_SCALE 16
95
96
97
98
99
100
101
102static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
103{
104 static const unsigned int map[4] = {
105 [1] = BANK_SVC,
106 [2] = BANK_HYP,
107 [3] = BANK_MON,
108 };
109 assert(el >= 1 && el <= 3);
110 return map[el];
111}
112
113
114static inline int bank_number(int mode)
115{
116 switch (mode) {
117 case ARM_CPU_MODE_USR:
118 case ARM_CPU_MODE_SYS:
119 return BANK_USRSYS;
120 case ARM_CPU_MODE_SVC:
121 return BANK_SVC;
122 case ARM_CPU_MODE_ABT:
123 return BANK_ABT;
124 case ARM_CPU_MODE_UND:
125 return BANK_UND;
126 case ARM_CPU_MODE_IRQ:
127 return BANK_IRQ;
128 case ARM_CPU_MODE_FIQ:
129 return BANK_FIQ;
130 case ARM_CPU_MODE_HYP:
131 return BANK_HYP;
132 case ARM_CPU_MODE_MON:
133 return BANK_MON;
134 }
135 g_assert_not_reached();
136}
137
138void switch_mode(CPUARMState *, int);
139void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
140void arm_translate_init(void);
141
142enum arm_fprounding {
143 FPROUNDING_TIEEVEN,
144 FPROUNDING_POSINF,
145 FPROUNDING_NEGINF,
146 FPROUNDING_ZERO,
147 FPROUNDING_TIEAWAY,
148 FPROUNDING_ODD
149};
150
151int arm_rmode_to_sf(int rmode);
152
153static inline void aarch64_save_sp(CPUARMState *env, int el)
154{
155 if (env->pstate & PSTATE_SP) {
156 env->sp_el[el] = env->xregs[31];
157 } else {
158 env->sp_el[0] = env->xregs[31];
159 }
160}
161
162static inline void aarch64_restore_sp(CPUARMState *env, int el)
163{
164 if (env->pstate & PSTATE_SP) {
165 env->xregs[31] = env->sp_el[el];
166 } else {
167 env->xregs[31] = env->sp_el[0];
168 }
169}
170
171static inline void update_spsel(CPUARMState *env, uint32_t imm)
172{
173 unsigned int cur_el = arm_current_el(env);
174
175
176
177 if (!((imm ^ env->pstate) & PSTATE_SP)) {
178 return;
179 }
180 aarch64_save_sp(env, cur_el);
181 env->pstate = deposit32(env->pstate, 0, 1, imm);
182
183
184
185
186 assert(cur_el >= 1 && cur_el <= 3);
187 aarch64_restore_sp(env, cur_el);
188}
189
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193
194
195
196
197static inline unsigned int arm_pamax(ARMCPU *cpu)
198{
199 static const unsigned int pamax_map[] = {
200 [0] = 32,
201 [1] = 36,
202 [2] = 40,
203 [3] = 42,
204 [4] = 44,
205 [5] = 48,
206 };
207 unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
208
209
210
211 assert(parange < ARRAY_SIZE(pamax_map));
212 return pamax_map[parange];
213}
214
215
216
217
218
219static inline bool extended_addresses_enabled(CPUARMState *env)
220{
221 TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
222 return arm_el_is_aa64(env, 1) ||
223 (arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
224}
225
226
227enum arm_exception_class {
228 EC_UNCATEGORIZED = 0x00,
229 EC_WFX_TRAP = 0x01,
230 EC_CP15RTTRAP = 0x03,
231 EC_CP15RRTTRAP = 0x04,
232 EC_CP14RTTRAP = 0x05,
233 EC_CP14DTTRAP = 0x06,
234 EC_ADVSIMDFPACCESSTRAP = 0x07,
235 EC_FPIDTRAP = 0x08,
236 EC_CP14RRTTRAP = 0x0c,
237 EC_ILLEGALSTATE = 0x0e,
238 EC_AA32_SVC = 0x11,
239 EC_AA32_HVC = 0x12,
240 EC_AA32_SMC = 0x13,
241 EC_AA64_SVC = 0x15,
242 EC_AA64_HVC = 0x16,
243 EC_AA64_SMC = 0x17,
244 EC_SYSTEMREGISTERTRAP = 0x18,
245 EC_INSNABORT = 0x20,
246 EC_INSNABORT_SAME_EL = 0x21,
247 EC_PCALIGNMENT = 0x22,
248 EC_DATAABORT = 0x24,
249 EC_DATAABORT_SAME_EL = 0x25,
250 EC_SPALIGNMENT = 0x26,
251 EC_AA32_FPTRAP = 0x28,
252 EC_AA64_FPTRAP = 0x2c,
253 EC_SERROR = 0x2f,
254 EC_BREAKPOINT = 0x30,
255 EC_BREAKPOINT_SAME_EL = 0x31,
256 EC_SOFTWARESTEP = 0x32,
257 EC_SOFTWARESTEP_SAME_EL = 0x33,
258 EC_WATCHPOINT = 0x34,
259 EC_WATCHPOINT_SAME_EL = 0x35,
260 EC_AA32_BKPT = 0x38,
261 EC_VECTORCATCH = 0x3a,
262 EC_AA64_BKPT = 0x3c,
263};
264
265#define ARM_EL_EC_SHIFT 26
266#define ARM_EL_IL_SHIFT 25
267#define ARM_EL_ISV_SHIFT 24
268#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
269#define ARM_EL_ISV (1 << ARM_EL_ISV_SHIFT)
270
271
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275
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277
278
279
280static inline uint32_t syn_uncategorized(void)
281{
282 return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
283}
284
285static inline uint32_t syn_aa64_svc(uint32_t imm16)
286{
287 return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
288}
289
290static inline uint32_t syn_aa64_hvc(uint32_t imm16)
291{
292 return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
293}
294
295static inline uint32_t syn_aa64_smc(uint32_t imm16)
296{
297 return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
298}
299
300static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_16bit)
301{
302 return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
303 | (is_16bit ? 0 : ARM_EL_IL);
304}
305
306static inline uint32_t syn_aa32_hvc(uint32_t imm16)
307{
308 return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
309}
310
311static inline uint32_t syn_aa32_smc(void)
312{
313 return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
314}
315
316static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
317{
318 return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
319}
320
321static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_16bit)
322{
323 return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
324 | (is_16bit ? 0 : ARM_EL_IL);
325}
326
327static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
328 int crn, int crm, int rt,
329 int isread)
330{
331 return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
332 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
333 | (crm << 1) | isread;
334}
335
336static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
337 int crn, int crm, int rt, int isread,
338 bool is_16bit)
339{
340 return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
341 | (is_16bit ? 0 : ARM_EL_IL)
342 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
343 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
344}
345
346static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
347 int crn, int crm, int rt, int isread,
348 bool is_16bit)
349{
350 return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
351 | (is_16bit ? 0 : ARM_EL_IL)
352 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
353 | (crn << 10) | (rt << 5) | (crm << 1) | isread;
354}
355
356static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
357 int rt, int rt2, int isread,
358 bool is_16bit)
359{
360 return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
361 | (is_16bit ? 0 : ARM_EL_IL)
362 | (cv << 24) | (cond << 20) | (opc1 << 16)
363 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
364}
365
366static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
367 int rt, int rt2, int isread,
368 bool is_16bit)
369{
370 return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
371 | (is_16bit ? 0 : ARM_EL_IL)
372 | (cv << 24) | (cond << 20) | (opc1 << 16)
373 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
374}
375
376static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_16bit)
377{
378 return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
379 | (is_16bit ? 0 : ARM_EL_IL)
380 | (cv << 24) | (cond << 20);
381}
382
383static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
384{
385 return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
386 | (ea << 9) | (s1ptw << 7) | fsc;
387}
388
389static inline uint32_t syn_data_abort_no_iss(int same_el,
390 int ea, int cm, int s1ptw,
391 int wnr, int fsc)
392{
393 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
394 | ARM_EL_IL
395 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
396}
397
398static inline uint32_t syn_data_abort_with_iss(int same_el,
399 int sas, int sse, int srt,
400 int sf, int ar,
401 int ea, int cm, int s1ptw,
402 int wnr, int fsc,
403 bool is_16bit)
404{
405 return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
406 | (is_16bit ? 0 : ARM_EL_IL)
407 | ARM_EL_ISV | (sas << 22) | (sse << 21) | (srt << 16)
408 | (sf << 15) | (ar << 14)
409 | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
410}
411
412static inline uint32_t syn_swstep(int same_el, int isv, int ex)
413{
414 return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
415 | (isv << 24) | (ex << 6) | 0x22;
416}
417
418static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
419{
420 return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
421 | (cm << 8) | (wnr << 6) | 0x22;
422}
423
424static inline uint32_t syn_breakpoint(int same_el)
425{
426 return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
427 | ARM_EL_IL | 0x22;
428}
429
430static inline uint32_t syn_wfx(int cv, int cond, int ti)
431{
432 return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL |
433 (cv << 24) | (cond << 20) | ti;
434}
435
436
437
438
439void hw_watchpoint_update(ARMCPU *cpu, int n);
440
441
442
443
444void hw_watchpoint_update_all(ARMCPU *cpu);
445
446
447
448void hw_breakpoint_update(ARMCPU *cpu, int n);
449
450
451
452
453void hw_breakpoint_update_all(ARMCPU *cpu);
454
455
456bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
457
458
459void arm_debug_excp_handler(CPUState *cs);
460
461#ifdef CONFIG_USER_ONLY
462static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
463{
464 return false;
465}
466#else
467
468bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
469
470void arm_handle_psci_call(ARMCPU *cpu);
471#endif
472
473
474
475
476
477
478
479typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
480struct ARMMMUFaultInfo {
481 target_ulong s2addr;
482 bool stage2;
483 bool s1ptw;
484};
485
486
487bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
488 uint32_t *fsr, ARMMMUFaultInfo *fi);
489
490
491
492bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx);
493
494
495void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
496 int is_user, uintptr_t retaddr);
497
498#endif
499