LXR qemu/target-cris/cpu.h

   1/*
   2 *  CRIS virtual CPU header
   3 *
   4 *  Copyright (c) 2007 AXIS Communications AB
   5 *  Written by Edgar E. Iglesias
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#ifndef CPU_CRIS_H
  21#define CPU_CRIS_H
  22
  23#include "qemu-common.h"
  24
  25#define TARGET_LONG_BITS 32
  26
  27#define CPUArchState struct CPUCRISState
  28
  29#include "exec/cpu-defs.h"
  30
  31#define EXCP_NMI        1
  32#define EXCP_GURU       2
  33#define EXCP_BUSFAULT   3
  34#define EXCP_IRQ        4
  35#define EXCP_BREAK      5
  36
  37/* CRIS-specific interrupt pending bits.  */
  38#define CPU_INTERRUPT_NMI       CPU_INTERRUPT_TGT_EXT_3
  39
  40/* CRUS CPU device objects interrupt lines.  */
  41#define CRIS_CPU_IRQ 0
  42#define CRIS_CPU_NMI 1
  43
  44/* Register aliases. R0 - R15 */
  45#define R_FP  8
  46#define R_SP  14
  47#define R_ACR 15
  48
  49/* Support regs, P0 - P15  */
  50#define PR_BZ  0
  51#define PR_VR  1
  52#define PR_PID 2
  53#define PR_SRS 3
  54#define PR_WZ  4
  55#define PR_EXS 5
  56#define PR_EDA 6
  57#define PR_PREFIX 6    /* On CRISv10 P6 is reserved, we use it as prefix.  */
  58#define PR_MOF 7
  59#define PR_DZ  8
  60#define PR_EBP 9
  61#define PR_ERP 10
  62#define PR_SRP 11
  63#define PR_NRP 12
  64#define PR_CCS 13
  65#define PR_USP 14
  66#define PRV10_BRP 14
  67#define PR_SPC 15
  68
  69/* CPU flags.  */
  70#define Q_FLAG 0x80000000
  71#define M_FLAG_V32 0x40000000
  72#define PFIX_FLAG 0x800      /* CRISv10 Only.  */
  73#define F_FLAG_V10 0x400
  74#define P_FLAG_V10 0x200
  75#define S_FLAG 0x200
  76#define R_FLAG 0x100
  77#define P_FLAG 0x80
  78#define M_FLAG_V10 0x80
  79#define U_FLAG 0x40
  80#define I_FLAG 0x20
  81#define X_FLAG 0x10
  82#define N_FLAG 0x08
  83#define Z_FLAG 0x04
  84#define V_FLAG 0x02
  85#define C_FLAG 0x01
  86#define ALU_FLAGS 0x1F
  87
  88/* Condition codes.  */
  89#define CC_CC   0
  90#define CC_CS   1
  91#define CC_NE   2
  92#define CC_EQ   3
  93#define CC_VC   4
  94#define CC_VS   5
  95#define CC_PL   6
  96#define CC_MI   7
  97#define CC_LS   8
  98#define CC_HI   9
  99#define CC_GE  10
 100#define CC_LT  11
 101#define CC_GT  12
 102#define CC_LE  13
 103#define CC_A   14
 104#define CC_P   15
 105
 106#define NB_MMU_MODES 2
 107
 108typedef struct {
 109    uint32_t hi;
 110    uint32_t lo;
 111} TLBSet;
 112
 113typedef struct CPUCRISState {
 114        uint32_t regs[16];
 115        /* P0 - P15 are referred to as special registers in the docs.  */
 116        uint32_t pregs[16];
 117
 118        /* Pseudo register for the PC. Not directly accessible on CRIS.  */
 119        uint32_t pc;
 120
 121        /* Pseudo register for the kernel stack.  */
 122        uint32_t ksp;
 123
 124        /* Branch.  */
 125        int dslot;
 126        int btaken;
 127        uint32_t btarget;
 128
 129        /* Condition flag tracking.  */
 130        uint32_t cc_op;
 131        uint32_t cc_mask;
 132        uint32_t cc_dest;
 133        uint32_t cc_src;
 134        uint32_t cc_result;
 135        /* size of the operation, 1 = byte, 2 = word, 4 = dword.  */
 136        int cc_size;
 137        /* X flag at the time of cc snapshot.  */
 138        int cc_x;
 139
 140        /* CRIS has certain insns that lockout interrupts.  */
 141        int locked_irq;
 142        int interrupt_vector;
 143        int fault_vector;
 144        int trap_vector;
 145
 146        /* FIXME: add a check in the translator to avoid writing to support
 147           register sets beyond the 4th. The ISA allows up to 256! but in
 148           practice there is no core that implements more than 4.
 149
 150           Support function registers are used to control units close to the
 151           core. Accesses do not pass down the normal hierarchy.
 152        */
 153        uint32_t sregs[4][16];
 154
 155        /* Linear feedback shift reg in the mmu. Used to provide pseudo
 156           randomness for the 'hint' the mmu gives to sw for choosing valid
 157           sets on TLB refills.  */
 158        uint32_t mmu_rand_lfsr;
 159
 160        /*
 161         * We just store the stores to the tlbset here for later evaluation
 162         * when the hw needs access to them.
 163         *
 164         * One for I and another for D.
 165         */
 166        TLBSet tlbsets[2][4][16];
 167
 168        CPU_COMMON
 169
 170    /* Members from load_info on are preserved across resets.  */
 171    void *load_info;
 172} CPUCRISState;
 173
 174#include "cpu-qom.h"
 175
 176CRISCPU *cpu_cris_init(const char *cpu_model);
 177int cpu_cris_exec(CPUState *cpu);
 178/* you can call this signal handler from your SIGBUS and SIGSEGV
 179   signal handlers to inform the virtual CPU of exceptions. non zero
 180   is returned if the signal was handled by the virtual CPU.  */
 181int cpu_cris_signal_handler(int host_signum, void *pinfo,
 182                           void *puc);
 183
 184void cris_initialize_tcg(void);
 185void cris_initialize_crisv10_tcg(void);
 186
 187enum {
 188    CC_OP_DYNAMIC, /* Use env->cc_op  */
 189    CC_OP_FLAGS,
 190    CC_OP_CMP,
 191    CC_OP_MOVE,
 192    CC_OP_ADD,
 193    CC_OP_ADDC,
 194    CC_OP_MCP,
 195    CC_OP_ADDU,
 196    CC_OP_SUB,
 197    CC_OP_SUBU,
 198    CC_OP_NEG,
 199    CC_OP_BTST,
 200    CC_OP_MULS,
 201    CC_OP_MULU,
 202    CC_OP_DSTEP,
 203    CC_OP_MSTEP,
 204    CC_OP_BOUND,
 205
 206    CC_OP_OR,
 207    CC_OP_AND,
 208    CC_OP_XOR,
 209    CC_OP_LSL,
 210    CC_OP_LSR,
 211    CC_OP_ASR,
 212    CC_OP_LZ
 213};
 214
 215/* CRIS uses 8k pages.  */
 216#define TARGET_PAGE_BITS 13
 217#define MMAP_SHIFT TARGET_PAGE_BITS
 218
 219#define TARGET_PHYS_ADDR_SPACE_BITS 32
 220#define TARGET_VIRT_ADDR_SPACE_BITS 32
 221
 222#define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
 223
 224#define cpu_exec cpu_cris_exec
 225#define cpu_signal_handler cpu_cris_signal_handler
 226
 227/* MMU modes definitions */
 228#define MMU_MODE0_SUFFIX _kernel
 229#define MMU_MODE1_SUFFIX _user
 230#define MMU_USER_IDX 1
 231static inline int cpu_mmu_index (CPUCRISState *env, bool ifetch)
 232{
 233        return !!(env->pregs[PR_CCS] & U_FLAG);
 234}
 235
 236int cris_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 237                              int mmu_idx);
 238
 239/* Support function regs.  */
 240#define SFR_RW_GC_CFG      0][0
 241#define SFR_RW_MM_CFG      env->pregs[PR_SRS]][0
 242#define SFR_RW_MM_KBASE_LO env->pregs[PR_SRS]][1
 243#define SFR_RW_MM_KBASE_HI env->pregs[PR_SRS]][2
 244#define SFR_R_MM_CAUSE     env->pregs[PR_SRS]][3
 245#define SFR_RW_MM_TLB_SEL  env->pregs[PR_SRS]][4
 246#define SFR_RW_MM_TLB_LO   env->pregs[PR_SRS]][5
 247#define SFR_RW_MM_TLB_HI   env->pregs[PR_SRS]][6
 248
 249#include "exec/cpu-all.h"
 250
 251static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc,
 252                                        target_ulong *cs_base, int *flags)
 253{
 254    *pc = env->pc;
 255    *cs_base = 0;
 256    *flags = env->dslot |
 257            (env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG
 258                                     | X_FLAG | PFIX_FLAG));
 259}
 260
 261#define cpu_list cris_cpu_list
 262void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 263
 264#include "exec/exec-all.h"
 265
 266#endif
 267