1#include "qemu/osdep.h"
2#include "hw/hw.h"
3#include "hw/boards.h"
4#include "hw/i386/pc.h"
5#include "hw/isa/isa.h"
6
7#include "cpu.h"
8#include "sysemu/kvm.h"
9
10#include "qemu/error-report.h"
11
12static const VMStateDescription vmstate_segment = {
13 .name = "segment",
14 .version_id = 1,
15 .minimum_version_id = 1,
16 .fields = (VMStateField[]) {
17 VMSTATE_UINT32(selector, SegmentCache),
18 VMSTATE_UINTTL(base, SegmentCache),
19 VMSTATE_UINT32(limit, SegmentCache),
20 VMSTATE_UINT32(flags, SegmentCache),
21 VMSTATE_END_OF_LIST()
22 }
23};
24
25#define VMSTATE_SEGMENT(_field, _state) { \
26 .name = (stringify(_field)), \
27 .size = sizeof(SegmentCache), \
28 .vmsd = &vmstate_segment, \
29 .flags = VMS_STRUCT, \
30 .offset = offsetof(_state, _field) \
31 + type_check(SegmentCache,typeof_field(_state, _field)) \
32}
33
34#define VMSTATE_SEGMENT_ARRAY(_field, _state, _n) \
35 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_segment, SegmentCache)
36
37static const VMStateDescription vmstate_xmm_reg = {
38 .name = "xmm_reg",
39 .version_id = 1,
40 .minimum_version_id = 1,
41 .fields = (VMStateField[]) {
42 VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
43 VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
44 VMSTATE_END_OF_LIST()
45 }
46};
47
48#define VMSTATE_XMM_REGS(_field, _state, _start) \
49 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
50 vmstate_xmm_reg, ZMMReg)
51
52
53static const VMStateDescription vmstate_ymmh_reg = {
54 .name = "ymmh_reg",
55 .version_id = 1,
56 .minimum_version_id = 1,
57 .fields = (VMStateField[]) {
58 VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
59 VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
60 VMSTATE_END_OF_LIST()
61 }
62};
63
64#define VMSTATE_YMMH_REGS_VARS(_field, _state, _start, _v) \
65 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, _v, \
66 vmstate_ymmh_reg, ZMMReg)
67
68static const VMStateDescription vmstate_zmmh_reg = {
69 .name = "zmmh_reg",
70 .version_id = 1,
71 .minimum_version_id = 1,
72 .fields = (VMStateField[]) {
73 VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
74 VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
75 VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
76 VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
77 VMSTATE_END_OF_LIST()
78 }
79};
80
81#define VMSTATE_ZMMH_REGS_VARS(_field, _state, _start) \
82 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
83 vmstate_zmmh_reg, ZMMReg)
84
85#ifdef TARGET_X86_64
86static const VMStateDescription vmstate_hi16_zmm_reg = {
87 .name = "hi16_zmm_reg",
88 .version_id = 1,
89 .minimum_version_id = 1,
90 .fields = (VMStateField[]) {
91 VMSTATE_UINT64(ZMM_Q(0), ZMMReg),
92 VMSTATE_UINT64(ZMM_Q(1), ZMMReg),
93 VMSTATE_UINT64(ZMM_Q(2), ZMMReg),
94 VMSTATE_UINT64(ZMM_Q(3), ZMMReg),
95 VMSTATE_UINT64(ZMM_Q(4), ZMMReg),
96 VMSTATE_UINT64(ZMM_Q(5), ZMMReg),
97 VMSTATE_UINT64(ZMM_Q(6), ZMMReg),
98 VMSTATE_UINT64(ZMM_Q(7), ZMMReg),
99 VMSTATE_END_OF_LIST()
100 }
101};
102
103#define VMSTATE_Hi16_ZMM_REGS_VARS(_field, _state, _start) \
104 VMSTATE_STRUCT_SUB_ARRAY(_field, _state, _start, CPU_NB_REGS, 0, \
105 vmstate_hi16_zmm_reg, ZMMReg)
106#endif
107
108static const VMStateDescription vmstate_bnd_regs = {
109 .name = "bnd_regs",
110 .version_id = 1,
111 .minimum_version_id = 1,
112 .fields = (VMStateField[]) {
113 VMSTATE_UINT64(lb, BNDReg),
114 VMSTATE_UINT64(ub, BNDReg),
115 VMSTATE_END_OF_LIST()
116 }
117};
118
119#define VMSTATE_BND_REGS(_field, _state, _n) \
120 VMSTATE_STRUCT_ARRAY(_field, _state, _n, 0, vmstate_bnd_regs, BNDReg)
121
122static const VMStateDescription vmstate_mtrr_var = {
123 .name = "mtrr_var",
124 .version_id = 1,
125 .minimum_version_id = 1,
126 .fields = (VMStateField[]) {
127 VMSTATE_UINT64(base, MTRRVar),
128 VMSTATE_UINT64(mask, MTRRVar),
129 VMSTATE_END_OF_LIST()
130 }
131};
132
133#define VMSTATE_MTRR_VARS(_field, _state, _n, _v) \
134 VMSTATE_STRUCT_ARRAY(_field, _state, _n, _v, vmstate_mtrr_var, MTRRVar)
135
136static void put_fpreg_error(QEMUFile *f, void *opaque, size_t size)
137{
138 fprintf(stderr, "call put_fpreg() with invalid arguments\n");
139 exit(0);
140}
141
142
143union x86_longdouble {
144 uint64_t mant;
145 uint16_t exp;
146};
147
148#define MANTD1(fp) (fp & ((1LL << 52) - 1))
149#define EXPBIAS1 1023
150#define EXPD1(fp) ((fp >> 52) & 0x7FF)
151#define SIGND1(fp) ((fp >> 32) & 0x80000000)
152
153static void fp64_to_fp80(union x86_longdouble *p, uint64_t temp)
154{
155 int e;
156
157 p->mant = (MANTD1(temp) << 11) | (1LL << 63);
158
159 e = EXPD1(temp) - EXPBIAS1 + 16383;
160 e |= SIGND1(temp) >> 16;
161 p->exp = e;
162}
163
164static int get_fpreg(QEMUFile *f, void *opaque, size_t size)
165{
166 FPReg *fp_reg = opaque;
167 uint64_t mant;
168 uint16_t exp;
169
170 qemu_get_be64s(f, &mant);
171 qemu_get_be16s(f, &exp);
172 fp_reg->d = cpu_set_fp80(mant, exp);
173 return 0;
174}
175
176static void put_fpreg(QEMUFile *f, void *opaque, size_t size)
177{
178 FPReg *fp_reg = opaque;
179 uint64_t mant;
180 uint16_t exp;
181
182
183 cpu_get_fp80(&mant, &exp, fp_reg->d);
184 qemu_put_be64s(f, &mant);
185 qemu_put_be16s(f, &exp);
186}
187
188static const VMStateInfo vmstate_fpreg = {
189 .name = "fpreg",
190 .get = get_fpreg,
191 .put = put_fpreg,
192};
193
194static int get_fpreg_1_mmx(QEMUFile *f, void *opaque, size_t size)
195{
196 union x86_longdouble *p = opaque;
197 uint64_t mant;
198
199 qemu_get_be64s(f, &mant);
200 p->mant = mant;
201 p->exp = 0xffff;
202 return 0;
203}
204
205static const VMStateInfo vmstate_fpreg_1_mmx = {
206 .name = "fpreg_1_mmx",
207 .get = get_fpreg_1_mmx,
208 .put = put_fpreg_error,
209};
210
211static int get_fpreg_1_no_mmx(QEMUFile *f, void *opaque, size_t size)
212{
213 union x86_longdouble *p = opaque;
214 uint64_t mant;
215
216 qemu_get_be64s(f, &mant);
217 fp64_to_fp80(p, mant);
218 return 0;
219}
220
221static const VMStateInfo vmstate_fpreg_1_no_mmx = {
222 .name = "fpreg_1_no_mmx",
223 .get = get_fpreg_1_no_mmx,
224 .put = put_fpreg_error,
225};
226
227static bool fpregs_is_0(void *opaque, int version_id)
228{
229 X86CPU *cpu = opaque;
230 CPUX86State *env = &cpu->env;
231
232 return (env->fpregs_format_vmstate == 0);
233}
234
235static bool fpregs_is_1_mmx(void *opaque, int version_id)
236{
237 X86CPU *cpu = opaque;
238 CPUX86State *env = &cpu->env;
239 int guess_mmx;
240
241 guess_mmx = ((env->fptag_vmstate == 0xff) &&
242 (env->fpus_vmstate & 0x3800) == 0);
243 return (guess_mmx && (env->fpregs_format_vmstate == 1));
244}
245
246static bool fpregs_is_1_no_mmx(void *opaque, int version_id)
247{
248 X86CPU *cpu = opaque;
249 CPUX86State *env = &cpu->env;
250 int guess_mmx;
251
252 guess_mmx = ((env->fptag_vmstate == 0xff) &&
253 (env->fpus_vmstate & 0x3800) == 0);
254 return (!guess_mmx && (env->fpregs_format_vmstate == 1));
255}
256
257#define VMSTATE_FP_REGS(_field, _state, _n) \
258 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_0, vmstate_fpreg, FPReg), \
259 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_mmx, vmstate_fpreg_1_mmx, FPReg), \
260 VMSTATE_ARRAY_TEST(_field, _state, _n, fpregs_is_1_no_mmx, vmstate_fpreg_1_no_mmx, FPReg)
261
262static bool version_is_5(void *opaque, int version_id)
263{
264 return version_id == 5;
265}
266
267#ifdef TARGET_X86_64
268static bool less_than_7(void *opaque, int version_id)
269{
270 return version_id < 7;
271}
272
273static int get_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
274{
275 uint64_t *v = pv;
276 *v = qemu_get_be32(f);
277 return 0;
278}
279
280static void put_uint64_as_uint32(QEMUFile *f, void *pv, size_t size)
281{
282 uint64_t *v = pv;
283 qemu_put_be32(f, *v);
284}
285
286static const VMStateInfo vmstate_hack_uint64_as_uint32 = {
287 .name = "uint64_as_uint32",
288 .get = get_uint64_as_uint32,
289 .put = put_uint64_as_uint32,
290};
291
292#define VMSTATE_HACK_UINT32(_f, _s, _t) \
293 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint64_as_uint32, uint64_t)
294#endif
295
296static void cpu_pre_save(void *opaque)
297{
298 X86CPU *cpu = opaque;
299 CPUX86State *env = &cpu->env;
300 int i;
301
302
303 env->fpus_vmstate = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
304 env->fptag_vmstate = 0;
305 for(i = 0; i < 8; i++) {
306 env->fptag_vmstate |= ((!env->fptags[i]) << i);
307 }
308
309 env->fpregs_format_vmstate = 0;
310
311
312
313
314
315
316
317
318 if (!(env->cr[0] & CR0_PE_MASK) &&
319 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
320 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
321 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
322 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
323 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
324 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
325 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
326 }
327
328}
329
330static int cpu_post_load(void *opaque, int version_id)
331{
332 X86CPU *cpu = opaque;
333 CPUState *cs = CPU(cpu);
334 CPUX86State *env = &cpu->env;
335 int i;
336
337 if (env->tsc_khz && env->user_tsc_khz &&
338 env->tsc_khz != env->user_tsc_khz) {
339 error_report("Mismatch between user-specified TSC frequency and "
340 "migrated TSC frequency");
341 return -EINVAL;
342 }
343
344
345
346
347
348
349
350
351
352 if (!(env->cr[0] & CR0_PE_MASK) &&
353 (env->segs[R_CS].flags >> DESC_DPL_SHIFT & 3) != 0) {
354 env->segs[R_CS].flags &= ~(env->segs[R_CS].flags & DESC_DPL_MASK);
355 env->segs[R_DS].flags &= ~(env->segs[R_DS].flags & DESC_DPL_MASK);
356 env->segs[R_ES].flags &= ~(env->segs[R_ES].flags & DESC_DPL_MASK);
357 env->segs[R_FS].flags &= ~(env->segs[R_FS].flags & DESC_DPL_MASK);
358 env->segs[R_GS].flags &= ~(env->segs[R_GS].flags & DESC_DPL_MASK);
359 env->segs[R_SS].flags &= ~(env->segs[R_SS].flags & DESC_DPL_MASK);
360 }
361
362
363
364
365
366
367 env->hflags &= ~HF_CPL_MASK;
368 env->hflags |= (env->segs[R_SS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
369
370 env->fpstt = (env->fpus_vmstate >> 11) & 7;
371 env->fpus = env->fpus_vmstate & ~0x3800;
372 env->fptag_vmstate ^= 0xff;
373 for(i = 0; i < 8; i++) {
374 env->fptags[i] = (env->fptag_vmstate >> i) & 1;
375 }
376 update_fp_status(env);
377
378 cpu_breakpoint_remove_all(cs, BP_CPU);
379 cpu_watchpoint_remove_all(cs, BP_CPU);
380 {
381
382
383 target_ulong dr7 = env->dr[7];
384 env->dr[7] = dr7 & ~(DR7_GLOBAL_BP_MASK | DR7_LOCAL_BP_MASK);
385 cpu_x86_update_dr7(env, dr7);
386 }
387 tlb_flush(cs, 1);
388
389 if (tcg_enabled()) {
390 cpu_smm_update(cpu);
391 }
392 return 0;
393}
394
395static bool async_pf_msr_needed(void *opaque)
396{
397 X86CPU *cpu = opaque;
398
399 return cpu->env.async_pf_en_msr != 0;
400}
401
402static bool pv_eoi_msr_needed(void *opaque)
403{
404 X86CPU *cpu = opaque;
405
406 return cpu->env.pv_eoi_en_msr != 0;
407}
408
409static bool steal_time_msr_needed(void *opaque)
410{
411 X86CPU *cpu = opaque;
412
413 return cpu->env.steal_time_msr != 0;
414}
415
416static const VMStateDescription vmstate_steal_time_msr = {
417 .name = "cpu/steal_time_msr",
418 .version_id = 1,
419 .minimum_version_id = 1,
420 .needed = steal_time_msr_needed,
421 .fields = (VMStateField[]) {
422 VMSTATE_UINT64(env.steal_time_msr, X86CPU),
423 VMSTATE_END_OF_LIST()
424 }
425};
426
427static const VMStateDescription vmstate_async_pf_msr = {
428 .name = "cpu/async_pf_msr",
429 .version_id = 1,
430 .minimum_version_id = 1,
431 .needed = async_pf_msr_needed,
432 .fields = (VMStateField[]) {
433 VMSTATE_UINT64(env.async_pf_en_msr, X86CPU),
434 VMSTATE_END_OF_LIST()
435 }
436};
437
438static const VMStateDescription vmstate_pv_eoi_msr = {
439 .name = "cpu/async_pv_eoi_msr",
440 .version_id = 1,
441 .minimum_version_id = 1,
442 .needed = pv_eoi_msr_needed,
443 .fields = (VMStateField[]) {
444 VMSTATE_UINT64(env.pv_eoi_en_msr, X86CPU),
445 VMSTATE_END_OF_LIST()
446 }
447};
448
449static bool fpop_ip_dp_needed(void *opaque)
450{
451 X86CPU *cpu = opaque;
452 CPUX86State *env = &cpu->env;
453
454 return env->fpop != 0 || env->fpip != 0 || env->fpdp != 0;
455}
456
457static const VMStateDescription vmstate_fpop_ip_dp = {
458 .name = "cpu/fpop_ip_dp",
459 .version_id = 1,
460 .minimum_version_id = 1,
461 .needed = fpop_ip_dp_needed,
462 .fields = (VMStateField[]) {
463 VMSTATE_UINT16(env.fpop, X86CPU),
464 VMSTATE_UINT64(env.fpip, X86CPU),
465 VMSTATE_UINT64(env.fpdp, X86CPU),
466 VMSTATE_END_OF_LIST()
467 }
468};
469
470static bool tsc_adjust_needed(void *opaque)
471{
472 X86CPU *cpu = opaque;
473 CPUX86State *env = &cpu->env;
474
475 return env->tsc_adjust != 0;
476}
477
478static const VMStateDescription vmstate_msr_tsc_adjust = {
479 .name = "cpu/msr_tsc_adjust",
480 .version_id = 1,
481 .minimum_version_id = 1,
482 .needed = tsc_adjust_needed,
483 .fields = (VMStateField[]) {
484 VMSTATE_UINT64(env.tsc_adjust, X86CPU),
485 VMSTATE_END_OF_LIST()
486 }
487};
488
489static bool tscdeadline_needed(void *opaque)
490{
491 X86CPU *cpu = opaque;
492 CPUX86State *env = &cpu->env;
493
494 return env->tsc_deadline != 0;
495}
496
497static const VMStateDescription vmstate_msr_tscdeadline = {
498 .name = "cpu/msr_tscdeadline",
499 .version_id = 1,
500 .minimum_version_id = 1,
501 .needed = tscdeadline_needed,
502 .fields = (VMStateField[]) {
503 VMSTATE_UINT64(env.tsc_deadline, X86CPU),
504 VMSTATE_END_OF_LIST()
505 }
506};
507
508static bool misc_enable_needed(void *opaque)
509{
510 X86CPU *cpu = opaque;
511 CPUX86State *env = &cpu->env;
512
513 return env->msr_ia32_misc_enable != MSR_IA32_MISC_ENABLE_DEFAULT;
514}
515
516static bool feature_control_needed(void *opaque)
517{
518 X86CPU *cpu = opaque;
519 CPUX86State *env = &cpu->env;
520
521 return env->msr_ia32_feature_control != 0;
522}
523
524static const VMStateDescription vmstate_msr_ia32_misc_enable = {
525 .name = "cpu/msr_ia32_misc_enable",
526 .version_id = 1,
527 .minimum_version_id = 1,
528 .needed = misc_enable_needed,
529 .fields = (VMStateField[]) {
530 VMSTATE_UINT64(env.msr_ia32_misc_enable, X86CPU),
531 VMSTATE_END_OF_LIST()
532 }
533};
534
535static const VMStateDescription vmstate_msr_ia32_feature_control = {
536 .name = "cpu/msr_ia32_feature_control",
537 .version_id = 1,
538 .minimum_version_id = 1,
539 .needed = feature_control_needed,
540 .fields = (VMStateField[]) {
541 VMSTATE_UINT64(env.msr_ia32_feature_control, X86CPU),
542 VMSTATE_END_OF_LIST()
543 }
544};
545
546static bool pmu_enable_needed(void *opaque)
547{
548 X86CPU *cpu = opaque;
549 CPUX86State *env = &cpu->env;
550 int i;
551
552 if (env->msr_fixed_ctr_ctrl || env->msr_global_ctrl ||
553 env->msr_global_status || env->msr_global_ovf_ctrl) {
554 return true;
555 }
556 for (i = 0; i < MAX_FIXED_COUNTERS; i++) {
557 if (env->msr_fixed_counters[i]) {
558 return true;
559 }
560 }
561 for (i = 0; i < MAX_GP_COUNTERS; i++) {
562 if (env->msr_gp_counters[i] || env->msr_gp_evtsel[i]) {
563 return true;
564 }
565 }
566
567 return false;
568}
569
570static const VMStateDescription vmstate_msr_architectural_pmu = {
571 .name = "cpu/msr_architectural_pmu",
572 .version_id = 1,
573 .minimum_version_id = 1,
574 .needed = pmu_enable_needed,
575 .fields = (VMStateField[]) {
576 VMSTATE_UINT64(env.msr_fixed_ctr_ctrl, X86CPU),
577 VMSTATE_UINT64(env.msr_global_ctrl, X86CPU),
578 VMSTATE_UINT64(env.msr_global_status, X86CPU),
579 VMSTATE_UINT64(env.msr_global_ovf_ctrl, X86CPU),
580 VMSTATE_UINT64_ARRAY(env.msr_fixed_counters, X86CPU, MAX_FIXED_COUNTERS),
581 VMSTATE_UINT64_ARRAY(env.msr_gp_counters, X86CPU, MAX_GP_COUNTERS),
582 VMSTATE_UINT64_ARRAY(env.msr_gp_evtsel, X86CPU, MAX_GP_COUNTERS),
583 VMSTATE_END_OF_LIST()
584 }
585};
586
587static bool mpx_needed(void *opaque)
588{
589 X86CPU *cpu = opaque;
590 CPUX86State *env = &cpu->env;
591 unsigned int i;
592
593 for (i = 0; i < 4; i++) {
594 if (env->bnd_regs[i].lb || env->bnd_regs[i].ub) {
595 return true;
596 }
597 }
598
599 if (env->bndcs_regs.cfgu || env->bndcs_regs.sts) {
600 return true;
601 }
602
603 return !!env->msr_bndcfgs;
604}
605
606static const VMStateDescription vmstate_mpx = {
607 .name = "cpu/mpx",
608 .version_id = 1,
609 .minimum_version_id = 1,
610 .needed = mpx_needed,
611 .fields = (VMStateField[]) {
612 VMSTATE_BND_REGS(env.bnd_regs, X86CPU, 4),
613 VMSTATE_UINT64(env.bndcs_regs.cfgu, X86CPU),
614 VMSTATE_UINT64(env.bndcs_regs.sts, X86CPU),
615 VMSTATE_UINT64(env.msr_bndcfgs, X86CPU),
616 VMSTATE_END_OF_LIST()
617 }
618};
619
620static bool hyperv_hypercall_enable_needed(void *opaque)
621{
622 X86CPU *cpu = opaque;
623 CPUX86State *env = &cpu->env;
624
625 return env->msr_hv_hypercall != 0 || env->msr_hv_guest_os_id != 0;
626}
627
628static const VMStateDescription vmstate_msr_hypercall_hypercall = {
629 .name = "cpu/msr_hyperv_hypercall",
630 .version_id = 1,
631 .minimum_version_id = 1,
632 .needed = hyperv_hypercall_enable_needed,
633 .fields = (VMStateField[]) {
634 VMSTATE_UINT64(env.msr_hv_guest_os_id, X86CPU),
635 VMSTATE_UINT64(env.msr_hv_hypercall, X86CPU),
636 VMSTATE_END_OF_LIST()
637 }
638};
639
640static bool hyperv_vapic_enable_needed(void *opaque)
641{
642 X86CPU *cpu = opaque;
643 CPUX86State *env = &cpu->env;
644
645 return env->msr_hv_vapic != 0;
646}
647
648static const VMStateDescription vmstate_msr_hyperv_vapic = {
649 .name = "cpu/msr_hyperv_vapic",
650 .version_id = 1,
651 .minimum_version_id = 1,
652 .needed = hyperv_vapic_enable_needed,
653 .fields = (VMStateField[]) {
654 VMSTATE_UINT64(env.msr_hv_vapic, X86CPU),
655 VMSTATE_END_OF_LIST()
656 }
657};
658
659static bool hyperv_time_enable_needed(void *opaque)
660{
661 X86CPU *cpu = opaque;
662 CPUX86State *env = &cpu->env;
663
664 return env->msr_hv_tsc != 0;
665}
666
667static const VMStateDescription vmstate_msr_hyperv_time = {
668 .name = "cpu/msr_hyperv_time",
669 .version_id = 1,
670 .minimum_version_id = 1,
671 .needed = hyperv_time_enable_needed,
672 .fields = (VMStateField[]) {
673 VMSTATE_UINT64(env.msr_hv_tsc, X86CPU),
674 VMSTATE_END_OF_LIST()
675 }
676};
677
678static bool hyperv_crash_enable_needed(void *opaque)
679{
680 X86CPU *cpu = opaque;
681 CPUX86State *env = &cpu->env;
682 int i;
683
684 for (i = 0; i < HV_X64_MSR_CRASH_PARAMS; i++) {
685 if (env->msr_hv_crash_params[i]) {
686 return true;
687 }
688 }
689 return false;
690}
691
692static const VMStateDescription vmstate_msr_hyperv_crash = {
693 .name = "cpu/msr_hyperv_crash",
694 .version_id = 1,
695 .minimum_version_id = 1,
696 .needed = hyperv_crash_enable_needed,
697 .fields = (VMStateField[]) {
698 VMSTATE_UINT64_ARRAY(env.msr_hv_crash_params,
699 X86CPU, HV_X64_MSR_CRASH_PARAMS),
700 VMSTATE_END_OF_LIST()
701 }
702};
703
704static bool hyperv_runtime_enable_needed(void *opaque)
705{
706 X86CPU *cpu = opaque;
707 CPUX86State *env = &cpu->env;
708
709 return env->msr_hv_runtime != 0;
710}
711
712static const VMStateDescription vmstate_msr_hyperv_runtime = {
713 .name = "cpu/msr_hyperv_runtime",
714 .version_id = 1,
715 .minimum_version_id = 1,
716 .needed = hyperv_runtime_enable_needed,
717 .fields = (VMStateField[]) {
718 VMSTATE_UINT64(env.msr_hv_runtime, X86CPU),
719 VMSTATE_END_OF_LIST()
720 }
721};
722
723static bool hyperv_synic_enable_needed(void *opaque)
724{
725 X86CPU *cpu = opaque;
726 CPUX86State *env = &cpu->env;
727 int i;
728
729 if (env->msr_hv_synic_control != 0 ||
730 env->msr_hv_synic_evt_page != 0 ||
731 env->msr_hv_synic_msg_page != 0) {
732 return true;
733 }
734
735 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
736 if (env->msr_hv_synic_sint[i] != 0) {
737 return true;
738 }
739 }
740
741 return false;
742}
743
744static const VMStateDescription vmstate_msr_hyperv_synic = {
745 .name = "cpu/msr_hyperv_synic",
746 .version_id = 1,
747 .minimum_version_id = 1,
748 .needed = hyperv_synic_enable_needed,
749 .fields = (VMStateField[]) {
750 VMSTATE_UINT64(env.msr_hv_synic_control, X86CPU),
751 VMSTATE_UINT64(env.msr_hv_synic_evt_page, X86CPU),
752 VMSTATE_UINT64(env.msr_hv_synic_msg_page, X86CPU),
753 VMSTATE_UINT64_ARRAY(env.msr_hv_synic_sint, X86CPU,
754 HV_SYNIC_SINT_COUNT),
755 VMSTATE_END_OF_LIST()
756 }
757};
758
759static bool hyperv_stimer_enable_needed(void *opaque)
760{
761 X86CPU *cpu = opaque;
762 CPUX86State *env = &cpu->env;
763 int i;
764
765 for (i = 0; i < ARRAY_SIZE(env->msr_hv_stimer_config); i++) {
766 if (env->msr_hv_stimer_config[i] || env->msr_hv_stimer_count[i]) {
767 return true;
768 }
769 }
770 return false;
771}
772
773static const VMStateDescription vmstate_msr_hyperv_stimer = {
774 .name = "cpu/msr_hyperv_stimer",
775 .version_id = 1,
776 .minimum_version_id = 1,
777 .needed = hyperv_stimer_enable_needed,
778 .fields = (VMStateField[]) {
779 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_config,
780 X86CPU, HV_SYNIC_STIMER_COUNT),
781 VMSTATE_UINT64_ARRAY(env.msr_hv_stimer_count,
782 X86CPU, HV_SYNIC_STIMER_COUNT),
783 VMSTATE_END_OF_LIST()
784 }
785};
786
787static bool avx512_needed(void *opaque)
788{
789 X86CPU *cpu = opaque;
790 CPUX86State *env = &cpu->env;
791 unsigned int i;
792
793 for (i = 0; i < NB_OPMASK_REGS; i++) {
794 if (env->opmask_regs[i]) {
795 return true;
796 }
797 }
798
799 for (i = 0; i < CPU_NB_REGS; i++) {
800#define ENV_XMM(reg, field) (env->xmm_regs[reg].ZMM_Q(field))
801 if (ENV_XMM(i, 4) || ENV_XMM(i, 6) ||
802 ENV_XMM(i, 5) || ENV_XMM(i, 7)) {
803 return true;
804 }
805#ifdef TARGET_X86_64
806 if (ENV_XMM(i+16, 0) || ENV_XMM(i+16, 1) ||
807 ENV_XMM(i+16, 2) || ENV_XMM(i+16, 3) ||
808 ENV_XMM(i+16, 4) || ENV_XMM(i+16, 5) ||
809 ENV_XMM(i+16, 6) || ENV_XMM(i+16, 7)) {
810 return true;
811 }
812#endif
813 }
814
815 return false;
816}
817
818static const VMStateDescription vmstate_avx512 = {
819 .name = "cpu/avx512",
820 .version_id = 1,
821 .minimum_version_id = 1,
822 .needed = avx512_needed,
823 .fields = (VMStateField[]) {
824 VMSTATE_UINT64_ARRAY(env.opmask_regs, X86CPU, NB_OPMASK_REGS),
825 VMSTATE_ZMMH_REGS_VARS(env.xmm_regs, X86CPU, 0),
826#ifdef TARGET_X86_64
827 VMSTATE_Hi16_ZMM_REGS_VARS(env.xmm_regs, X86CPU, 16),
828#endif
829 VMSTATE_END_OF_LIST()
830 }
831};
832
833static bool xss_needed(void *opaque)
834{
835 X86CPU *cpu = opaque;
836 CPUX86State *env = &cpu->env;
837
838 return env->xss != 0;
839}
840
841static const VMStateDescription vmstate_xss = {
842 .name = "cpu/xss",
843 .version_id = 1,
844 .minimum_version_id = 1,
845 .needed = xss_needed,
846 .fields = (VMStateField[]) {
847 VMSTATE_UINT64(env.xss, X86CPU),
848 VMSTATE_END_OF_LIST()
849 }
850};
851
852#ifdef TARGET_X86_64
853static bool pkru_needed(void *opaque)
854{
855 X86CPU *cpu = opaque;
856 CPUX86State *env = &cpu->env;
857
858 return env->pkru != 0;
859}
860
861static const VMStateDescription vmstate_pkru = {
862 .name = "cpu/pkru",
863 .version_id = 1,
864 .minimum_version_id = 1,
865 .needed = pkru_needed,
866 .fields = (VMStateField[]){
867 VMSTATE_UINT32(env.pkru, X86CPU),
868 VMSTATE_END_OF_LIST()
869 }
870};
871#endif
872
873static bool tsc_khz_needed(void *opaque)
874{
875 X86CPU *cpu = opaque;
876 CPUX86State *env = &cpu->env;
877 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
878 PCMachineClass *pcmc = PC_MACHINE_CLASS(mc);
879 return env->tsc_khz && pcmc->save_tsc_khz;
880}
881
882static const VMStateDescription vmstate_tsc_khz = {
883 .name = "cpu/tsc_khz",
884 .version_id = 1,
885 .minimum_version_id = 1,
886 .needed = tsc_khz_needed,
887 .fields = (VMStateField[]) {
888 VMSTATE_INT64(env.tsc_khz, X86CPU),
889 VMSTATE_END_OF_LIST()
890 }
891};
892
893VMStateDescription vmstate_x86_cpu = {
894 .name = "cpu",
895 .version_id = 12,
896 .minimum_version_id = 3,
897 .pre_save = cpu_pre_save,
898 .post_load = cpu_post_load,
899 .fields = (VMStateField[]) {
900 VMSTATE_UINTTL_ARRAY(env.regs, X86CPU, CPU_NB_REGS),
901 VMSTATE_UINTTL(env.eip, X86CPU),
902 VMSTATE_UINTTL(env.eflags, X86CPU),
903 VMSTATE_UINT32(env.hflags, X86CPU),
904
905 VMSTATE_UINT16(env.fpuc, X86CPU),
906 VMSTATE_UINT16(env.fpus_vmstate, X86CPU),
907 VMSTATE_UINT16(env.fptag_vmstate, X86CPU),
908 VMSTATE_UINT16(env.fpregs_format_vmstate, X86CPU),
909 VMSTATE_FP_REGS(env.fpregs, X86CPU, 8),
910
911 VMSTATE_SEGMENT_ARRAY(env.segs, X86CPU, 6),
912 VMSTATE_SEGMENT(env.ldt, X86CPU),
913 VMSTATE_SEGMENT(env.tr, X86CPU),
914 VMSTATE_SEGMENT(env.gdt, X86CPU),
915 VMSTATE_SEGMENT(env.idt, X86CPU),
916
917 VMSTATE_UINT32(env.sysenter_cs, X86CPU),
918#ifdef TARGET_X86_64
919
920 VMSTATE_HACK_UINT32(env.sysenter_esp, X86CPU, less_than_7),
921 VMSTATE_HACK_UINT32(env.sysenter_eip, X86CPU, less_than_7),
922 VMSTATE_UINTTL_V(env.sysenter_esp, X86CPU, 7),
923 VMSTATE_UINTTL_V(env.sysenter_eip, X86CPU, 7),
924#else
925 VMSTATE_UINTTL(env.sysenter_esp, X86CPU),
926 VMSTATE_UINTTL(env.sysenter_eip, X86CPU),
927#endif
928
929 VMSTATE_UINTTL(env.cr[0], X86CPU),
930 VMSTATE_UINTTL(env.cr[2], X86CPU),
931 VMSTATE_UINTTL(env.cr[3], X86CPU),
932 VMSTATE_UINTTL(env.cr[4], X86CPU),
933 VMSTATE_UINTTL_ARRAY(env.dr, X86CPU, 8),
934
935 VMSTATE_INT32(env.a20_mask, X86CPU),
936
937 VMSTATE_UINT32(env.mxcsr, X86CPU),
938 VMSTATE_XMM_REGS(env.xmm_regs, X86CPU, 0),
939
940#ifdef TARGET_X86_64
941 VMSTATE_UINT64(env.efer, X86CPU),
942 VMSTATE_UINT64(env.star, X86CPU),
943 VMSTATE_UINT64(env.lstar, X86CPU),
944 VMSTATE_UINT64(env.cstar, X86CPU),
945 VMSTATE_UINT64(env.fmask, X86CPU),
946 VMSTATE_UINT64(env.kernelgsbase, X86CPU),
947#endif
948 VMSTATE_UINT32_V(env.smbase, X86CPU, 4),
949
950 VMSTATE_UINT64_V(env.pat, X86CPU, 5),
951 VMSTATE_UINT32_V(env.hflags2, X86CPU, 5),
952
953 VMSTATE_UINT32_TEST(parent_obj.halted, X86CPU, version_is_5),
954 VMSTATE_UINT64_V(env.vm_hsave, X86CPU, 5),
955 VMSTATE_UINT64_V(env.vm_vmcb, X86CPU, 5),
956 VMSTATE_UINT64_V(env.tsc_offset, X86CPU, 5),
957 VMSTATE_UINT64_V(env.intercept, X86CPU, 5),
958 VMSTATE_UINT16_V(env.intercept_cr_read, X86CPU, 5),
959 VMSTATE_UINT16_V(env.intercept_cr_write, X86CPU, 5),
960 VMSTATE_UINT16_V(env.intercept_dr_read, X86CPU, 5),
961 VMSTATE_UINT16_V(env.intercept_dr_write, X86CPU, 5),
962 VMSTATE_UINT32_V(env.intercept_exceptions, X86CPU, 5),
963 VMSTATE_UINT8_V(env.v_tpr, X86CPU, 5),
964
965 VMSTATE_UINT64_ARRAY_V(env.mtrr_fixed, X86CPU, 11, 8),
966 VMSTATE_UINT64_V(env.mtrr_deftype, X86CPU, 8),
967 VMSTATE_MTRR_VARS(env.mtrr_var, X86CPU, MSR_MTRRcap_VCNT, 8),
968
969 VMSTATE_INT32_V(env.interrupt_injected, X86CPU, 9),
970 VMSTATE_UINT32_V(env.mp_state, X86CPU, 9),
971 VMSTATE_UINT64_V(env.tsc, X86CPU, 9),
972 VMSTATE_INT32_V(env.exception_injected, X86CPU, 11),
973 VMSTATE_UINT8_V(env.soft_interrupt, X86CPU, 11),
974 VMSTATE_UINT8_V(env.nmi_injected, X86CPU, 11),
975 VMSTATE_UINT8_V(env.nmi_pending, X86CPU, 11),
976 VMSTATE_UINT8_V(env.has_error_code, X86CPU, 11),
977 VMSTATE_UINT32_V(env.sipi_vector, X86CPU, 11),
978
979 VMSTATE_UINT64_V(env.mcg_cap, X86CPU, 10),
980 VMSTATE_UINT64_V(env.mcg_status, X86CPU, 10),
981 VMSTATE_UINT64_V(env.mcg_ctl, X86CPU, 10),
982 VMSTATE_UINT64_ARRAY_V(env.mce_banks, X86CPU, MCE_BANKS_DEF * 4, 10),
983
984 VMSTATE_UINT64_V(env.tsc_aux, X86CPU, 11),
985
986 VMSTATE_UINT64_V(env.system_time_msr, X86CPU, 11),
987 VMSTATE_UINT64_V(env.wall_clock_msr, X86CPU, 11),
988
989 VMSTATE_UINT64_V(env.xcr0, X86CPU, 12),
990 VMSTATE_UINT64_V(env.xstate_bv, X86CPU, 12),
991 VMSTATE_YMMH_REGS_VARS(env.xmm_regs, X86CPU, 0, 12),
992 VMSTATE_END_OF_LIST()
993
994 },
995 .subsections = (const VMStateDescription*[]) {
996 &vmstate_async_pf_msr,
997 &vmstate_pv_eoi_msr,
998 &vmstate_steal_time_msr,
999 &vmstate_fpop_ip_dp,
1000 &vmstate_msr_tsc_adjust,
1001 &vmstate_msr_tscdeadline,
1002 &vmstate_msr_ia32_misc_enable,
1003 &vmstate_msr_ia32_feature_control,
1004 &vmstate_msr_architectural_pmu,
1005 &vmstate_mpx,
1006 &vmstate_msr_hypercall_hypercall,
1007 &vmstate_msr_hyperv_vapic,
1008 &vmstate_msr_hyperv_time,
1009 &vmstate_msr_hyperv_crash,
1010 &vmstate_msr_hyperv_runtime,
1011 &vmstate_msr_hyperv_synic,
1012 &vmstate_msr_hyperv_stimer,
1013 &vmstate_avx512,
1014 &vmstate_xss,
1015 &vmstate_tsc_khz,
1016#ifdef TARGET_X86_64
1017 &vmstate_pkru,
1018#endif
1019 NULL
1020 }
1021};
1022
