LXR qemu/target-lm32/cpu-qom.h

   1/*
   2 * QEMU LatticeMico32 CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_LM32_CPU_QOM_H
  21#define QEMU_LM32_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24#include "cpu.h"
  25
  26#define TYPE_LM32_CPU "lm32-cpu"
  27
  28#define LM32_CPU_CLASS(klass) \
  29    OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
  30#define LM32_CPU(obj) \
  31    OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
  32#define LM32_CPU_GET_CLASS(obj) \
  33    OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
  34
  35/**
  36 * LM32CPUClass:
  37 * @parent_realize: The parent class' realize handler.
  38 * @parent_reset: The parent class' reset handler.
  39 *
  40 * A LatticeMico32 CPU model.
  41 */
  42typedef struct LM32CPUClass {
  43    /*< private >*/
  44    CPUClass parent_class;
  45    /*< public >*/
  46
  47    DeviceRealize parent_realize;
  48    void (*parent_reset)(CPUState *cpu);
  49} LM32CPUClass;
  50
  51/**
  52 * LM32CPU:
  53 * @env: #CPULM32State
  54 *
  55 * A LatticeMico32 CPU.
  56 */
  57typedef struct LM32CPU {
  58    /*< private >*/
  59    CPUState parent_obj;
  60    /*< public >*/
  61
  62    CPULM32State env;
  63
  64    uint32_t revision;
  65    uint8_t num_interrupts;
  66    uint8_t num_breakpoints;
  67    uint8_t num_watchpoints;
  68    uint32_t features;
  69} LM32CPU;
  70
  71static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
  72{
  73    return container_of(env, LM32CPU, env);
  74}
  75
  76#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e))
  77
  78#define ENV_OFFSET offsetof(LM32CPU, env)
  79
  80#ifndef CONFIG_USER_ONLY
  81extern const struct VMStateDescription vmstate_lm32_cpu;
  82#endif
  83
  84void lm32_cpu_do_interrupt(CPUState *cpu);
  85bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req);
  86void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  87                         int flags);
  88hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  89int lm32_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
  90int lm32_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  91
  92#endif
  93