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20#include "qemu/osdep.h"
21#include "cpu.h"
22#include "qemu/host-utils.h"
23#include "sysemu/sysemu.h"
24#include "exec/semihost.h"
25#include "exec/log.h"
26
27int lm32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
28 int mmu_idx)
29{
30 LM32CPU *cpu = LM32_CPU(cs);
31 CPULM32State *env = &cpu->env;
32 int prot;
33
34 address &= TARGET_PAGE_MASK;
35 prot = PAGE_BITS;
36 if (env->flags & LM32_FLAG_IGNORE_MSB) {
37 tlb_set_page(cs, address, address & 0x7fffffff, prot, mmu_idx,
38 TARGET_PAGE_SIZE);
39 } else {
40 tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
41 }
42
43 return 0;
44}
45
46hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
47{
48 LM32CPU *cpu = LM32_CPU(cs);
49
50 addr &= TARGET_PAGE_MASK;
51 if (cpu->env.flags & LM32_FLAG_IGNORE_MSB) {
52 return addr & 0x7fffffff;
53 } else {
54 return addr;
55 }
56}
57
58void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
59{
60 LM32CPU *cpu = lm32_env_get_cpu(env);
61
62 cpu_breakpoint_insert(CPU(cpu), address, BP_CPU,
63 &env->cpu_breakpoint[idx]);
64}
65
66void lm32_breakpoint_remove(CPULM32State *env, int idx)
67{
68 LM32CPU *cpu = lm32_env_get_cpu(env);
69
70 if (!env->cpu_breakpoint[idx]) {
71 return;
72 }
73
74 cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[idx]);
75 env->cpu_breakpoint[idx] = NULL;
76}
77
78void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
79 lm32_wp_t wp_type)
80{
81 LM32CPU *cpu = lm32_env_get_cpu(env);
82 int flags = 0;
83
84 switch (wp_type) {
85 case LM32_WP_DISABLED:
86
87 break;
88 case LM32_WP_READ:
89 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
90 break;
91 case LM32_WP_WRITE:
92 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
93 break;
94 case LM32_WP_READ_WRITE:
95 flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
96 break;
97 }
98
99 if (flags != 0) {
100 cpu_watchpoint_insert(CPU(cpu), address, 1, flags,
101 &env->cpu_watchpoint[idx]);
102 }
103}
104
105void lm32_watchpoint_remove(CPULM32State *env, int idx)
106{
107 LM32CPU *cpu = lm32_env_get_cpu(env);
108
109 if (!env->cpu_watchpoint[idx]) {
110 return;
111 }
112
113 cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[idx]);
114 env->cpu_watchpoint[idx] = NULL;
115}
116
117static bool check_watchpoints(CPULM32State *env)
118{
119 LM32CPU *cpu = lm32_env_get_cpu(env);
120 int i;
121
122 for (i = 0; i < cpu->num_watchpoints; i++) {
123 if (env->cpu_watchpoint[i] &&
124 env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
125 return true;
126 }
127 }
128 return false;
129}
130
131void lm32_debug_excp_handler(CPUState *cs)
132{
133 LM32CPU *cpu = LM32_CPU(cs);
134 CPULM32State *env = &cpu->env;
135 CPUBreakpoint *bp;
136
137 if (cs->watchpoint_hit) {
138 if (cs->watchpoint_hit->flags & BP_CPU) {
139 cs->watchpoint_hit = NULL;
140 if (check_watchpoints(env)) {
141 raise_exception(env, EXCP_WATCHPOINT);
142 } else {
143 cpu_resume_from_signal(cs, NULL);
144 }
145 }
146 } else {
147 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
148 if (bp->pc == env->pc) {
149 if (bp->flags & BP_CPU) {
150 raise_exception(env, EXCP_BREAKPOINT);
151 }
152 break;
153 }
154 }
155 }
156}
157
158void lm32_cpu_do_interrupt(CPUState *cs)
159{
160 LM32CPU *cpu = LM32_CPU(cs);
161 CPULM32State *env = &cpu->env;
162
163 qemu_log_mask(CPU_LOG_INT,
164 "exception at pc=%x type=%x\n", env->pc, cs->exception_index);
165
166 switch (cs->exception_index) {
167 case EXCP_SYSTEMCALL:
168 if (unlikely(semihosting_enabled())) {
169
170
171 if (lm32_cpu_do_semihosting(cs)) {
172 env->pc += 4;
173 break;
174 }
175 }
176
177 case EXCP_INSN_BUS_ERROR:
178 case EXCP_DATA_BUS_ERROR:
179 case EXCP_DIVIDE_BY_ZERO:
180 case EXCP_IRQ:
181
182 env->regs[R_EA] = env->pc;
183 env->ie |= (env->ie & IE_IE) ? IE_EIE : 0;
184 env->ie &= ~IE_IE;
185 if (env->dc & DC_RE) {
186 env->pc = env->deba + (cs->exception_index * 32);
187 } else {
188 env->pc = env->eba + (cs->exception_index * 32);
189 }
190 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
191 break;
192 case EXCP_BREAKPOINT:
193 case EXCP_WATCHPOINT:
194
195 env->regs[R_BA] = env->pc;
196 env->ie |= (env->ie & IE_IE) ? IE_BIE : 0;
197 env->ie &= ~IE_IE;
198 env->pc = env->deba + (cs->exception_index * 32);
199 log_cpu_state_mask(CPU_LOG_INT, cs, 0);
200 break;
201 default:
202 cpu_abort(cs, "unhandled exception type=%d\n",
203 cs->exception_index);
204 break;
205 }
206}
207
208bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
209{
210 LM32CPU *cpu = LM32_CPU(cs);
211 CPULM32State *env = &cpu->env;
212
213 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) {
214 cs->exception_index = EXCP_IRQ;
215 lm32_cpu_do_interrupt(cs);
216 return true;
217 }
218 return false;
219}
220
221LM32CPU *cpu_lm32_init(const char *cpu_model)
222{
223 return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model));
224}
225
226
227
228
229void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value)
230{
231 if (value) {
232 env->flags |= LM32_FLAG_IGNORE_MSB;
233 } else {
234 env->flags &= ~LM32_FLAG_IGNORE_MSB;
235 }
236}
237