LXR qemu/target-microblaze/helper.c

   1/*
   2 *  MicroBlaze helper routines.
   3 *
   4 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>
   5 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "qemu/host-utils.h"
  24#include "exec/log.h"
  25
  26#define D(x)
  27
  28#if defined(CONFIG_USER_ONLY)
  29
  30void mb_cpu_do_interrupt(CPUState *cs)
  31{
  32    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  33    CPUMBState *env = &cpu->env;
  34
  35    cs->exception_index = -1;
  36    env->res_addr = RES_ADDR_NONE;
  37    env->regs[14] = env->sregs[SR_PC];
  38}
  39
  40int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  41                            int mmu_idx)
  42{
  43    cs->exception_index = 0xaa;
  44    cpu_dump_state(cs, stderr, fprintf, 0);
  45    return 1;
  46}
  47
  48#else /* !CONFIG_USER_ONLY */
  49
  50int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
  51                            int mmu_idx)
  52{
  53    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
  54    CPUMBState *env = &cpu->env;
  55    unsigned int hit;
  56    unsigned int mmu_available;
  57    int r = 1;
  58    int prot;
  59
  60    mmu_available = 0;
  61    if (cpu->cfg.use_mmu) {
  62        mmu_available = 1;
  63        if ((cpu->cfg.pvr == C_PVR_FULL) &&
  64            (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) {
  65            mmu_available = 0;
  66        }
  67    }
  68
  69    /* Translate if the MMU is available and enabled.  */
  70    if (mmu_available && (env->sregs[SR_MSR] & MSR_VM)) {
  71        target_ulong vaddr, paddr;
  72        struct microblaze_mmu_lookup lu;
  73
  74        hit = mmu_translate(&env->mmu, &lu, address, rw, mmu_idx);
  75        if (hit) {
  76            vaddr = address & TARGET_PAGE_MASK;
  77            paddr = lu.paddr + vaddr - lu.vaddr;
  78
  79            qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
  80                    mmu_idx, vaddr, paddr, lu.prot);
  81            tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
  82            r = 0;
  83        } else {
  84            env->sregs[SR_EAR] = address;
  85            qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
  86                                        mmu_idx, address);
  87
  88            switch (lu.err) {
  89                case ERR_PROT:
  90                    env->sregs[SR_ESR] = rw == 2 ? 17 : 16;
  91                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  92                    break;
  93                case ERR_MISS:
  94                    env->sregs[SR_ESR] = rw == 2 ? 19 : 18;
  95                    env->sregs[SR_ESR] |= (rw == 1) << 10;
  96                    break;
  97                default:
  98                    abort();
  99                    break;
 100            }
 101
 102            if (cs->exception_index == EXCP_MMU) {
 103                cpu_abort(cs, "recursive faults\n");
 104            }
 105
 106            /* TLB miss.  */
 107            cs->exception_index = EXCP_MMU;
 108        }
 109    } else {
 110        /* MMU disabled or not available.  */
 111        address &= TARGET_PAGE_MASK;
 112        prot = PAGE_BITS;
 113        tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
 114        r = 0;
 115    }
 116    return r;
 117}
 118
 119#include "hw/remote-port.h"
 120
 121void mb_cpu_do_interrupt(CPUState *cs)
 122{
 123    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 124    CPUMBState *env = &cpu->env;
 125    uint32_t t;
 126
 127    /* IMM flag cannot propagate across a branch and into the dslot.  */
 128    assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG)));
 129    assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)));
 130/*    assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions.  */
 131    if (env->res_addr != RES_ADDR_NONE) {
 132        env->res_addr = RES_ADDR_NONE;
 133    }
 134    switch (cs->exception_index) {
 135        case EXCP_HW_EXCP:
 136            if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) {
 137                qemu_log_mask(LOG_GUEST_ERROR, "Exception raised on system without exceptions!\n");
 138                return;
 139            }
 140
 141            env->regs[17] = env->sregs[SR_PC] + 4;
 142            env->sregs[SR_ESR] &= ~(1 << 12);
 143
 144            /* Exception breaks branch + dslot sequence?  */
 145            if (env->iflags & D_FLAG) {
 146                env->sregs[SR_ESR] |= 1 << 12 ;
 147                env->sregs[SR_BTR] = env->btarget;
 148            }
 149
 150            /* Disable the MMU.  */
 151            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 152            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 153            env->sregs[SR_MSR] |= t;
 154            /* Exception in progress.  */
 155            env->sregs[SR_MSR] |= MSR_EIP;
 156
 157            qemu_log_mask(CPU_LOG_INT,
 158                          "hw exception at pc=%x ear=%x esr=%x iflags=%x\n",
 159                          env->sregs[SR_PC], env->sregs[SR_EAR],
 160                          env->sregs[SR_ESR], env->iflags);
 161            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 162            env->iflags &= ~(IMM_FLAG | D_FLAG);
 163            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 164            break;
 165
 166        case EXCP_MMU:
 167            env->regs[17] = env->sregs[SR_PC];
 168
 169            env->sregs[SR_ESR] &= ~(1 << 12);
 170            /* Exception breaks branch + dslot sequence?  */
 171            if (env->iflags & D_FLAG) {
 172                D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
 173                env->sregs[SR_ESR] |= 1 << 12 ;
 174                env->sregs[SR_BTR] = env->btarget;
 175
 176                /* Reexecute the branch.  */
 177                env->regs[17] -= 4;
 178                /* was the branch immprefixed?.  */
 179                if (env->bimm) {
 180                    qemu_log_mask(CPU_LOG_INT,
 181                                  "bimm exception at pc=%x iflags=%x\n",
 182                                  env->sregs[SR_PC], env->iflags);
 183                    env->regs[17] -= 4;
 184                    log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 185                }
 186            } else if (env->iflags & IMM_FLAG) {
 187                D(qemu_log("IMM_FLAG set at exception\n"));
 188                env->regs[17] -= 4;
 189            }
 190
 191            /* Disable the MMU.  */
 192            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 193            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 194            env->sregs[SR_MSR] |= t;
 195            /* Exception in progress.  */
 196            env->sregs[SR_MSR] |= MSR_EIP;
 197
 198            qemu_log_mask(CPU_LOG_INT,
 199                          "exception at pc=%x ear=%x iflags=%x\n",
 200                          env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
 201            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 202            env->iflags &= ~(IMM_FLAG | D_FLAG);
 203            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
 204            break;
 205
 206        case EXCP_IRQ:
 207            assert(!(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)));
 208            assert(env->sregs[SR_MSR] & MSR_IE);
 209            assert(!(env->iflags & D_FLAG));
 210
 211            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 212
 213#if 0
 214#include "disas/disas.h"
 215
 216/* Useful instrumentation when debugging interrupt issues in either
 217   the models or in sw.  */
 218            {
 219                const char *sym;
 220
 221                sym = lookup_symbol(env->sregs[SR_PC]);
 222                if (sym
 223                    && (!strcmp("netif_rx", sym)
 224                        || !strcmp("process_backlog", sym))) {
 225
 226                    qemu_log(
 227                         "interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
 228                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
 229                         sym);
 230
 231                    log_cpu_state(cs, 0);
 232                }
 233            }
 234#endif
 235            qemu_log_mask(CPU_LOG_INT,
 236                         "interrupt at pc=%x msr=%x %x iflags=%x\n",
 237                         env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 238
 239            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
 240                                    | MSR_UM | MSR_IE);
 241            env->sregs[SR_MSR] |= t;
 242
 243            env->regs[14] = env->sregs[SR_PC];
 244            env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
 245            //log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 246            break;
 247
 248        case EXCP_BREAK:
 249        case EXCP_HW_BREAK:
 250            assert(!(env->iflags & IMM_FLAG));
 251            assert(!(env->iflags & D_FLAG));
 252            t = (env->sregs[SR_MSR] & (MSR_VM | MSR_UM)) << 1;
 253            qemu_log_mask(CPU_LOG_INT,
 254                        "break at pc=%x msr=%x %x iflags=%x\n",
 255                        env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
 256            log_cpu_state_mask(CPU_LOG_INT, cs, 0);
 257            env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
 258            env->sregs[SR_MSR] |= t;
 259            env->sregs[SR_MSR] |= MSR_BIP;
 260            if (cs->exception_index == EXCP_HW_BREAK) {
 261                env->regs[16] = env->sregs[SR_PC];
 262                env->sregs[SR_MSR] |= MSR_BIP;
 263                env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
 264            } else
 265                env->sregs[SR_PC] = env->btarget;
 266            break;
 267        default:
 268            cpu_abort(cs, "unhandled exception type=%d\n",
 269                      cs->exception_index);
 270            break;
 271    }
 272}
 273
 274hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 275{
 276    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 277    CPUMBState *env = &cpu->env;
 278    target_ulong vaddr, paddr = 0;
 279    struct microblaze_mmu_lookup lu;
 280    unsigned int hit;
 281
 282    if (env->sregs[SR_MSR] & MSR_VM) {
 283        hit = mmu_translate(&env->mmu, &lu, addr, 0, 0);
 284        if (hit) {
 285            vaddr = addr & TARGET_PAGE_MASK;
 286            paddr = lu.paddr + vaddr - lu.vaddr;
 287        } else
 288            paddr = 0; /* ???.  */
 289    } else
 290        paddr = addr & TARGET_PAGE_MASK;
 291
 292    return paddr;
 293}
 294#endif
 295
 296bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 297{
 298    MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
 299    CPUMBState *env = &cpu->env;
 300
 301    if ((interrupt_request & CPU_INTERRUPT_HARD)
 302        && (env->sregs[SR_MSR] & MSR_IE)
 303        && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 304        && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 305        cs->exception_index = EXCP_IRQ;
 306        mb_cpu_do_interrupt(cs);
 307        return true;
 308    }
 309    return false;
 310}
 311