qemu/target-mips/cpu.c
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   1/*
   2 * QEMU MIPS CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "qapi/error.h"
  23#include "cpu.h"
  24#include "kvm_mips.h"
  25#include "qemu-common.h"
  26#include "sysemu/kvm.h"
  27
  28
  29static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  30{
  31    MIPSCPU *cpu = MIPS_CPU(cs);
  32    CPUMIPSState *env = &cpu->env;
  33
  34    env->active_tc.PC = value & ~(target_ulong)1;
  35    if (value & 1) {
  36        env->hflags |= MIPS_HFLAG_M16;
  37    } else {
  38        env->hflags &= ~(MIPS_HFLAG_M16);
  39    }
  40}
  41
  42static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  43{
  44    MIPSCPU *cpu = MIPS_CPU(cs);
  45    CPUMIPSState *env = &cpu->env;
  46
  47    env->active_tc.PC = tb->pc;
  48    env->hflags &= ~MIPS_HFLAG_BMASK;
  49    env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  50}
  51
  52static bool mips_cpu_has_work(CPUState *cs)
  53{
  54    MIPSCPU *cpu = MIPS_CPU(cs);
  55    CPUMIPSState *env = &cpu->env;
  56    bool has_work = false;
  57
  58    /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
  59       interrupts wake-up the CPU, however most of the implementations only
  60       check for interrupts that can be taken. */
  61    if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  62        cpu_mips_hw_interrupts_pending(env)) {
  63        if (cpu_mips_hw_interrupts_enabled(env) ||
  64            (env->insn_flags & ISA_MIPS32R6)) {
  65            has_work = true;
  66        }
  67    }
  68
  69    /* MIPS-MT has the ability to halt the CPU.  */
  70    if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  71        /* The QEMU model will issue an _WAKE request whenever the CPUs
  72           should be woken up.  */
  73        if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  74            has_work = true;
  75        }
  76
  77        if (!mips_vpe_active(env)) {
  78            has_work = false;
  79        }
  80    }
  81    /* MIPS Release 6 has the ability to halt the CPU.  */
  82    if (env->CP0_Config5 & (1 << CP0C5_VP)) {
  83        if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  84            has_work = true;
  85        }
  86        if (!mips_vp_active(env)) {
  87            has_work = false;
  88        }
  89    }
  90    return has_work;
  91}
  92
  93/* CPUClass::reset() */
  94static void mips_cpu_reset(CPUState *s)
  95{
  96    MIPSCPU *cpu = MIPS_CPU(s);
  97    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  98    CPUMIPSState *env = &cpu->env;
  99
 100    mcc->parent_reset(s);
 101
 102    memset(env, 0, offsetof(CPUMIPSState, mvp));
 103    tlb_flush(s, 1);
 104
 105    cpu_state_reset(env);
 106
 107#ifndef CONFIG_USER_ONLY
 108    if (kvm_enabled()) {
 109        kvm_mips_reset_vcpu(cpu);
 110    }
 111#endif
 112}
 113
 114static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
 115#ifdef TARGET_WORDS_BIGENDIAN
 116    info->print_insn = print_insn_big_mips;
 117#else
 118    info->print_insn = print_insn_little_mips;
 119#endif
 120}
 121
 122static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 123{
 124    CPUState *cs = CPU(dev);
 125    MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 126
 127    cpu_reset(cs);
 128    qemu_init_vcpu(cs);
 129
 130    mcc->parent_realize(dev, errp);
 131}
 132
 133static void mips_cpu_initfn(Object *obj)
 134{
 135    CPUState *cs = CPU(obj);
 136    MIPSCPU *cpu = MIPS_CPU(obj);
 137    CPUMIPSState *env = &cpu->env;
 138
 139    cs->env_ptr = env;
 140    cpu_exec_init(cs, &error_abort);
 141
 142    if (tcg_enabled()) {
 143        mips_tcg_init();
 144    }
 145}
 146
 147static void mips_cpu_class_init(ObjectClass *c, void *data)
 148{
 149    MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 150    CPUClass *cc = CPU_CLASS(c);
 151    DeviceClass *dc = DEVICE_CLASS(c);
 152
 153    mcc->parent_realize = dc->realize;
 154    dc->realize = mips_cpu_realizefn;
 155
 156    mcc->parent_reset = cc->reset;
 157    cc->reset = mips_cpu_reset;
 158
 159    cc->has_work = mips_cpu_has_work;
 160    cc->do_interrupt = mips_cpu_do_interrupt;
 161    cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 162    cc->dump_state = mips_cpu_dump_state;
 163    cc->set_pc = mips_cpu_set_pc;
 164    cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 165    cc->gdb_read_register = mips_cpu_gdb_read_register;
 166    cc->gdb_write_register = mips_cpu_gdb_write_register;
 167#ifdef CONFIG_USER_ONLY
 168    cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
 169#else
 170    cc->do_unassigned_access = mips_cpu_unassigned_access;
 171    cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 172    cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 173    cc->vmsd = &vmstate_mips_cpu;
 174#endif
 175    cc->disas_set_info = mips_cpu_disas_set_info;
 176
 177    cc->gdb_num_core_regs = 73;
 178    cc->gdb_stop_before_watchpoint = true;
 179
 180    /*
 181     * Reason: mips_cpu_initfn() calls cpu_exec_init(), which saves
 182     * the object in cpus -> dangling pointer after final
 183     * object_unref().
 184     */
 185    dc->cannot_destroy_with_object_finalize_yet = true;
 186}
 187
 188static const TypeInfo mips_cpu_type_info = {
 189    .name = TYPE_MIPS_CPU,
 190    .parent = TYPE_CPU,
 191    .instance_size = sizeof(MIPSCPU),
 192    .instance_init = mips_cpu_initfn,
 193    .abstract = false,
 194    .class_size = sizeof(MIPSCPUClass),
 195    .class_init = mips_cpu_class_init,
 196};
 197
 198static void mips_cpu_register_types(void)
 199{
 200    type_register_static(&mips_cpu_type_info);
 201}
 202
 203type_init(mips_cpu_register_types)
 204