1/* 2 * OpenRISC interrupt. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20#include "qemu/osdep.h" 21#include "cpu.h" 22#include "qemu-common.h" 23#include "exec/gdbstub.h" 24#include "qemu/host-utils.h" 25#ifndef CONFIG_USER_ONLY 26#include "hw/loader.h" 27#endif 28 29void openrisc_cpu_do_interrupt(CPUState *cs) 30{ 31#ifndef CONFIG_USER_ONLY 32 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 33 CPUOpenRISCState *env = &cpu->env; 34 35 env->epcr = env->pc; 36 if (env->flags & D_FLAG) { 37 env->flags &= ~D_FLAG; 38 env->sr |= SR_DSX; 39 env->epcr -= 4; 40 } 41 if (cs->exception_index == EXCP_SYSCALL) { 42 env->epcr += 4; 43 } 44 45 /* For machine-state changed between user-mode and supervisor mode, 46 we need flush TLB when we enter&exit EXCP. */ 47 tlb_flush(cs, 1); 48 49 env->esr = env->sr; 50 env->sr &= ~SR_DME; 51 env->sr &= ~SR_IME; 52 env->sr |= SR_SM; 53 env->sr &= ~SR_IEE; 54 env->sr &= ~SR_TEE; 55 env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; 56 env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; 57 58 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { 59 env->pc = (cs->exception_index << 8); 60 } else { 61 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 62 } 63#endif 64 65 cs->exception_index = -1; 66} 67 68bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 69{ 70 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 71 CPUOpenRISCState *env = &cpu->env; 72 int idx = -1; 73 74 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { 75 idx = EXCP_INT; 76 } 77 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { 78 idx = EXCP_TICK; 79 } 80 if (idx >= 0) { 81 cs->exception_index = idx; 82 openrisc_cpu_do_interrupt(cs); 83 return true; 84 } 85 return false; 86} 87