LXR qemu/target-openrisc/interrupt

   1/*
   2 * OpenRISC interrupt helper routines
   3 *
   4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
   5 *                         Feng Gao <gf91597@gmail.com>
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "exec/helper-proto.h"
  24
  25void HELPER(rfe)(CPUOpenRISCState *env)
  26{
  27    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
  28    CPUState *cs = CPU(cpu);
  29#ifndef CONFIG_USER_ONLY
  30    int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
  31                         (cpu->env.esr & (SR_SM | SR_IME | SR_DME));
  32#endif
  33    cpu->env.pc = cpu->env.epcr;
  34    cpu->env.npc = cpu->env.epcr;
  35    cpu->env.sr = cpu->env.esr;
  36
  37#ifndef CONFIG_USER_ONLY
  38    if (cpu->env.sr & SR_DME) {
  39        cpu->env.tlb->cpu_openrisc_map_address_data =
  40            &cpu_openrisc_get_phys_data;
  41    } else {
  42        cpu->env.tlb->cpu_openrisc_map_address_data =
  43            &cpu_openrisc_get_phys_nommu;
  44    }
  45
  46    if (cpu->env.sr & SR_IME) {
  47        cpu->env.tlb->cpu_openrisc_map_address_code =
  48            &cpu_openrisc_get_phys_code;
  49    } else {
  50        cpu->env.tlb->cpu_openrisc_map_address_code =
  51            &cpu_openrisc_get_phys_nommu;
  52    }
  53
  54    if (need_flush_tlb) {
  55        tlb_flush(cs, 1);
  56    }
  57#endif
  58    cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
  59}
  60