LXR qemu/target-ppc/misc

   1/*
   2 * Miscellaneous PowerPC emulation helpers for QEMU.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19#include "qemu/osdep.h"
  20#include "cpu.h"
  21#include "exec/helper-proto.h"
  22
  23#include "helper_regs.h"
  24
  25/*****************************************************************************/
  26/* SPR accesses */
  27void helper_load_dump_spr(CPUPPCState *env, uint32_t sprn)
  28{
  29    qemu_log("Read SPR %d %03x => " TARGET_FMT_lx "\n", sprn, sprn,
  30             env->spr[sprn]);
  31}
  32
  33void helper_store_dump_spr(CPUPPCState *env, uint32_t sprn)
  34{
  35    qemu_log("Write SPR %d %03x <= " TARGET_FMT_lx "\n", sprn, sprn,
  36             env->spr[sprn]);
  37}
  38
  39#ifdef TARGET_PPC64
  40static void raise_fu_exception(CPUPPCState *env, uint32_t bit,
  41                               uint32_t sprn, uint32_t cause)
  42{
  43    qemu_log("Facility SPR %d is unavailable (SPR FSCR:%d)\n", sprn, bit);
  44
  45    env->spr[SPR_FSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
  46    cause &= FSCR_IC_MASK;
  47    env->spr[SPR_FSCR] |= (target_ulong)cause << FSCR_IC_POS;
  48
  49    helper_raise_exception_err(env, POWERPC_EXCP_FU, 0);
  50}
  51#endif
  52
  53void helper_fscr_facility_check(CPUPPCState *env, uint32_t bit,
  54                                uint32_t sprn, uint32_t cause)
  55{
  56#ifdef TARGET_PPC64
  57    if (env->spr[SPR_FSCR] & (1ULL << bit)) {
  58        /* Facility is enabled, continue */
  59        return;
  60    }
  61    raise_fu_exception(env, bit, sprn, cause);
  62#endif
  63}
  64
  65void helper_msr_facility_check(CPUPPCState *env, uint32_t bit,
  66                               uint32_t sprn, uint32_t cause)
  67{
  68#ifdef TARGET_PPC64
  69    if (env->msr & (1ULL << bit)) {
  70        /* Facility is enabled, continue */
  71        return;
  72    }
  73    raise_fu_exception(env, bit, sprn, cause);
  74#endif
  75}
  76
  77#if !defined(CONFIG_USER_ONLY)
  78
  79void helper_store_sdr1(CPUPPCState *env, target_ulong val)
  80{
  81    PowerPCCPU *cpu = ppc_env_get_cpu(env);
  82
  83    if (!env->external_htab) {
  84        if (env->spr[SPR_SDR1] != val) {
  85            ppc_store_sdr1(env, val);
  86            tlb_flush(CPU(cpu), 1);
  87        }
  88    }
  89}
  90
  91void helper_store_hid0_601(CPUPPCState *env, target_ulong val)
  92{
  93    target_ulong hid0;
  94
  95    hid0 = env->spr[SPR_HID0];
  96    if ((val ^ hid0) & 0x00000008) {
  97        /* Change current endianness */
  98        env->hflags &= ~(1 << MSR_LE);
  99        env->hflags_nmsr &= ~(1 << MSR_LE);
 100        env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
 101        env->hflags |= env->hflags_nmsr;
 102        qemu_log("%s: set endianness to %c => " TARGET_FMT_lx "\n", __func__,
 103                 val & 0x8 ? 'l' : 'b', env->hflags);
 104    }
 105    env->spr[SPR_HID0] = (uint32_t)val;
 106}
 107
 108void helper_store_403_pbr(CPUPPCState *env, uint32_t num, target_ulong value)
 109{
 110    PowerPCCPU *cpu = ppc_env_get_cpu(env);
 111
 112    if (likely(env->pb[num] != value)) {
 113        env->pb[num] = value;
 114        /* Should be optimized */
 115        tlb_flush(CPU(cpu), 1);
 116    }
 117}
 118
 119void helper_store_40x_dbcr0(CPUPPCState *env, target_ulong val)
 120{
 121    store_40x_dbcr0(env, val);
 122}
 123
 124void helper_store_40x_sler(CPUPPCState *env, target_ulong val)
 125{
 126    store_40x_sler(env, val);
 127}
 128#endif
 129/*****************************************************************************/
 130/* PowerPC 601 specific instructions (POWER bridge) */
 131
 132target_ulong helper_clcs(CPUPPCState *env, uint32_t arg)
 133{
 134    switch (arg) {
 135    case 0x0CUL:
 136        /* Instruction cache line size */
 137        return env->icache_line_size;
 138        break;
 139    case 0x0DUL:
 140        /* Data cache line size */
 141        return env->dcache_line_size;
 142        break;
 143    case 0x0EUL:
 144        /* Minimum cache line size */
 145        return (env->icache_line_size < env->dcache_line_size) ?
 146            env->icache_line_size : env->dcache_line_size;
 147        break;
 148    case 0x0FUL:
 149        /* Maximum cache line size */
 150        return (env->icache_line_size > env->dcache_line_size) ?
 151            env->icache_line_size : env->dcache_line_size;
 152        break;
 153    default:
 154        /* Undefined */
 155        return 0;
 156        break;
 157    }
 158}
 159
 160/*****************************************************************************/
 161/* Special registers manipulation */
 162
 163/* GDBstub can read and write MSR... */
 164void ppc_store_msr(CPUPPCState *env, target_ulong value)
 165{
 166    hreg_store_msr(env, value, 0);
 167}
 168