qemu/target-ppc/translate.c
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   1/*
   2 *  PowerPC emulation for qemu: main translation routines.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright (C) 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "disas/disas.h"
  24#include "tcg-op.h"
  25#include "qemu/host-utils.h"
  26#include "exec/cpu_ldst.h"
  27
  28#include "exec/helper-proto.h"
  29#include "exec/helper-gen.h"
  30
  31#include "trace-tcg.h"
  32#include "exec/log.h"
  33
  34
  35#define CPU_SINGLE_STEP 0x1
  36#define CPU_BRANCH_STEP 0x2
  37#define GDBSTUB_SINGLE_STEP 0x4
  38
  39/* Include definitions for instructions classes and implementations flags */
  40//#define PPC_DEBUG_DISAS
  41//#define DO_PPC_STATISTICS
  42
  43#ifdef PPC_DEBUG_DISAS
  44#  define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
  45#else
  46#  define LOG_DISAS(...) do { } while (0)
  47#endif
  48/*****************************************************************************/
  49/* Code translation helpers                                                  */
  50
  51/* global register indexes */
  52static TCGv_env cpu_env;
  53static char cpu_reg_names[10*3 + 22*4 /* GPR */
  54    + 10*4 + 22*5 /* SPE GPRh */
  55    + 10*4 + 22*5 /* FPR */
  56    + 2*(10*6 + 22*7) /* AVRh, AVRl */
  57    + 10*5 + 22*6 /* VSR */
  58    + 8*5 /* CRF */];
  59static TCGv cpu_gpr[32];
  60static TCGv cpu_gprh[32];
  61static TCGv_i64 cpu_fpr[32];
  62static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
  63static TCGv_i64 cpu_vsr[32];
  64static TCGv_i32 cpu_crf[8];
  65static TCGv cpu_nip;
  66static TCGv cpu_msr;
  67static TCGv cpu_ctr;
  68static TCGv cpu_lr;
  69#if defined(TARGET_PPC64)
  70static TCGv cpu_cfar;
  71#endif
  72static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
  73static TCGv cpu_reserve;
  74static TCGv cpu_fpscr;
  75static TCGv_i32 cpu_access_type;
  76
  77#include "exec/gen-icount.h"
  78
  79void ppc_translate_init(void)
  80{
  81    int i;
  82    char* p;
  83    size_t cpu_reg_names_size;
  84    static int done_init = 0;
  85
  86    if (done_init)
  87        return;
  88
  89    cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
  90
  91    p = cpu_reg_names;
  92    cpu_reg_names_size = sizeof(cpu_reg_names);
  93
  94    for (i = 0; i < 8; i++) {
  95        snprintf(p, cpu_reg_names_size, "crf%d", i);
  96        cpu_crf[i] = tcg_global_mem_new_i32(cpu_env,
  97                                            offsetof(CPUPPCState, crf[i]), p);
  98        p += 5;
  99        cpu_reg_names_size -= 5;
 100    }
 101
 102    for (i = 0; i < 32; i++) {
 103        snprintf(p, cpu_reg_names_size, "r%d", i);
 104        cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 105                                        offsetof(CPUPPCState, gpr[i]), p);
 106        p += (i < 10) ? 3 : 4;
 107        cpu_reg_names_size -= (i < 10) ? 3 : 4;
 108        snprintf(p, cpu_reg_names_size, "r%dH", i);
 109        cpu_gprh[i] = tcg_global_mem_new(cpu_env,
 110                                         offsetof(CPUPPCState, gprh[i]), p);
 111        p += (i < 10) ? 4 : 5;
 112        cpu_reg_names_size -= (i < 10) ? 4 : 5;
 113
 114        snprintf(p, cpu_reg_names_size, "fp%d", i);
 115        cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
 116                                            offsetof(CPUPPCState, fpr[i]), p);
 117        p += (i < 10) ? 4 : 5;
 118        cpu_reg_names_size -= (i < 10) ? 4 : 5;
 119
 120        snprintf(p, cpu_reg_names_size, "avr%dH", i);
 121#ifdef HOST_WORDS_BIGENDIAN
 122        cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
 123                                             offsetof(CPUPPCState, avr[i].u64[0]), p);
 124#else
 125        cpu_avrh[i] = tcg_global_mem_new_i64(cpu_env,
 126                                             offsetof(CPUPPCState, avr[i].u64[1]), p);
 127#endif
 128        p += (i < 10) ? 6 : 7;
 129        cpu_reg_names_size -= (i < 10) ? 6 : 7;
 130
 131        snprintf(p, cpu_reg_names_size, "avr%dL", i);
 132#ifdef HOST_WORDS_BIGENDIAN
 133        cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
 134                                             offsetof(CPUPPCState, avr[i].u64[1]), p);
 135#else
 136        cpu_avrl[i] = tcg_global_mem_new_i64(cpu_env,
 137                                             offsetof(CPUPPCState, avr[i].u64[0]), p);
 138#endif
 139        p += (i < 10) ? 6 : 7;
 140        cpu_reg_names_size -= (i < 10) ? 6 : 7;
 141        snprintf(p, cpu_reg_names_size, "vsr%d", i);
 142        cpu_vsr[i] = tcg_global_mem_new_i64(cpu_env,
 143                                            offsetof(CPUPPCState, vsr[i]), p);
 144        p += (i < 10) ? 5 : 6;
 145        cpu_reg_names_size -= (i < 10) ? 5 : 6;
 146    }
 147
 148    cpu_nip = tcg_global_mem_new(cpu_env,
 149                                 offsetof(CPUPPCState, nip), "nip");
 150
 151    cpu_msr = tcg_global_mem_new(cpu_env,
 152                                 offsetof(CPUPPCState, msr), "msr");
 153
 154    cpu_ctr = tcg_global_mem_new(cpu_env,
 155                                 offsetof(CPUPPCState, ctr), "ctr");
 156
 157    cpu_lr = tcg_global_mem_new(cpu_env,
 158                                offsetof(CPUPPCState, lr), "lr");
 159
 160#if defined(TARGET_PPC64)
 161    cpu_cfar = tcg_global_mem_new(cpu_env,
 162                                  offsetof(CPUPPCState, cfar), "cfar");
 163#endif
 164
 165    cpu_xer = tcg_global_mem_new(cpu_env,
 166                                 offsetof(CPUPPCState, xer), "xer");
 167    cpu_so = tcg_global_mem_new(cpu_env,
 168                                offsetof(CPUPPCState, so), "SO");
 169    cpu_ov = tcg_global_mem_new(cpu_env,
 170                                offsetof(CPUPPCState, ov), "OV");
 171    cpu_ca = tcg_global_mem_new(cpu_env,
 172                                offsetof(CPUPPCState, ca), "CA");
 173
 174    cpu_reserve = tcg_global_mem_new(cpu_env,
 175                                     offsetof(CPUPPCState, reserve_addr),
 176                                     "reserve_addr");
 177
 178    cpu_fpscr = tcg_global_mem_new(cpu_env,
 179                                   offsetof(CPUPPCState, fpscr), "fpscr");
 180
 181    cpu_access_type = tcg_global_mem_new_i32(cpu_env,
 182                                             offsetof(CPUPPCState, access_type), "access_type");
 183
 184    done_init = 1;
 185}
 186
 187/* internal defines */
 188struct DisasContext {
 189    struct TranslationBlock *tb;
 190    target_ulong nip;
 191    uint32_t opcode;
 192    uint32_t exception;
 193    /* Routine used to access memory */
 194    bool pr, hv;
 195    int mem_idx;
 196    int access_type;
 197    /* Translation flags */
 198    int le_mode;
 199    TCGMemOp default_tcg_memop_mask;
 200#if defined(TARGET_PPC64)
 201    int sf_mode;
 202    int has_cfar;
 203#endif
 204    int fpu_enabled;
 205    int altivec_enabled;
 206    int vsx_enabled;
 207    int spe_enabled;
 208    int tm_enabled;
 209    ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
 210    int singlestep_enabled;
 211    uint64_t insns_flags;
 212    uint64_t insns_flags2;
 213};
 214
 215/* Return true iff byteswap is needed in a scalar memop */
 216static inline bool need_byteswap(const DisasContext *ctx)
 217{
 218#if defined(TARGET_WORDS_BIGENDIAN)
 219     return ctx->le_mode;
 220#else
 221     return !ctx->le_mode;
 222#endif
 223}
 224
 225/* True when active word size < size of target_long.  */
 226#ifdef TARGET_PPC64
 227# define NARROW_MODE(C)  (!(C)->sf_mode)
 228#else
 229# define NARROW_MODE(C)  0
 230#endif
 231
 232struct opc_handler_t {
 233    /* invalid bits for instruction 1 (Rc(opcode) == 0) */
 234    uint32_t inval1;
 235    /* invalid bits for instruction 2 (Rc(opcode) == 1) */
 236    uint32_t inval2;
 237    /* instruction type */
 238    uint64_t type;
 239    /* extended instruction type */
 240    uint64_t type2;
 241    /* handler */
 242    void (*handler)(DisasContext *ctx);
 243#if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
 244    const char *oname;
 245#endif
 246#if defined(DO_PPC_STATISTICS)
 247    uint64_t count;
 248#endif
 249};
 250
 251static inline void gen_reset_fpstatus(void)
 252{
 253    gen_helper_reset_fpstatus(cpu_env);
 254}
 255
 256static inline void gen_compute_fprf(TCGv_i64 arg)
 257{
 258    gen_helper_compute_fprf(cpu_env, arg);
 259    gen_helper_float_check_status(cpu_env);
 260}
 261
 262static inline void gen_set_access_type(DisasContext *ctx, int access_type)
 263{
 264    if (ctx->access_type != access_type) {
 265        tcg_gen_movi_i32(cpu_access_type, access_type);
 266        ctx->access_type = access_type;
 267    }
 268}
 269
 270static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
 271{
 272    if (NARROW_MODE(ctx)) {
 273        nip = (uint32_t)nip;
 274    }
 275    tcg_gen_movi_tl(cpu_nip, nip);
 276}
 277
 278void gen_update_current_nip(void *opaque)
 279{
 280    DisasContext *ctx = opaque;
 281
 282    tcg_gen_movi_tl(cpu_nip, ctx->nip);
 283}
 284
 285static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
 286{
 287    TCGv_i32 t0, t1;
 288    if (ctx->exception == POWERPC_EXCP_NONE) {
 289        gen_update_nip(ctx, ctx->nip);
 290    }
 291    t0 = tcg_const_i32(excp);
 292    t1 = tcg_const_i32(error);
 293    gen_helper_raise_exception_err(cpu_env, t0, t1);
 294    tcg_temp_free_i32(t0);
 295    tcg_temp_free_i32(t1);
 296    ctx->exception = (excp);
 297}
 298
 299static inline void gen_exception(DisasContext *ctx, uint32_t excp)
 300{
 301    TCGv_i32 t0;
 302    if (ctx->exception == POWERPC_EXCP_NONE) {
 303        gen_update_nip(ctx, ctx->nip);
 304    }
 305    t0 = tcg_const_i32(excp);
 306    gen_helper_raise_exception(cpu_env, t0);
 307    tcg_temp_free_i32(t0);
 308    ctx->exception = (excp);
 309}
 310
 311static inline void gen_debug_exception(DisasContext *ctx)
 312{
 313    TCGv_i32 t0;
 314
 315    if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
 316        (ctx->exception != POWERPC_EXCP_SYNC)) {
 317        gen_update_nip(ctx, ctx->nip);
 318    }
 319    t0 = tcg_const_i32(EXCP_DEBUG);
 320    gen_helper_raise_exception(cpu_env, t0);
 321    tcg_temp_free_i32(t0);
 322}
 323
 324static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
 325{
 326    gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
 327}
 328
 329/* Stop translation */
 330static inline void gen_stop_exception(DisasContext *ctx)
 331{
 332    gen_update_nip(ctx, ctx->nip);
 333    ctx->exception = POWERPC_EXCP_STOP;
 334}
 335
 336#ifndef CONFIG_USER_ONLY
 337/* No need to update nip here, as execution flow will change */
 338static inline void gen_sync_exception(DisasContext *ctx)
 339{
 340    ctx->exception = POWERPC_EXCP_SYNC;
 341}
 342#endif
 343
 344#define GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                      \
 345GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
 346
 347#define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2)             \
 348GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
 349
 350#define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type)               \
 351GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
 352
 353#define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2)      \
 354GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
 355
 356typedef struct opcode_t {
 357    unsigned char opc1, opc2, opc3;
 358#if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
 359    unsigned char pad[5];
 360#else
 361    unsigned char pad[1];
 362#endif
 363    opc_handler_t handler;
 364    const char *oname;
 365} opcode_t;
 366
 367/*****************************************************************************/
 368/***                           Instruction decoding                        ***/
 369#define EXTRACT_HELPER(name, shift, nb)                                       \
 370static inline uint32_t name(uint32_t opcode)                                  \
 371{                                                                             \
 372    return (opcode >> (shift)) & ((1 << (nb)) - 1);                           \
 373}
 374
 375#define EXTRACT_SHELPER(name, shift, nb)                                      \
 376static inline int32_t name(uint32_t opcode)                                   \
 377{                                                                             \
 378    return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1));                \
 379}
 380
 381#define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2)                  \
 382static inline uint32_t name(uint32_t opcode)                                  \
 383{                                                                             \
 384    return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) |             \
 385            ((opcode >> (shift2)) & ((1 << (nb2)) - 1));                      \
 386}
 387/* Opcode part 1 */
 388EXTRACT_HELPER(opc1, 26, 6);
 389/* Opcode part 2 */
 390EXTRACT_HELPER(opc2, 1, 5);
 391/* Opcode part 3 */
 392EXTRACT_HELPER(opc3, 6, 5);
 393/* Update Cr0 flags */
 394EXTRACT_HELPER(Rc, 0, 1);
 395/* Update Cr6 flags (Altivec) */
 396EXTRACT_HELPER(Rc21, 10, 1);
 397/* Destination */
 398EXTRACT_HELPER(rD, 21, 5);
 399/* Source */
 400EXTRACT_HELPER(rS, 21, 5);
 401/* First operand */
 402EXTRACT_HELPER(rA, 16, 5);
 403/* Second operand */
 404EXTRACT_HELPER(rB, 11, 5);
 405/* Third operand */
 406EXTRACT_HELPER(rC, 6, 5);
 407/***                               Get CRn                                 ***/
 408EXTRACT_HELPER(crfD, 23, 3);
 409EXTRACT_HELPER(crfS, 18, 3);
 410EXTRACT_HELPER(crbD, 21, 5);
 411EXTRACT_HELPER(crbA, 16, 5);
 412EXTRACT_HELPER(crbB, 11, 5);
 413/* SPR / TBL */
 414EXTRACT_HELPER(_SPR, 11, 10);
 415static inline uint32_t SPR(uint32_t opcode)
 416{
 417    uint32_t sprn = _SPR(opcode);
 418
 419    return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
 420}
 421/***                              Get constants                            ***/
 422/* 16 bits signed immediate value */
 423EXTRACT_SHELPER(SIMM, 0, 16);
 424/* 16 bits unsigned immediate value */
 425EXTRACT_HELPER(UIMM, 0, 16);
 426/* 5 bits signed immediate value */
 427EXTRACT_HELPER(SIMM5, 16, 5);
 428/* 5 bits signed immediate value */
 429EXTRACT_HELPER(UIMM5, 16, 5);
 430/* Bit count */
 431EXTRACT_HELPER(NB, 11, 5);
 432/* Shift count */
 433EXTRACT_HELPER(SH, 11, 5);
 434/* Vector shift count */
 435EXTRACT_HELPER(VSH, 6, 4);
 436/* Mask start */
 437EXTRACT_HELPER(MB, 6, 5);
 438/* Mask end */
 439EXTRACT_HELPER(ME, 1, 5);
 440/* Trap operand */
 441EXTRACT_HELPER(TO, 21, 5);
 442
 443EXTRACT_HELPER(CRM, 12, 8);
 444
 445#ifndef CONFIG_USER_ONLY
 446EXTRACT_HELPER(SR, 16, 4);
 447#endif
 448
 449/* mtfsf/mtfsfi */
 450EXTRACT_HELPER(FPBF, 23, 3);
 451EXTRACT_HELPER(FPIMM, 12, 4);
 452EXTRACT_HELPER(FPL, 25, 1);
 453EXTRACT_HELPER(FPFLM, 17, 8);
 454EXTRACT_HELPER(FPW, 16, 1);
 455
 456/***                            Jump target decoding                       ***/
 457/* Immediate address */
 458static inline target_ulong LI(uint32_t opcode)
 459{
 460    return (opcode >> 0) & 0x03FFFFFC;
 461}
 462
 463static inline uint32_t BD(uint32_t opcode)
 464{
 465    return (opcode >> 0) & 0xFFFC;
 466}
 467
 468EXTRACT_HELPER(BO, 21, 5);
 469EXTRACT_HELPER(BI, 16, 5);
 470/* Absolute/relative address */
 471EXTRACT_HELPER(AA, 1, 1);
 472/* Link */
 473EXTRACT_HELPER(LK, 0, 1);
 474
 475/* DFP Z22-form */
 476EXTRACT_HELPER(DCM, 10, 6)
 477
 478/* DFP Z23-form */
 479EXTRACT_HELPER(RMC, 9, 2)
 480
 481/* Create a mask between <start> and <end> bits */
 482static inline target_ulong MASK(uint32_t start, uint32_t end)
 483{
 484    target_ulong ret;
 485
 486#if defined(TARGET_PPC64)
 487    if (likely(start == 0)) {
 488        ret = UINT64_MAX << (63 - end);
 489    } else if (likely(end == 63)) {
 490        ret = UINT64_MAX >> start;
 491    }
 492#else
 493    if (likely(start == 0)) {
 494        ret = UINT32_MAX << (31  - end);
 495    } else if (likely(end == 31)) {
 496        ret = UINT32_MAX >> start;
 497    }
 498#endif
 499    else {
 500        ret = (((target_ulong)(-1ULL)) >> (start)) ^
 501            (((target_ulong)(-1ULL) >> (end)) >> 1);
 502        if (unlikely(start > end))
 503            return ~ret;
 504    }
 505
 506    return ret;
 507}
 508
 509EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
 510EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
 511EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
 512EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
 513EXTRACT_HELPER_SPLIT(xC, 3, 1,  6, 5);
 514EXTRACT_HELPER(DM, 8, 2);
 515EXTRACT_HELPER(UIM, 16, 2);
 516EXTRACT_HELPER(SHW, 8, 2);
 517EXTRACT_HELPER(SP, 19, 2);
 518/*****************************************************************************/
 519/* PowerPC instructions table                                                */
 520
 521#if defined(DO_PPC_STATISTICS)
 522#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
 523{                                                                             \
 524    .opc1 = op1,                                                              \
 525    .opc2 = op2,                                                              \
 526    .opc3 = op3,                                                              \
 527    .pad  = { 0, },                                                           \
 528    .handler = {                                                              \
 529        .inval1  = invl,                                                      \
 530        .type = _typ,                                                         \
 531        .type2 = _typ2,                                                       \
 532        .handler = &gen_##name,                                               \
 533        .oname = stringify(name),                                             \
 534    },                                                                        \
 535    .oname = stringify(name),                                                 \
 536}
 537#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
 538{                                                                             \
 539    .opc1 = op1,                                                              \
 540    .opc2 = op2,                                                              \
 541    .opc3 = op3,                                                              \
 542    .pad  = { 0, },                                                           \
 543    .handler = {                                                              \
 544        .inval1  = invl1,                                                     \
 545        .inval2  = invl2,                                                     \
 546        .type = _typ,                                                         \
 547        .type2 = _typ2,                                                       \
 548        .handler = &gen_##name,                                               \
 549        .oname = stringify(name),                                             \
 550    },                                                                        \
 551    .oname = stringify(name),                                                 \
 552}
 553#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
 554{                                                                             \
 555    .opc1 = op1,                                                              \
 556    .opc2 = op2,                                                              \
 557    .opc3 = op3,                                                              \
 558    .pad  = { 0, },                                                           \
 559    .handler = {                                                              \
 560        .inval1  = invl,                                                      \
 561        .type = _typ,                                                         \
 562        .type2 = _typ2,                                                       \
 563        .handler = &gen_##name,                                               \
 564        .oname = onam,                                                        \
 565    },                                                                        \
 566    .oname = onam,                                                            \
 567}
 568#else
 569#define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2)                    \
 570{                                                                             \
 571    .opc1 = op1,                                                              \
 572    .opc2 = op2,                                                              \
 573    .opc3 = op3,                                                              \
 574    .pad  = { 0, },                                                           \
 575    .handler = {                                                              \
 576        .inval1  = invl,                                                      \
 577        .type = _typ,                                                         \
 578        .type2 = _typ2,                                                       \
 579        .handler = &gen_##name,                                               \
 580    },                                                                        \
 581    .oname = stringify(name),                                                 \
 582}
 583#define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2)       \
 584{                                                                             \
 585    .opc1 = op1,                                                              \
 586    .opc2 = op2,                                                              \
 587    .opc3 = op3,                                                              \
 588    .pad  = { 0, },                                                           \
 589    .handler = {                                                              \
 590        .inval1  = invl1,                                                     \
 591        .inval2  = invl2,                                                     \
 592        .type = _typ,                                                         \
 593        .type2 = _typ2,                                                       \
 594        .handler = &gen_##name,                                               \
 595    },                                                                        \
 596    .oname = stringify(name),                                                 \
 597}
 598#define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2)             \
 599{                                                                             \
 600    .opc1 = op1,                                                              \
 601    .opc2 = op2,                                                              \
 602    .opc3 = op3,                                                              \
 603    .pad  = { 0, },                                                           \
 604    .handler = {                                                              \
 605        .inval1  = invl,                                                      \
 606        .type = _typ,                                                         \
 607        .type2 = _typ2,                                                       \
 608        .handler = &gen_##name,                                               \
 609    },                                                                        \
 610    .oname = onam,                                                            \
 611}
 612#endif
 613
 614/* SPR load/store helpers */
 615static inline void gen_load_spr(TCGv t, int reg)
 616{
 617    tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
 618}
 619
 620static inline void gen_store_spr(int reg, TCGv t)
 621{
 622    tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
 623}
 624
 625/* Invalid instruction */
 626static void gen_invalid(DisasContext *ctx)
 627{
 628    gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
 629}
 630
 631static opc_handler_t invalid_handler = {
 632    .inval1  = 0xFFFFFFFF,
 633    .inval2  = 0xFFFFFFFF,
 634    .type    = PPC_NONE,
 635    .type2   = PPC_NONE,
 636    .handler = gen_invalid,
 637};
 638
 639/***                           Integer comparison                          ***/
 640
 641static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
 642{
 643    TCGv t0 = tcg_temp_new();
 644    TCGv_i32 t1 = tcg_temp_new_i32();
 645
 646    tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
 647
 648    tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
 649    tcg_gen_trunc_tl_i32(t1, t0);
 650    tcg_gen_shli_i32(t1, t1, CRF_LT);
 651    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
 652
 653    tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
 654    tcg_gen_trunc_tl_i32(t1, t0);
 655    tcg_gen_shli_i32(t1, t1, CRF_GT);
 656    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
 657
 658    tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
 659    tcg_gen_trunc_tl_i32(t1, t0);
 660    tcg_gen_shli_i32(t1, t1, CRF_EQ);
 661    tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
 662
 663    tcg_temp_free(t0);
 664    tcg_temp_free_i32(t1);
 665}
 666
 667static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
 668{
 669    TCGv t0 = tcg_const_tl(arg1);
 670    gen_op_cmp(arg0, t0, s, crf);
 671    tcg_temp_free(t0);
 672}
 673
 674static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
 675{
 676    TCGv t0, t1;
 677    t0 = tcg_temp_new();
 678    t1 = tcg_temp_new();
 679    if (s) {
 680        tcg_gen_ext32s_tl(t0, arg0);
 681        tcg_gen_ext32s_tl(t1, arg1);
 682    } else {
 683        tcg_gen_ext32u_tl(t0, arg0);
 684        tcg_gen_ext32u_tl(t1, arg1);
 685    }
 686    gen_op_cmp(t0, t1, s, crf);
 687    tcg_temp_free(t1);
 688    tcg_temp_free(t0);
 689}
 690
 691static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
 692{
 693    TCGv t0 = tcg_const_tl(arg1);
 694    gen_op_cmp32(arg0, t0, s, crf);
 695    tcg_temp_free(t0);
 696}
 697
 698static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
 699{
 700    if (NARROW_MODE(ctx)) {
 701        gen_op_cmpi32(reg, 0, 1, 0);
 702    } else {
 703        gen_op_cmpi(reg, 0, 1, 0);
 704    }
 705}
 706
 707/* cmp */
 708static void gen_cmp(DisasContext *ctx)
 709{
 710    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
 711        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
 712                   1, crfD(ctx->opcode));
 713    } else {
 714        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
 715                     1, crfD(ctx->opcode));
 716    }
 717}
 718
 719/* cmpi */
 720static void gen_cmpi(DisasContext *ctx)
 721{
 722    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
 723        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
 724                    1, crfD(ctx->opcode));
 725    } else {
 726        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
 727                      1, crfD(ctx->opcode));
 728    }
 729}
 730
 731/* cmpl */
 732static void gen_cmpl(DisasContext *ctx)
 733{
 734    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
 735        gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
 736                   0, crfD(ctx->opcode));
 737    } else {
 738        gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
 739                     0, crfD(ctx->opcode));
 740    }
 741}
 742
 743/* cmpli */
 744static void gen_cmpli(DisasContext *ctx)
 745{
 746    if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
 747        gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
 748                    0, crfD(ctx->opcode));
 749    } else {
 750        gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
 751                      0, crfD(ctx->opcode));
 752    }
 753}
 754
 755/* isel (PowerPC 2.03 specification) */
 756static void gen_isel(DisasContext *ctx)
 757{
 758    TCGLabel *l1, *l2;
 759    uint32_t bi = rC(ctx->opcode);
 760    uint32_t mask;
 761    TCGv_i32 t0;
 762
 763    l1 = gen_new_label();
 764    l2 = gen_new_label();
 765
 766    mask = 0x08 >> (bi & 0x03);
 767    t0 = tcg_temp_new_i32();
 768    tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
 769    tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
 770    if (rA(ctx->opcode) == 0)
 771        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
 772    else
 773        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
 774    tcg_gen_br(l2);
 775    gen_set_label(l1);
 776    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
 777    gen_set_label(l2);
 778    tcg_temp_free_i32(t0);
 779}
 780
 781/* cmpb: PowerPC 2.05 specification */
 782static void gen_cmpb(DisasContext *ctx)
 783{
 784    gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
 785                    cpu_gpr[rB(ctx->opcode)]);
 786}
 787
 788/***                           Integer arithmetic                          ***/
 789
 790static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
 791                                           TCGv arg1, TCGv arg2, int sub)
 792{
 793    TCGv t0 = tcg_temp_new();
 794
 795    tcg_gen_xor_tl(cpu_ov, arg0, arg2);
 796    tcg_gen_xor_tl(t0, arg1, arg2);
 797    if (sub) {
 798        tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
 799    } else {
 800        tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
 801    }
 802    tcg_temp_free(t0);
 803    if (NARROW_MODE(ctx)) {
 804        tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
 805    }
 806    tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
 807    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
 808}
 809
 810/* Common add function */
 811static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
 812                                    TCGv arg2, bool add_ca, bool compute_ca,
 813                                    bool compute_ov, bool compute_rc0)
 814{
 815    TCGv t0 = ret;
 816
 817    if (compute_ca || compute_ov) {
 818        t0 = tcg_temp_new();
 819    }
 820
 821    if (compute_ca) {
 822        if (NARROW_MODE(ctx)) {
 823            /* Caution: a non-obvious corner case of the spec is that we
 824               must produce the *entire* 64-bit addition, but produce the
 825               carry into bit 32.  */
 826            TCGv t1 = tcg_temp_new();
 827            tcg_gen_xor_tl(t1, arg1, arg2);        /* add without carry */
 828            tcg_gen_add_tl(t0, arg1, arg2);
 829            if (add_ca) {
 830                tcg_gen_add_tl(t0, t0, cpu_ca);
 831            }
 832            tcg_gen_xor_tl(cpu_ca, t0, t1);        /* bits changed w/ carry */
 833            tcg_temp_free(t1);
 834            tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);   /* extract bit 32 */
 835            tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
 836        } else {
 837            TCGv zero = tcg_const_tl(0);
 838            if (add_ca) {
 839                tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
 840                tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
 841            } else {
 842                tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
 843            }
 844            tcg_temp_free(zero);
 845        }
 846    } else {
 847        tcg_gen_add_tl(t0, arg1, arg2);
 848        if (add_ca) {
 849            tcg_gen_add_tl(t0, t0, cpu_ca);
 850        }
 851    }
 852
 853    if (compute_ov) {
 854        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
 855    }
 856    if (unlikely(compute_rc0)) {
 857        gen_set_Rc0(ctx, t0);
 858    }
 859
 860    if (!TCGV_EQUAL(t0, ret)) {
 861        tcg_gen_mov_tl(ret, t0);
 862        tcg_temp_free(t0);
 863    }
 864}
 865/* Add functions with two operands */
 866#define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov)         \
 867static void glue(gen_, name)(DisasContext *ctx)                               \
 868{                                                                             \
 869    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
 870                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
 871                     add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
 872}
 873/* Add functions with one operand and one immediate */
 874#define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val,                        \
 875                                add_ca, compute_ca, compute_ov)               \
 876static void glue(gen_, name)(DisasContext *ctx)                               \
 877{                                                                             \
 878    TCGv t0 = tcg_const_tl(const_val);                                        \
 879    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)],                           \
 880                     cpu_gpr[rA(ctx->opcode)], t0,                            \
 881                     add_ca, compute_ca, compute_ov, Rc(ctx->opcode));        \
 882    tcg_temp_free(t0);                                                        \
 883}
 884
 885/* add  add.  addo  addo. */
 886GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
 887GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
 888/* addc  addc.  addco  addco. */
 889GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
 890GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
 891/* adde  adde.  addeo  addeo. */
 892GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
 893GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
 894/* addme  addme.  addmeo  addmeo.  */
 895GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
 896GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
 897/* addze  addze.  addzeo  addzeo.*/
 898GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
 899GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
 900/* addi */
 901static void gen_addi(DisasContext *ctx)
 902{
 903    target_long simm = SIMM(ctx->opcode);
 904
 905    if (rA(ctx->opcode) == 0) {
 906        /* li case */
 907        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
 908    } else {
 909        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
 910                        cpu_gpr[rA(ctx->opcode)], simm);
 911    }
 912}
 913/* addic  addic.*/
 914static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
 915{
 916    TCGv c = tcg_const_tl(SIMM(ctx->opcode));
 917    gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
 918                     c, 0, 1, 0, compute_rc0);
 919    tcg_temp_free(c);
 920}
 921
 922static void gen_addic(DisasContext *ctx)
 923{
 924    gen_op_addic(ctx, 0);
 925}
 926
 927static void gen_addic_(DisasContext *ctx)
 928{
 929    gen_op_addic(ctx, 1);
 930}
 931
 932/* addis */
 933static void gen_addis(DisasContext *ctx)
 934{
 935    target_long simm = SIMM(ctx->opcode);
 936
 937    if (rA(ctx->opcode) == 0) {
 938        /* lis case */
 939        tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
 940    } else {
 941        tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
 942                        cpu_gpr[rA(ctx->opcode)], simm << 16);
 943    }
 944}
 945
 946static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
 947                                     TCGv arg2, int sign, int compute_ov)
 948{
 949    TCGLabel *l1 = gen_new_label();
 950    TCGLabel *l2 = gen_new_label();
 951    TCGv_i32 t0 = tcg_temp_local_new_i32();
 952    TCGv_i32 t1 = tcg_temp_local_new_i32();
 953
 954    tcg_gen_trunc_tl_i32(t0, arg1);
 955    tcg_gen_trunc_tl_i32(t1, arg2);
 956    tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
 957    if (sign) {
 958        TCGLabel *l3 = gen_new_label();
 959        tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
 960        tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
 961        gen_set_label(l3);
 962        tcg_gen_div_i32(t0, t0, t1);
 963    } else {
 964        tcg_gen_divu_i32(t0, t0, t1);
 965    }
 966    if (compute_ov) {
 967        tcg_gen_movi_tl(cpu_ov, 0);
 968    }
 969    tcg_gen_br(l2);
 970    gen_set_label(l1);
 971    if (sign) {
 972        tcg_gen_sari_i32(t0, t0, 31);
 973    } else {
 974        tcg_gen_movi_i32(t0, 0);
 975    }
 976    if (compute_ov) {
 977        tcg_gen_movi_tl(cpu_ov, 1);
 978        tcg_gen_movi_tl(cpu_so, 1);
 979    }
 980    gen_set_label(l2);
 981    tcg_gen_extu_i32_tl(ret, t0);
 982    tcg_temp_free_i32(t0);
 983    tcg_temp_free_i32(t1);
 984    if (unlikely(Rc(ctx->opcode) != 0))
 985        gen_set_Rc0(ctx, ret);
 986}
 987/* Div functions */
 988#define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov)                      \
 989static void glue(gen_, name)(DisasContext *ctx)                                       \
 990{                                                                             \
 991    gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)],                          \
 992                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],      \
 993                     sign, compute_ov);                                       \
 994}
 995/* divwu  divwu.  divwuo  divwuo.   */
 996GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
 997GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
 998/* divw  divw.  divwo  divwo.   */
 999GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1000GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1001
1002/* div[wd]eu[o][.] */
1003#define GEN_DIVE(name, hlpr, compute_ov)                                      \
1004static void gen_##name(DisasContext *ctx)                                     \
1005{                                                                             \
1006    TCGv_i32 t0 = tcg_const_i32(compute_ov);                                  \
1007    gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env,                      \
1008                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
1009    tcg_temp_free_i32(t0);                                                    \
1010    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
1011        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);                           \
1012    }                                                                         \
1013}
1014
1015GEN_DIVE(divweu, divweu, 0);
1016GEN_DIVE(divweuo, divweu, 1);
1017GEN_DIVE(divwe, divwe, 0);
1018GEN_DIVE(divweo, divwe, 1);
1019
1020#if defined(TARGET_PPC64)
1021static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1022                                     TCGv arg2, int sign, int compute_ov)
1023{
1024    TCGLabel *l1 = gen_new_label();
1025    TCGLabel *l2 = gen_new_label();
1026
1027    tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1028    if (sign) {
1029        TCGLabel *l3 = gen_new_label();
1030        tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1031        tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1032        gen_set_label(l3);
1033        tcg_gen_div_i64(ret, arg1, arg2);
1034    } else {
1035        tcg_gen_divu_i64(ret, arg1, arg2);
1036    }
1037    if (compute_ov) {
1038        tcg_gen_movi_tl(cpu_ov, 0);
1039    }
1040    tcg_gen_br(l2);
1041    gen_set_label(l1);
1042    if (sign) {
1043        tcg_gen_sari_i64(ret, arg1, 63);
1044    } else {
1045        tcg_gen_movi_i64(ret, 0);
1046    }
1047    if (compute_ov) {
1048        tcg_gen_movi_tl(cpu_ov, 1);
1049        tcg_gen_movi_tl(cpu_so, 1);
1050    }
1051    gen_set_label(l2);
1052    if (unlikely(Rc(ctx->opcode) != 0))
1053        gen_set_Rc0(ctx, ret);
1054}
1055#define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov)                      \
1056static void glue(gen_, name)(DisasContext *ctx)                                       \
1057{                                                                             \
1058    gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1059                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1060                      sign, compute_ov);                                      \
1061}
1062/* divwu  divwu.  divwuo  divwuo.   */
1063GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1064GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1065/* divw  divw.  divwo  divwo.   */
1066GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1067GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1068
1069GEN_DIVE(divdeu, divdeu, 0);
1070GEN_DIVE(divdeuo, divdeu, 1);
1071GEN_DIVE(divde, divde, 0);
1072GEN_DIVE(divdeo, divde, 1);
1073#endif
1074
1075/* mulhw  mulhw. */
1076static void gen_mulhw(DisasContext *ctx)
1077{
1078    TCGv_i32 t0 = tcg_temp_new_i32();
1079    TCGv_i32 t1 = tcg_temp_new_i32();
1080
1081    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1082    tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1083    tcg_gen_muls2_i32(t0, t1, t0, t1);
1084    tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1085    tcg_temp_free_i32(t0);
1086    tcg_temp_free_i32(t1);
1087    if (unlikely(Rc(ctx->opcode) != 0))
1088        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1089}
1090
1091/* mulhwu  mulhwu.  */
1092static void gen_mulhwu(DisasContext *ctx)
1093{
1094    TCGv_i32 t0 = tcg_temp_new_i32();
1095    TCGv_i32 t1 = tcg_temp_new_i32();
1096
1097    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1098    tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1099    tcg_gen_mulu2_i32(t0, t1, t0, t1);
1100    tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1101    tcg_temp_free_i32(t0);
1102    tcg_temp_free_i32(t1);
1103    if (unlikely(Rc(ctx->opcode) != 0))
1104        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1105}
1106
1107/* mullw  mullw. */
1108static void gen_mullw(DisasContext *ctx)
1109{
1110#if defined(TARGET_PPC64)
1111    TCGv_i64 t0, t1;
1112    t0 = tcg_temp_new_i64();
1113    t1 = tcg_temp_new_i64();
1114    tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
1115    tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
1116    tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1117    tcg_temp_free(t0);
1118    tcg_temp_free(t1);
1119#else
1120    tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1121                    cpu_gpr[rB(ctx->opcode)]);
1122#endif
1123    if (unlikely(Rc(ctx->opcode) != 0))
1124        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1125}
1126
1127/* mullwo  mullwo. */
1128static void gen_mullwo(DisasContext *ctx)
1129{
1130    TCGv_i32 t0 = tcg_temp_new_i32();
1131    TCGv_i32 t1 = tcg_temp_new_i32();
1132
1133    tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1134    tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1135    tcg_gen_muls2_i32(t0, t1, t0, t1);
1136#if defined(TARGET_PPC64)
1137    tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1);
1138#else
1139    tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0);
1140#endif
1141
1142    tcg_gen_sari_i32(t0, t0, 31);
1143    tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1144    tcg_gen_extu_i32_tl(cpu_ov, t0);
1145    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1146
1147    tcg_temp_free_i32(t0);
1148    tcg_temp_free_i32(t1);
1149    if (unlikely(Rc(ctx->opcode) != 0))
1150        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1151}
1152
1153/* mulli */
1154static void gen_mulli(DisasContext *ctx)
1155{
1156    tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1157                    SIMM(ctx->opcode));
1158}
1159
1160#if defined(TARGET_PPC64)
1161/* mulhd  mulhd. */
1162static void gen_mulhd(DisasContext *ctx)
1163{
1164    TCGv lo = tcg_temp_new();
1165    tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1166                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1167    tcg_temp_free(lo);
1168    if (unlikely(Rc(ctx->opcode) != 0)) {
1169        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1170    }
1171}
1172
1173/* mulhdu  mulhdu. */
1174static void gen_mulhdu(DisasContext *ctx)
1175{
1176    TCGv lo = tcg_temp_new();
1177    tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1178                     cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1179    tcg_temp_free(lo);
1180    if (unlikely(Rc(ctx->opcode) != 0)) {
1181        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1182    }
1183}
1184
1185/* mulld  mulld. */
1186static void gen_mulld(DisasContext *ctx)
1187{
1188    tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1189                   cpu_gpr[rB(ctx->opcode)]);
1190    if (unlikely(Rc(ctx->opcode) != 0))
1191        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1192}
1193
1194/* mulldo  mulldo. */
1195static void gen_mulldo(DisasContext *ctx)
1196{
1197    TCGv_i64 t0 = tcg_temp_new_i64();
1198    TCGv_i64 t1 = tcg_temp_new_i64();
1199
1200    tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)],
1201                      cpu_gpr[rB(ctx->opcode)]);
1202    tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0);
1203
1204    tcg_gen_sari_i64(t0, t0, 63);
1205    tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1);
1206    tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1207
1208    tcg_temp_free_i64(t0);
1209    tcg_temp_free_i64(t1);
1210
1211    if (unlikely(Rc(ctx->opcode) != 0)) {
1212        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1213    }
1214}
1215#endif
1216
1217/* Common subf function */
1218static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1219                                     TCGv arg2, bool add_ca, bool compute_ca,
1220                                     bool compute_ov, bool compute_rc0)
1221{
1222    TCGv t0 = ret;
1223
1224    if (compute_ca || compute_ov) {
1225        t0 = tcg_temp_new();
1226    }
1227
1228    if (compute_ca) {
1229        /* dest = ~arg1 + arg2 [+ ca].  */
1230        if (NARROW_MODE(ctx)) {
1231            /* Caution: a non-obvious corner case of the spec is that we
1232               must produce the *entire* 64-bit addition, but produce the
1233               carry into bit 32.  */
1234            TCGv inv1 = tcg_temp_new();
1235            TCGv t1 = tcg_temp_new();
1236            tcg_gen_not_tl(inv1, arg1);
1237            if (add_ca) {
1238                tcg_gen_add_tl(t0, arg2, cpu_ca);
1239            } else {
1240                tcg_gen_addi_tl(t0, arg2, 1);
1241            }
1242            tcg_gen_xor_tl(t1, arg2, inv1);         /* add without carry */
1243            tcg_gen_add_tl(t0, t0, inv1);
1244            tcg_temp_free(inv1);
1245            tcg_gen_xor_tl(cpu_ca, t0, t1);         /* bits changes w/ carry */
1246            tcg_temp_free(t1);
1247            tcg_gen_shri_tl(cpu_ca, cpu_ca, 32);    /* extract bit 32 */
1248            tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1249        } else if (add_ca) {
1250            TCGv zero, inv1 = tcg_temp_new();
1251            tcg_gen_not_tl(inv1, arg1);
1252            zero = tcg_const_tl(0);
1253            tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1254            tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1255            tcg_temp_free(zero);
1256            tcg_temp_free(inv1);
1257        } else {
1258            tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1259            tcg_gen_sub_tl(t0, arg2, arg1);
1260        }
1261    } else if (add_ca) {
1262        /* Since we're ignoring carry-out, we can simplify the
1263           standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1.  */
1264        tcg_gen_sub_tl(t0, arg2, arg1);
1265        tcg_gen_add_tl(t0, t0, cpu_ca);
1266        tcg_gen_subi_tl(t0, t0, 1);
1267    } else {
1268        tcg_gen_sub_tl(t0, arg2, arg1);
1269    }
1270
1271    if (compute_ov) {
1272        gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1273    }
1274    if (unlikely(compute_rc0)) {
1275        gen_set_Rc0(ctx, t0);
1276    }
1277
1278    if (!TCGV_EQUAL(t0, ret)) {
1279        tcg_gen_mov_tl(ret, t0);
1280        tcg_temp_free(t0);
1281    }
1282}
1283/* Sub functions with Two operands functions */
1284#define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov)        \
1285static void glue(gen_, name)(DisasContext *ctx)                               \
1286{                                                                             \
1287    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1288                      cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],     \
1289                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
1290}
1291/* Sub functions with one operand and one immediate */
1292#define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val,                       \
1293                                add_ca, compute_ca, compute_ov)               \
1294static void glue(gen_, name)(DisasContext *ctx)                               \
1295{                                                                             \
1296    TCGv t0 = tcg_const_tl(const_val);                                        \
1297    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)],                          \
1298                      cpu_gpr[rA(ctx->opcode)], t0,                           \
1299                      add_ca, compute_ca, compute_ov, Rc(ctx->opcode));       \
1300    tcg_temp_free(t0);                                                        \
1301}
1302/* subf  subf.  subfo  subfo. */
1303GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1304GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1305/* subfc  subfc.  subfco  subfco. */
1306GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1307GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1308/* subfe  subfe.  subfeo  subfo. */
1309GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1310GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1311/* subfme  subfme.  subfmeo  subfmeo.  */
1312GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1313GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1314/* subfze  subfze.  subfzeo  subfzeo.*/
1315GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1316GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1317
1318/* subfic */
1319static void gen_subfic(DisasContext *ctx)
1320{
1321    TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1322    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1323                      c, 0, 1, 0, 0);
1324    tcg_temp_free(c);
1325}
1326
1327/* neg neg. nego nego. */
1328static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1329{
1330    TCGv zero = tcg_const_tl(0);
1331    gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1332                      zero, 0, 0, compute_ov, Rc(ctx->opcode));
1333    tcg_temp_free(zero);
1334}
1335
1336static void gen_neg(DisasContext *ctx)
1337{
1338    gen_op_arith_neg(ctx, 0);
1339}
1340
1341static void gen_nego(DisasContext *ctx)
1342{
1343    gen_op_arith_neg(ctx, 1);
1344}
1345
1346/***                            Integer logical                            ***/
1347#define GEN_LOGICAL2(name, tcg_op, opc, type)                                 \
1348static void glue(gen_, name)(DisasContext *ctx)                                       \
1349{                                                                             \
1350    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],                \
1351       cpu_gpr[rB(ctx->opcode)]);                                             \
1352    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1353        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1354}
1355
1356#define GEN_LOGICAL1(name, tcg_op, opc, type)                                 \
1357static void glue(gen_, name)(DisasContext *ctx)                                       \
1358{                                                                             \
1359    tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);               \
1360    if (unlikely(Rc(ctx->opcode) != 0))                                       \
1361        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);                           \
1362}
1363
1364/* and & and. */
1365GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1366/* andc & andc. */
1367GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1368
1369/* andi. */
1370static void gen_andi_(DisasContext *ctx)
1371{
1372    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1373    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1374}
1375
1376/* andis. */
1377static void gen_andis_(DisasContext *ctx)
1378{
1379    tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1380    gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1381}
1382
1383/* cntlzw */
1384static void gen_cntlzw(DisasContext *ctx)
1385{
1386    gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1387    if (unlikely(Rc(ctx->opcode) != 0))
1388        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1389}
1390/* eqv & eqv. */
1391GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1392/* extsb & extsb. */
1393GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1394/* extsh & extsh. */
1395GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1396/* nand & nand. */
1397GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1398/* nor & nor. */
1399GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1400
1401/* or & or. */
1402static void gen_or(DisasContext *ctx)
1403{
1404    int rs, ra, rb;
1405
1406    rs = rS(ctx->opcode);
1407    ra = rA(ctx->opcode);
1408    rb = rB(ctx->opcode);
1409    /* Optimisation for mr. ri case */
1410    if (rs != ra || rs != rb) {
1411        if (rs != rb)
1412            tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1413        else
1414            tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1415        if (unlikely(Rc(ctx->opcode) != 0))
1416            gen_set_Rc0(ctx, cpu_gpr[ra]);
1417    } else if (unlikely(Rc(ctx->opcode) != 0)) {
1418        gen_set_Rc0(ctx, cpu_gpr[rs]);
1419#if defined(TARGET_PPC64)
1420    } else {
1421        int prio = 0;
1422
1423        switch (rs) {
1424        case 1:
1425            /* Set process priority to low */
1426            prio = 2;
1427            break;
1428        case 6:
1429            /* Set process priority to medium-low */
1430            prio = 3;
1431            break;
1432        case 2:
1433            /* Set process priority to normal */
1434            prio = 4;
1435            break;
1436#if !defined(CONFIG_USER_ONLY)
1437        case 31:
1438            if (!ctx->pr) {
1439                /* Set process priority to very low */
1440                prio = 1;
1441            }
1442            break;
1443        case 5:
1444            if (!ctx->pr) {
1445                /* Set process priority to medium-hight */
1446                prio = 5;
1447            }
1448            break;
1449        case 3:
1450            if (!ctx->pr) {
1451                /* Set process priority to high */
1452                prio = 6;
1453            }
1454            break;
1455        case 7:
1456            if (ctx->hv) {
1457                /* Set process priority to very high */
1458                prio = 7;
1459            }
1460            break;
1461#endif
1462        default:
1463            /* nop */
1464            break;
1465        }
1466        if (prio) {
1467            TCGv t0 = tcg_temp_new();
1468            gen_load_spr(t0, SPR_PPR);
1469            tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1470            tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1471            gen_store_spr(SPR_PPR, t0);
1472            tcg_temp_free(t0);
1473        }
1474#endif
1475    }
1476}
1477/* orc & orc. */
1478GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1479
1480/* xor & xor. */
1481static void gen_xor(DisasContext *ctx)
1482{
1483    /* Optimisation for "set to zero" case */
1484    if (rS(ctx->opcode) != rB(ctx->opcode))
1485        tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1486    else
1487        tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1488    if (unlikely(Rc(ctx->opcode) != 0))
1489        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1490}
1491
1492/* ori */
1493static void gen_ori(DisasContext *ctx)
1494{
1495    target_ulong uimm = UIMM(ctx->opcode);
1496
1497    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1498        /* NOP */
1499        /* XXX: should handle special NOPs for POWER series */
1500        return;
1501    }
1502    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1503}
1504
1505/* oris */
1506static void gen_oris(DisasContext *ctx)
1507{
1508    target_ulong uimm = UIMM(ctx->opcode);
1509
1510    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1511        /* NOP */
1512        return;
1513    }
1514    tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1515}
1516
1517/* xori */
1518static void gen_xori(DisasContext *ctx)
1519{
1520    target_ulong uimm = UIMM(ctx->opcode);
1521
1522    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1523        /* NOP */
1524        return;
1525    }
1526    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1527}
1528
1529/* xoris */
1530static void gen_xoris(DisasContext *ctx)
1531{
1532    target_ulong uimm = UIMM(ctx->opcode);
1533
1534    if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1535        /* NOP */
1536        return;
1537    }
1538    tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1539}
1540
1541/* popcntb : PowerPC 2.03 specification */
1542static void gen_popcntb(DisasContext *ctx)
1543{
1544    gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1545}
1546
1547static void gen_popcntw(DisasContext *ctx)
1548{
1549    gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1550}
1551
1552#if defined(TARGET_PPC64)
1553/* popcntd: PowerPC 2.06 specification */
1554static void gen_popcntd(DisasContext *ctx)
1555{
1556    gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1557}
1558#endif
1559
1560/* prtyw: PowerPC 2.05 specification */
1561static void gen_prtyw(DisasContext *ctx)
1562{
1563    TCGv ra = cpu_gpr[rA(ctx->opcode)];
1564    TCGv rs = cpu_gpr[rS(ctx->opcode)];
1565    TCGv t0 = tcg_temp_new();
1566    tcg_gen_shri_tl(t0, rs, 16);
1567    tcg_gen_xor_tl(ra, rs, t0);
1568    tcg_gen_shri_tl(t0, ra, 8);
1569    tcg_gen_xor_tl(ra, ra, t0);
1570    tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1571    tcg_temp_free(t0);
1572}
1573
1574#if defined(TARGET_PPC64)
1575/* prtyd: PowerPC 2.05 specification */
1576static void gen_prtyd(DisasContext *ctx)
1577{
1578    TCGv ra = cpu_gpr[rA(ctx->opcode)];
1579    TCGv rs = cpu_gpr[rS(ctx->opcode)];
1580    TCGv t0 = tcg_temp_new();
1581    tcg_gen_shri_tl(t0, rs, 32);
1582    tcg_gen_xor_tl(ra, rs, t0);
1583    tcg_gen_shri_tl(t0, ra, 16);
1584    tcg_gen_xor_tl(ra, ra, t0);
1585    tcg_gen_shri_tl(t0, ra, 8);
1586    tcg_gen_xor_tl(ra, ra, t0);
1587    tcg_gen_andi_tl(ra, ra, 1);
1588    tcg_temp_free(t0);
1589}
1590#endif
1591
1592#if defined(TARGET_PPC64)
1593/* bpermd */
1594static void gen_bpermd(DisasContext *ctx)
1595{
1596    gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1597                      cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1598}
1599#endif
1600
1601#if defined(TARGET_PPC64)
1602/* extsw & extsw. */
1603GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1604
1605/* cntlzd */
1606static void gen_cntlzd(DisasContext *ctx)
1607{
1608    gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1609    if (unlikely(Rc(ctx->opcode) != 0))
1610        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1611}
1612#endif
1613
1614/***                             Integer rotate                            ***/
1615
1616/* rlwimi & rlwimi. */
1617static void gen_rlwimi(DisasContext *ctx)
1618{
1619    uint32_t mb, me, sh;
1620
1621    mb = MB(ctx->opcode);
1622    me = ME(ctx->opcode);
1623    sh = SH(ctx->opcode);
1624    if (likely(sh == (31-me) && mb <= me)) {
1625        tcg_gen_deposit_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1626                           cpu_gpr[rS(ctx->opcode)], sh, me - mb + 1);
1627    } else {
1628        target_ulong mask;
1629        TCGv t1;
1630        TCGv t0 = tcg_temp_new();
1631#if defined(TARGET_PPC64)
1632        tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1633            cpu_gpr[rS(ctx->opcode)], 32, 32);
1634        tcg_gen_rotli_i64(t0, t0, sh);
1635#else
1636        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1637#endif
1638#if defined(TARGET_PPC64)
1639        mb += 32;
1640        me += 32;
1641#endif
1642        mask = MASK(mb, me);
1643        t1 = tcg_temp_new();
1644        tcg_gen_andi_tl(t0, t0, mask);
1645        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1646        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1647        tcg_temp_free(t0);
1648        tcg_temp_free(t1);
1649    }
1650    if (unlikely(Rc(ctx->opcode) != 0))
1651        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1652}
1653
1654/* rlwinm & rlwinm. */
1655static void gen_rlwinm(DisasContext *ctx)
1656{
1657    uint32_t mb, me, sh;
1658
1659    sh = SH(ctx->opcode);
1660    mb = MB(ctx->opcode);
1661    me = ME(ctx->opcode);
1662
1663    if (likely(mb == 0 && me == (31 - sh))) {
1664        if (likely(sh == 0)) {
1665            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1666        } else {
1667            TCGv t0 = tcg_temp_new();
1668            tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1669            tcg_gen_shli_tl(t0, t0, sh);
1670            tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1671            tcg_temp_free(t0);
1672        }
1673    } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1674        TCGv t0 = tcg_temp_new();
1675        tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1676        tcg_gen_shri_tl(t0, t0, mb);
1677        tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1678        tcg_temp_free(t0);
1679    } else if (likely(mb == 0 && me == 31)) {
1680        TCGv_i32 t0 = tcg_temp_new_i32();
1681        tcg_gen_trunc_tl_i32(t0, cpu_gpr[rS(ctx->opcode)]);
1682        tcg_gen_rotli_i32(t0, t0, sh);
1683        tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t0);
1684        tcg_temp_free_i32(t0);
1685    } else {
1686        TCGv t0 = tcg_temp_new();
1687#if defined(TARGET_PPC64)
1688        tcg_gen_deposit_i64(t0, cpu_gpr[rS(ctx->opcode)],
1689            cpu_gpr[rS(ctx->opcode)], 32, 32);
1690        tcg_gen_rotli_i64(t0, t0, sh);
1691#else
1692        tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1693#endif
1694#if defined(TARGET_PPC64)
1695        mb += 32;
1696        me += 32;
1697#endif
1698        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1699        tcg_temp_free(t0);
1700    }
1701    if (unlikely(Rc(ctx->opcode) != 0))
1702        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1703}
1704
1705/* rlwnm & rlwnm. */
1706static void gen_rlwnm(DisasContext *ctx)
1707{
1708    uint32_t mb, me;
1709    mb = MB(ctx->opcode);
1710    me = ME(ctx->opcode);
1711
1712    if (likely(mb == 0 && me == 31)) {
1713        TCGv_i32 t0, t1;
1714        t0 = tcg_temp_new_i32();
1715        t1 = tcg_temp_new_i32();
1716        tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]);
1717        tcg_gen_trunc_tl_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1718        tcg_gen_andi_i32(t0, t0, 0x1f);
1719        tcg_gen_rotl_i32(t1, t1, t0);
1720        tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t1);
1721        tcg_temp_free_i32(t0);
1722        tcg_temp_free_i32(t1);
1723    } else {
1724        TCGv t0;
1725#if defined(TARGET_PPC64)
1726        TCGv t1;
1727#endif
1728
1729        t0 = tcg_temp_new();
1730        tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1731#if defined(TARGET_PPC64)
1732        t1 = tcg_temp_new_i64();
1733        tcg_gen_deposit_i64(t1, cpu_gpr[rS(ctx->opcode)],
1734                            cpu_gpr[rS(ctx->opcode)], 32, 32);
1735        tcg_gen_rotl_i64(t0, t1, t0);
1736        tcg_temp_free_i64(t1);
1737#else
1738        tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1739#endif
1740        if (unlikely(mb != 0 || me != 31)) {
1741#if defined(TARGET_PPC64)
1742            mb += 32;
1743            me += 32;
1744#endif
1745            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746        } else {
1747            tcg_gen_andi_tl(t0, t0, MASK(32, 63));
1748            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1749        }
1750        tcg_temp_free(t0);
1751    }
1752    if (unlikely(Rc(ctx->opcode) != 0))
1753        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1754}
1755
1756#if defined(TARGET_PPC64)
1757#define GEN_PPC64_R2(name, opc1, opc2)                                        \
1758static void glue(gen_, name##0)(DisasContext *ctx)                            \
1759{                                                                             \
1760    gen_##name(ctx, 0);                                                       \
1761}                                                                             \
1762                                                                              \
1763static void glue(gen_, name##1)(DisasContext *ctx)                            \
1764{                                                                             \
1765    gen_##name(ctx, 1);                                                       \
1766}
1767#define GEN_PPC64_R4(name, opc1, opc2)                                        \
1768static void glue(gen_, name##0)(DisasContext *ctx)                            \
1769{                                                                             \
1770    gen_##name(ctx, 0, 0);                                                    \
1771}                                                                             \
1772                                                                              \
1773static void glue(gen_, name##1)(DisasContext *ctx)                            \
1774{                                                                             \
1775    gen_##name(ctx, 0, 1);                                                    \
1776}                                                                             \
1777                                                                              \
1778static void glue(gen_, name##2)(DisasContext *ctx)                            \
1779{                                                                             \
1780    gen_##name(ctx, 1, 0);                                                    \
1781}                                                                             \
1782                                                                              \
1783static void glue(gen_, name##3)(DisasContext *ctx)                            \
1784{                                                                             \
1785    gen_##name(ctx, 1, 1);                                                    \
1786}
1787
1788static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1789                              uint32_t sh)
1790{
1791    if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1792        tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1793    } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1794        tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1795    } else {
1796        TCGv t0 = tcg_temp_new();
1797        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1798        if (likely(mb == 0 && me == 63)) {
1799            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1800        } else {
1801            tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1802        }
1803        tcg_temp_free(t0);
1804    }
1805    if (unlikely(Rc(ctx->opcode) != 0))
1806        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1807}
1808/* rldicl - rldicl. */
1809static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1810{
1811    uint32_t sh, mb;
1812
1813    sh = SH(ctx->opcode) | (shn << 5);
1814    mb = MB(ctx->opcode) | (mbn << 5);
1815    gen_rldinm(ctx, mb, 63, sh);
1816}
1817GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1818/* rldicr - rldicr. */
1819static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1820{
1821    uint32_t sh, me;
1822
1823    sh = SH(ctx->opcode) | (shn << 5);
1824    me = MB(ctx->opcode) | (men << 5);
1825    gen_rldinm(ctx, 0, me, sh);
1826}
1827GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1828/* rldic - rldic. */
1829static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1830{
1831    uint32_t sh, mb;
1832
1833    sh = SH(ctx->opcode) | (shn << 5);
1834    mb = MB(ctx->opcode) | (mbn << 5);
1835    gen_rldinm(ctx, mb, 63 - sh, sh);
1836}
1837GEN_PPC64_R4(rldic, 0x1E, 0x04);
1838
1839static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1840{
1841    TCGv t0;
1842
1843    t0 = tcg_temp_new();
1844    tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1845    tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1846    if (unlikely(mb != 0 || me != 63)) {
1847        tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1848    } else {
1849        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1850    }
1851    tcg_temp_free(t0);
1852    if (unlikely(Rc(ctx->opcode) != 0))
1853        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1854}
1855
1856/* rldcl - rldcl. */
1857static inline void gen_rldcl(DisasContext *ctx, int mbn)
1858{
1859    uint32_t mb;
1860
1861    mb = MB(ctx->opcode) | (mbn << 5);
1862    gen_rldnm(ctx, mb, 63);
1863}
1864GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1865/* rldcr - rldcr. */
1866static inline void gen_rldcr(DisasContext *ctx, int men)
1867{
1868    uint32_t me;
1869
1870    me = MB(ctx->opcode) | (men << 5);
1871    gen_rldnm(ctx, 0, me);
1872}
1873GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1874/* rldimi - rldimi. */
1875static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1876{
1877    uint32_t sh, mb, me;
1878
1879    sh = SH(ctx->opcode) | (shn << 5);
1880    mb = MB(ctx->opcode) | (mbn << 5);
1881    me = 63 - sh;
1882    if (unlikely(sh == 0 && mb == 0)) {
1883        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1884    } else {
1885        TCGv t0, t1;
1886        target_ulong mask;
1887
1888        t0 = tcg_temp_new();
1889        tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1890        t1 = tcg_temp_new();
1891        mask = MASK(mb, me);
1892        tcg_gen_andi_tl(t0, t0, mask);
1893        tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1894        tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1895        tcg_temp_free(t0);
1896        tcg_temp_free(t1);
1897    }
1898    if (unlikely(Rc(ctx->opcode) != 0))
1899        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1900}
1901GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1902#endif
1903
1904/***                             Integer shift                             ***/
1905
1906/* slw & slw. */
1907static void gen_slw(DisasContext *ctx)
1908{
1909    TCGv t0, t1;
1910
1911    t0 = tcg_temp_new();
1912    /* AND rS with a mask that is 0 when rB >= 0x20 */
1913#if defined(TARGET_PPC64)
1914    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1915    tcg_gen_sari_tl(t0, t0, 0x3f);
1916#else
1917    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1918    tcg_gen_sari_tl(t0, t0, 0x1f);
1919#endif
1920    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1921    t1 = tcg_temp_new();
1922    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1923    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1924    tcg_temp_free(t1);
1925    tcg_temp_free(t0);
1926    tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1927    if (unlikely(Rc(ctx->opcode) != 0))
1928        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1929}
1930
1931/* sraw & sraw. */
1932static void gen_sraw(DisasContext *ctx)
1933{
1934    gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1935                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1936    if (unlikely(Rc(ctx->opcode) != 0))
1937        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1938}
1939
1940/* srawi & srawi. */
1941static void gen_srawi(DisasContext *ctx)
1942{
1943    int sh = SH(ctx->opcode);
1944    TCGv dst = cpu_gpr[rA(ctx->opcode)];
1945    TCGv src = cpu_gpr[rS(ctx->opcode)];
1946    if (sh == 0) {
1947        tcg_gen_ext32s_tl(dst, src);
1948        tcg_gen_movi_tl(cpu_ca, 0);
1949    } else {
1950        TCGv t0;
1951        tcg_gen_ext32s_tl(dst, src);
1952        tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1953        t0 = tcg_temp_new();
1954        tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1955        tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1956        tcg_temp_free(t0);
1957        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1958        tcg_gen_sari_tl(dst, dst, sh);
1959    }
1960    if (unlikely(Rc(ctx->opcode) != 0)) {
1961        gen_set_Rc0(ctx, dst);
1962    }
1963}
1964
1965/* srw & srw. */
1966static void gen_srw(DisasContext *ctx)
1967{
1968    TCGv t0, t1;
1969
1970    t0 = tcg_temp_new();
1971    /* AND rS with a mask that is 0 when rB >= 0x20 */
1972#if defined(TARGET_PPC64)
1973    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1974    tcg_gen_sari_tl(t0, t0, 0x3f);
1975#else
1976    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1977    tcg_gen_sari_tl(t0, t0, 0x1f);
1978#endif
1979    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1980    tcg_gen_ext32u_tl(t0, t0);
1981    t1 = tcg_temp_new();
1982    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1983    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1984    tcg_temp_free(t1);
1985    tcg_temp_free(t0);
1986    if (unlikely(Rc(ctx->opcode) != 0))
1987        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1988}
1989
1990#if defined(TARGET_PPC64)
1991/* sld & sld. */
1992static void gen_sld(DisasContext *ctx)
1993{
1994    TCGv t0, t1;
1995
1996    t0 = tcg_temp_new();
1997    /* AND rS with a mask that is 0 when rB >= 0x40 */
1998    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1999    tcg_gen_sari_tl(t0, t0, 0x3f);
2000    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2001    t1 = tcg_temp_new();
2002    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2003    tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2004    tcg_temp_free(t1);
2005    tcg_temp_free(t0);
2006    if (unlikely(Rc(ctx->opcode) != 0))
2007        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2008}
2009
2010/* srad & srad. */
2011static void gen_srad(DisasContext *ctx)
2012{
2013    gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
2014                    cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2015    if (unlikely(Rc(ctx->opcode) != 0))
2016        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2017}
2018/* sradi & sradi. */
2019static inline void gen_sradi(DisasContext *ctx, int n)
2020{
2021    int sh = SH(ctx->opcode) + (n << 5);
2022    TCGv dst = cpu_gpr[rA(ctx->opcode)];
2023    TCGv src = cpu_gpr[rS(ctx->opcode)];
2024    if (sh == 0) {
2025        tcg_gen_mov_tl(dst, src);
2026        tcg_gen_movi_tl(cpu_ca, 0);
2027    } else {
2028        TCGv t0;
2029        tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
2030        t0 = tcg_temp_new();
2031        tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
2032        tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
2033        tcg_temp_free(t0);
2034        tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
2035        tcg_gen_sari_tl(dst, src, sh);
2036    }
2037    if (unlikely(Rc(ctx->opcode) != 0)) {
2038        gen_set_Rc0(ctx, dst);
2039    }
2040}
2041
2042static void gen_sradi0(DisasContext *ctx)
2043{
2044    gen_sradi(ctx, 0);
2045}
2046
2047static void gen_sradi1(DisasContext *ctx)
2048{
2049    gen_sradi(ctx, 1);
2050}
2051
2052/* srd & srd. */
2053static void gen_srd(DisasContext *ctx)
2054{
2055    TCGv t0, t1;
2056
2057    t0 = tcg_temp_new();
2058    /* AND rS with a mask that is 0 when rB >= 0x40 */
2059    tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2060    tcg_gen_sari_tl(t0, t0, 0x3f);
2061    tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2062    t1 = tcg_temp_new();
2063    tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2064    tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2065    tcg_temp_free(t1);
2066    tcg_temp_free(t0);
2067    if (unlikely(Rc(ctx->opcode) != 0))
2068        gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2069}
2070#endif
2071
2072#if defined(TARGET_PPC64)
2073static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2074{
2075    TCGv_i32 tmp = tcg_temp_new_i32();
2076    tcg_gen_trunc_tl_i32(tmp, cpu_fpscr);
2077    tcg_gen_shri_i32(cpu_crf[1], tmp, 28);
2078    tcg_temp_free_i32(tmp);
2079}
2080#else
2081static void gen_set_cr1_from_fpscr(DisasContext *ctx)
2082{
2083    tcg_gen_shri_tl(cpu_crf[1], cpu_fpscr, 28);
2084}
2085#endif
2086
2087/***                       Floating-Point arithmetic                       ***/
2088#define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type)           \
2089static void gen_f##name(DisasContext *ctx)                                    \
2090{                                                                             \
2091    if (unlikely(!ctx->fpu_enabled)) {                                        \
2092        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2093        return;                                                               \
2094    }                                                                         \
2095    /* NIP cannot be restored if the memory exception comes from an helper */ \
2096    gen_update_nip(ctx, ctx->nip - 4);                                        \
2097    gen_reset_fpstatus();                                                     \
2098    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env,                       \
2099                     cpu_fpr[rA(ctx->opcode)],                                \
2100                     cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);     \
2101    if (isfloat) {                                                            \
2102        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,                    \
2103                        cpu_fpr[rD(ctx->opcode)]);                            \
2104    }                                                                         \
2105    if (set_fprf) {                                                           \
2106        gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);                           \
2107    }                                                                         \
2108    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
2109        gen_set_cr1_from_fpscr(ctx);                                          \
2110    }                                                                         \
2111}
2112
2113#define GEN_FLOAT_ACB(name, op2, set_fprf, type)                              \
2114_GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type);                     \
2115_GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2116
2117#define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2118static void gen_f##name(DisasContext *ctx)                                    \
2119{                                                                             \
2120    if (unlikely(!ctx->fpu_enabled)) {                                        \
2121        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2122        return;                                                               \
2123    }                                                                         \
2124    /* NIP cannot be restored if the memory exception comes from an helper */ \
2125    gen_update_nip(ctx, ctx->nip - 4);                                        \
2126    gen_reset_fpstatus();                                                     \
2127    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env,                       \
2128                     cpu_fpr[rA(ctx->opcode)],                                \
2129                     cpu_fpr[rB(ctx->opcode)]);                               \
2130    if (isfloat) {                                                            \
2131        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,                    \
2132                        cpu_fpr[rD(ctx->opcode)]);                            \
2133    }                                                                         \
2134    if (set_fprf) {                                                           \
2135        gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);                           \
2136    }                                                                         \
2137    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
2138        gen_set_cr1_from_fpscr(ctx);                                          \
2139    }                                                                         \
2140}
2141#define GEN_FLOAT_AB(name, op2, inval, set_fprf, type)                        \
2142_GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2143_GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2144
2145#define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type)     \
2146static void gen_f##name(DisasContext *ctx)                                    \
2147{                                                                             \
2148    if (unlikely(!ctx->fpu_enabled)) {                                        \
2149        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2150        return;                                                               \
2151    }                                                                         \
2152    /* NIP cannot be restored if the memory exception comes from an helper */ \
2153    gen_update_nip(ctx, ctx->nip - 4);                                        \
2154    gen_reset_fpstatus();                                                     \
2155    gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env,                       \
2156                     cpu_fpr[rA(ctx->opcode)],                                \
2157                     cpu_fpr[rC(ctx->opcode)]);                               \
2158    if (isfloat) {                                                            \
2159        gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,                    \
2160                        cpu_fpr[rD(ctx->opcode)]);                            \
2161    }                                                                         \
2162    if (set_fprf) {                                                           \
2163        gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);                           \
2164    }                                                                         \
2165    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
2166        gen_set_cr1_from_fpscr(ctx);                                          \
2167    }                                                                         \
2168}
2169#define GEN_FLOAT_AC(name, op2, inval, set_fprf, type)                        \
2170_GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type);               \
2171_GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2172
2173#define GEN_FLOAT_B(name, op2, op3, set_fprf, type)                           \
2174static void gen_f##name(DisasContext *ctx)                                    \
2175{                                                                             \
2176    if (unlikely(!ctx->fpu_enabled)) {                                        \
2177        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2178        return;                                                               \
2179    }                                                                         \
2180    /* NIP cannot be restored if the memory exception comes from an helper */ \
2181    gen_update_nip(ctx, ctx->nip - 4);                                        \
2182    gen_reset_fpstatus();                                                     \
2183    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env,                     \
2184                       cpu_fpr[rB(ctx->opcode)]);                             \
2185    if (set_fprf) {                                                           \
2186        gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);                           \
2187    }                                                                         \
2188    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
2189        gen_set_cr1_from_fpscr(ctx);                                          \
2190    }                                                                         \
2191}
2192
2193#define GEN_FLOAT_BS(name, op1, op2, set_fprf, type)                          \
2194static void gen_f##name(DisasContext *ctx)                                    \
2195{                                                                             \
2196    if (unlikely(!ctx->fpu_enabled)) {                                        \
2197        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
2198        return;                                                               \
2199    }                                                                         \
2200    /* NIP cannot be restored if the memory exception comes from an helper */ \
2201    gen_update_nip(ctx, ctx->nip - 4);                                        \
2202    gen_reset_fpstatus();                                                     \
2203    gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env,                     \
2204                       cpu_fpr[rB(ctx->opcode)]);                             \
2205    if (set_fprf) {                                                           \
2206        gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);                           \
2207    }                                                                         \
2208    if (unlikely(Rc(ctx->opcode) != 0)) {                                     \
2209        gen_set_cr1_from_fpscr(ctx);                                          \
2210    }                                                                         \
2211}
2212
2213/* fadd - fadds */
2214GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2215/* fdiv - fdivs */
2216GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2217/* fmul - fmuls */
2218GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2219
2220/* fre */
2221GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2222
2223/* fres */
2224GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2225
2226/* frsqrte */
2227GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2228
2229/* frsqrtes */
2230static void gen_frsqrtes(DisasContext *ctx)
2231{
2232    if (unlikely(!ctx->fpu_enabled)) {
2233        gen_exception(ctx, POWERPC_EXCP_FPU);
2234        return;
2235    }
2236    /* NIP cannot be restored if the memory exception comes from an helper */
2237    gen_update_nip(ctx, ctx->nip - 4);
2238    gen_reset_fpstatus();
2239    gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2240                       cpu_fpr[rB(ctx->opcode)]);
2241    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2242                    cpu_fpr[rD(ctx->opcode)]);
2243    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2244    if (unlikely(Rc(ctx->opcode) != 0)) {
2245        gen_set_cr1_from_fpscr(ctx);
2246    }
2247}
2248
2249/* fsel */
2250_GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2251/* fsub - fsubs */
2252GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2253/* Optional: */
2254
2255/* fsqrt */
2256static void gen_fsqrt(DisasContext *ctx)
2257{
2258    if (unlikely(!ctx->fpu_enabled)) {
2259        gen_exception(ctx, POWERPC_EXCP_FPU);
2260        return;
2261    }
2262    /* NIP cannot be restored if the memory exception comes from an helper */
2263    gen_update_nip(ctx, ctx->nip - 4);
2264    gen_reset_fpstatus();
2265    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2266                     cpu_fpr[rB(ctx->opcode)]);
2267    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2268    if (unlikely(Rc(ctx->opcode) != 0)) {
2269        gen_set_cr1_from_fpscr(ctx);
2270    }
2271}
2272
2273static void gen_fsqrts(DisasContext *ctx)
2274{
2275    if (unlikely(!ctx->fpu_enabled)) {
2276        gen_exception(ctx, POWERPC_EXCP_FPU);
2277        return;
2278    }
2279    /* NIP cannot be restored if the memory exception comes from an helper */
2280    gen_update_nip(ctx, ctx->nip - 4);
2281    gen_reset_fpstatus();
2282    gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2283                     cpu_fpr[rB(ctx->opcode)]);
2284    gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2285                    cpu_fpr[rD(ctx->opcode)]);
2286    gen_compute_fprf(cpu_fpr[rD(ctx->opcode)]);
2287    if (unlikely(Rc(ctx->opcode) != 0)) {
2288        gen_set_cr1_from_fpscr(ctx);
2289    }
2290}
2291
2292/***                     Floating-Point multiply-and-add                   ***/
2293/* fmadd - fmadds */
2294GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2295/* fmsub - fmsubs */
2296GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2297/* fnmadd - fnmadds */
2298GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2299/* fnmsub - fnmsubs */
2300GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2301
2302/***                     Floating-Point round & convert                    ***/
2303/* fctiw */
2304GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2305/* fctiwu */
2306GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2307/* fctiwz */
2308GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2309/* fctiwuz */
2310GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2311/* frsp */
2312GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2313/* fcfid */
2314GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC2_FP_CVT_S64);
2315/* fcfids */
2316GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2317/* fcfidu */
2318GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2319/* fcfidus */
2320GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2321/* fctid */
2322GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC2_FP_CVT_S64);
2323/* fctidu */
2324GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2325/* fctidz */
2326GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC2_FP_CVT_S64);
2327/* fctidu */
2328GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2329
2330/* frin */
2331GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2332/* friz */
2333GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2334/* frip */
2335GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2336/* frim */
2337GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2338
2339static void gen_ftdiv(DisasContext *ctx)
2340{
2341    if (unlikely(!ctx->fpu_enabled)) {
2342        gen_exception(ctx, POWERPC_EXCP_FPU);
2343        return;
2344    }
2345    gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2346                     cpu_fpr[rB(ctx->opcode)]);
2347}
2348
2349static void gen_ftsqrt(DisasContext *ctx)
2350{
2351    if (unlikely(!ctx->fpu_enabled)) {
2352        gen_exception(ctx, POWERPC_EXCP_FPU);
2353        return;
2354    }
2355    gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2356}
2357
2358
2359
2360/***                         Floating-Point compare                        ***/
2361
2362/* fcmpo */
2363static void gen_fcmpo(DisasContext *ctx)
2364{
2365    TCGv_i32 crf;
2366    if (unlikely(!ctx->fpu_enabled)) {
2367        gen_exception(ctx, POWERPC_EXCP_FPU);
2368        return;
2369    }
2370    /* NIP cannot be restored if the memory exception comes from an helper */
2371    gen_update_nip(ctx, ctx->nip - 4);
2372    gen_reset_fpstatus();
2373    crf = tcg_const_i32(crfD(ctx->opcode));
2374    gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2375                     cpu_fpr[rB(ctx->opcode)], crf);
2376    tcg_temp_free_i32(crf);
2377    gen_helper_float_check_status(cpu_env);
2378}
2379
2380/* fcmpu */
2381static void gen_fcmpu(DisasContext *ctx)
2382{
2383    TCGv_i32 crf;
2384    if (unlikely(!ctx->fpu_enabled)) {
2385        gen_exception(ctx, POWERPC_EXCP_FPU);
2386        return;
2387    }
2388    /* NIP cannot be restored if the memory exception comes from an helper */
2389    gen_update_nip(ctx, ctx->nip - 4);
2390    gen_reset_fpstatus();
2391    crf = tcg_const_i32(crfD(ctx->opcode));
2392    gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2393                     cpu_fpr[rB(ctx->opcode)], crf);
2394    tcg_temp_free_i32(crf);
2395    gen_helper_float_check_status(cpu_env);
2396}
2397
2398/***                         Floating-point move                           ***/
2399/* fabs */
2400/* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2401static void gen_fabs(DisasContext *ctx)
2402{
2403    if (unlikely(!ctx->fpu_enabled)) {
2404        gen_exception(ctx, POWERPC_EXCP_FPU);
2405        return;
2406    }
2407    tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2408                     ~(1ULL << 63));
2409    if (unlikely(Rc(ctx->opcode))) {
2410        gen_set_cr1_from_fpscr(ctx);
2411    }
2412}
2413
2414/* fmr  - fmr. */
2415/* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2416static void gen_fmr(DisasContext *ctx)
2417{
2418    if (unlikely(!ctx->fpu_enabled)) {
2419        gen_exception(ctx, POWERPC_EXCP_FPU);
2420        return;
2421    }
2422    tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2423    if (unlikely(Rc(ctx->opcode))) {
2424        gen_set_cr1_from_fpscr(ctx);
2425    }
2426}
2427
2428/* fnabs */
2429/* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2430static void gen_fnabs(DisasContext *ctx)
2431{
2432    if (unlikely(!ctx->fpu_enabled)) {
2433        gen_exception(ctx, POWERPC_EXCP_FPU);
2434        return;
2435    }
2436    tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2437                    1ULL << 63);
2438    if (unlikely(Rc(ctx->opcode))) {
2439        gen_set_cr1_from_fpscr(ctx);
2440    }
2441}
2442
2443/* fneg */
2444/* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2445static void gen_fneg(DisasContext *ctx)
2446{
2447    if (unlikely(!ctx->fpu_enabled)) {
2448        gen_exception(ctx, POWERPC_EXCP_FPU);
2449        return;
2450    }
2451    tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2452                     1ULL << 63);
2453    if (unlikely(Rc(ctx->opcode))) {
2454        gen_set_cr1_from_fpscr(ctx);
2455    }
2456}
2457
2458/* fcpsgn: PowerPC 2.05 specification */
2459/* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2460static void gen_fcpsgn(DisasContext *ctx)
2461{
2462    if (unlikely(!ctx->fpu_enabled)) {
2463        gen_exception(ctx, POWERPC_EXCP_FPU);
2464        return;
2465    }
2466    tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2467                        cpu_fpr[rB(ctx->opcode)], 0, 63);
2468    if (unlikely(Rc(ctx->opcode))) {
2469        gen_set_cr1_from_fpscr(ctx);
2470    }
2471}
2472
2473static void gen_fmrgew(DisasContext *ctx)
2474{
2475    TCGv_i64 b0;
2476    if (unlikely(!ctx->fpu_enabled)) {
2477        gen_exception(ctx, POWERPC_EXCP_FPU);
2478        return;
2479    }
2480    b0 = tcg_temp_new_i64();
2481    tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2482    tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2483                        b0, 0, 32);
2484    tcg_temp_free_i64(b0);
2485}
2486
2487static void gen_fmrgow(DisasContext *ctx)
2488{
2489    if (unlikely(!ctx->fpu_enabled)) {
2490        gen_exception(ctx, POWERPC_EXCP_FPU);
2491        return;
2492    }
2493    tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2494                        cpu_fpr[rB(ctx->opcode)],
2495                        cpu_fpr[rA(ctx->opcode)],
2496                        32, 32);
2497}
2498
2499/***                  Floating-Point status & ctrl register                ***/
2500
2501/* mcrfs */
2502static void gen_mcrfs(DisasContext *ctx)
2503{
2504    TCGv tmp = tcg_temp_new();
2505    TCGv_i32 tmask;
2506    TCGv_i64 tnew_fpscr = tcg_temp_new_i64();
2507    int bfa;
2508    int nibble;
2509    int shift;
2510
2511    if (unlikely(!ctx->fpu_enabled)) {
2512        gen_exception(ctx, POWERPC_EXCP_FPU);
2513        return;
2514    }
2515    bfa = crfS(ctx->opcode);
2516    nibble = 7 - bfa;
2517    shift = 4 * nibble;
2518    tcg_gen_shri_tl(tmp, cpu_fpscr, shift);
2519    tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2520    tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2521    tcg_temp_free(tmp);
2522    tcg_gen_extu_tl_i64(tnew_fpscr, cpu_fpscr);
2523    /* Only the exception bits (including FX) should be cleared if read */
2524    tcg_gen_andi_i64(tnew_fpscr, tnew_fpscr, ~((0xF << shift) & FP_EX_CLEAR_BITS));
2525    /* FEX and VX need to be updated, so don't set fpscr directly */
2526    tmask = tcg_const_i32(1 << nibble);
2527    gen_helper_store_fpscr(cpu_env, tnew_fpscr, tmask);
2528    tcg_temp_free_i32(tmask);
2529    tcg_temp_free_i64(tnew_fpscr);
2530}
2531
2532/* mffs */
2533static void gen_mffs(DisasContext *ctx)
2534{
2535    if (unlikely(!ctx->fpu_enabled)) {
2536        gen_exception(ctx, POWERPC_EXCP_FPU);
2537        return;
2538    }
2539    gen_reset_fpstatus();
2540    tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2541    if (unlikely(Rc(ctx->opcode))) {
2542        gen_set_cr1_from_fpscr(ctx);
2543    }
2544}
2545
2546/* mtfsb0 */
2547static void gen_mtfsb0(DisasContext *ctx)
2548{
2549    uint8_t crb;
2550
2551    if (unlikely(!ctx->fpu_enabled)) {
2552        gen_exception(ctx, POWERPC_EXCP_FPU);
2553        return;
2554    }
2555    crb = 31 - crbD(ctx->opcode);
2556    gen_reset_fpstatus();
2557    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2558        TCGv_i32 t0;
2559        /* NIP cannot be restored if the memory exception comes from an helper */
2560        gen_update_nip(ctx, ctx->nip - 4);
2561        t0 = tcg_const_i32(crb);
2562        gen_helper_fpscr_clrbit(cpu_env, t0);
2563        tcg_temp_free_i32(t0);
2564    }
2565    if (unlikely(Rc(ctx->opcode) != 0)) {
2566        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2567        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2568    }
2569}
2570
2571/* mtfsb1 */
2572static void gen_mtfsb1(DisasContext *ctx)
2573{
2574    uint8_t crb;
2575
2576    if (unlikely(!ctx->fpu_enabled)) {
2577        gen_exception(ctx, POWERPC_EXCP_FPU);
2578        return;
2579    }
2580    crb = 31 - crbD(ctx->opcode);
2581    gen_reset_fpstatus();
2582    /* XXX: we pretend we can only do IEEE floating-point computations */
2583    if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2584        TCGv_i32 t0;
2585        /* NIP cannot be restored if the memory exception comes from an helper */
2586        gen_update_nip(ctx, ctx->nip - 4);
2587        t0 = tcg_const_i32(crb);
2588        gen_helper_fpscr_setbit(cpu_env, t0);
2589        tcg_temp_free_i32(t0);
2590    }
2591    if (unlikely(Rc(ctx->opcode) != 0)) {
2592        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2593        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2594    }
2595    /* We can raise a differed exception */
2596    gen_helper_float_check_status(cpu_env);
2597}
2598
2599/* mtfsf */
2600static void gen_mtfsf(DisasContext *ctx)
2601{
2602    TCGv_i32 t0;
2603    int flm, l, w;
2604
2605    if (unlikely(!ctx->fpu_enabled)) {
2606        gen_exception(ctx, POWERPC_EXCP_FPU);
2607        return;
2608    }
2609    flm = FPFLM(ctx->opcode);
2610    l = FPL(ctx->opcode);
2611    w = FPW(ctx->opcode);
2612    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2613        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2614        return;
2615    }
2616    /* NIP cannot be restored if the memory exception comes from an helper */
2617    gen_update_nip(ctx, ctx->nip - 4);
2618    gen_reset_fpstatus();
2619    if (l) {
2620        t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2621    } else {
2622        t0 = tcg_const_i32(flm << (w * 8));
2623    }
2624    gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2625    tcg_temp_free_i32(t0);
2626    if (unlikely(Rc(ctx->opcode) != 0)) {
2627        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2628        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2629    }
2630    /* We can raise a differed exception */
2631    gen_helper_float_check_status(cpu_env);
2632}
2633
2634/* mtfsfi */
2635static void gen_mtfsfi(DisasContext *ctx)
2636{
2637    int bf, sh, w;
2638    TCGv_i64 t0;
2639    TCGv_i32 t1;
2640
2641    if (unlikely(!ctx->fpu_enabled)) {
2642        gen_exception(ctx, POWERPC_EXCP_FPU);
2643        return;
2644    }
2645    w = FPW(ctx->opcode);
2646    bf = FPBF(ctx->opcode);
2647    if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2648        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2649        return;
2650    }
2651    sh = (8 * w) + 7 - bf;
2652    /* NIP cannot be restored if the memory exception comes from an helper */
2653    gen_update_nip(ctx, ctx->nip - 4);
2654    gen_reset_fpstatus();
2655    t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2656    t1 = tcg_const_i32(1 << sh);
2657    gen_helper_store_fpscr(cpu_env, t0, t1);
2658    tcg_temp_free_i64(t0);
2659    tcg_temp_free_i32(t1);
2660    if (unlikely(Rc(ctx->opcode) != 0)) {
2661        tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2662        tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2663    }
2664    /* We can raise a differed exception */
2665    gen_helper_float_check_status(cpu_env);
2666}
2667
2668/***                           Addressing modes                            ***/
2669/* Register indirect with immediate index : EA = (rA|0) + SIMM */
2670static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2671                                      target_long maskl)
2672{
2673    target_long simm = SIMM(ctx->opcode);
2674
2675    simm &= ~maskl;
2676    if (rA(ctx->opcode) == 0) {
2677        if (NARROW_MODE(ctx)) {
2678            simm = (uint32_t)simm;
2679        }
2680        tcg_gen_movi_tl(EA, simm);
2681    } else if (likely(simm != 0)) {
2682        tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2683        if (NARROW_MODE(ctx)) {
2684            tcg_gen_ext32u_tl(EA, EA);
2685        }
2686    } else {
2687        if (NARROW_MODE(ctx)) {
2688            tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2689        } else {
2690            tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2691        }
2692    }
2693}
2694
2695static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2696{
2697    if (rA(ctx->opcode) == 0) {
2698        if (NARROW_MODE(ctx)) {
2699            tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2700        } else {
2701            tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2702        }
2703    } else {
2704        tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2705        if (NARROW_MODE(ctx)) {
2706            tcg_gen_ext32u_tl(EA, EA);
2707        }
2708    }
2709}
2710
2711static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2712{
2713    if (rA(ctx->opcode) == 0) {
2714        tcg_gen_movi_tl(EA, 0);
2715    } else if (NARROW_MODE(ctx)) {
2716        tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2717    } else {
2718        tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2719    }
2720}
2721
2722static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2723                                target_long val)
2724{
2725    tcg_gen_addi_tl(ret, arg1, val);
2726    if (NARROW_MODE(ctx)) {
2727        tcg_gen_ext32u_tl(ret, ret);
2728    }
2729}
2730
2731static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2732{
2733    TCGLabel *l1 = gen_new_label();
2734    TCGv t0 = tcg_temp_new();
2735    TCGv_i32 t1, t2;
2736    /* NIP cannot be restored if the memory exception comes from an helper */
2737    gen_update_nip(ctx, ctx->nip - 4);
2738    tcg_gen_andi_tl(t0, EA, mask);
2739    tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2740    t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2741    t2 = tcg_const_i32(0);
2742    gen_helper_raise_exception_err(cpu_env, t1, t2);
2743    tcg_temp_free_i32(t1);
2744    tcg_temp_free_i32(t2);
2745    gen_set_label(l1);
2746    tcg_temp_free(t0);
2747}
2748
2749/***                             Integer load                              ***/
2750static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2751{
2752    tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2753}
2754
2755static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2756{
2757    TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2758    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2759}
2760
2761static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2762{
2763    TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
2764    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2765}
2766
2767static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2768{
2769    TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2770    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2771}
2772
2773static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2774{
2775    TCGv tmp = tcg_temp_new();
2776    gen_qemu_ld32u(ctx, tmp, addr);
2777    tcg_gen_extu_tl_i64(val, tmp);
2778    tcg_temp_free(tmp);
2779}
2780
2781static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2782{
2783    TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
2784    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
2785}
2786
2787static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2788{
2789    TCGv tmp = tcg_temp_new();
2790    gen_qemu_ld32s(ctx, tmp, addr);
2791    tcg_gen_ext_tl_i64(val, tmp);
2792    tcg_temp_free(tmp);
2793}
2794
2795static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2796{
2797    TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2798    tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
2799}
2800
2801static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2802{
2803    tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2804}
2805
2806static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2807{
2808    TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
2809    tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2810}
2811
2812static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2813{
2814    TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
2815    tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
2816}
2817
2818static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2819{
2820    TCGv tmp = tcg_temp_new();
2821    tcg_gen_trunc_i64_tl(tmp, val);
2822    gen_qemu_st32(ctx, tmp, addr);
2823    tcg_temp_free(tmp);
2824}
2825
2826static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2827{
2828    TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
2829    tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
2830}
2831
2832#define GEN_LD(name, ldop, opc, type)                                         \
2833static void glue(gen_, name)(DisasContext *ctx)                                       \
2834{                                                                             \
2835    TCGv EA;                                                                  \
2836    gen_set_access_type(ctx, ACCESS_INT);                                     \
2837    EA = tcg_temp_new();                                                      \
2838    gen_addr_imm_index(ctx, EA, 0);                                           \
2839    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2840    tcg_temp_free(EA);                                                        \
2841}
2842
2843#define GEN_LDU(name, ldop, opc, type)                                        \
2844static void glue(gen_, name##u)(DisasContext *ctx)                                    \
2845{                                                                             \
2846    TCGv EA;                                                                  \
2847    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2848                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2849        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2850        return;                                                               \
2851    }                                                                         \
2852    gen_set_access_type(ctx, ACCESS_INT);                                     \
2853    EA = tcg_temp_new();                                                      \
2854    if (type == PPC_64B)                                                      \
2855        gen_addr_imm_index(ctx, EA, 0x03);                                    \
2856    else                                                                      \
2857        gen_addr_imm_index(ctx, EA, 0);                                       \
2858    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2859    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2860    tcg_temp_free(EA);                                                        \
2861}
2862
2863#define GEN_LDUX(name, ldop, opc2, opc3, type)                                \
2864static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
2865{                                                                             \
2866    TCGv EA;                                                                  \
2867    if (unlikely(rA(ctx->opcode) == 0 ||                                      \
2868                 rA(ctx->opcode) == rD(ctx->opcode))) {                       \
2869        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
2870        return;                                                               \
2871    }                                                                         \
2872    gen_set_access_type(ctx, ACCESS_INT);                                     \
2873    EA = tcg_temp_new();                                                      \
2874    gen_addr_reg_index(ctx, EA);                                              \
2875    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2876    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
2877    tcg_temp_free(EA);                                                        \
2878}
2879
2880#define GEN_LDX_E(name, ldop, opc2, opc3, type, type2)                        \
2881static void glue(gen_, name##x)(DisasContext *ctx)                            \
2882{                                                                             \
2883    TCGv EA;                                                                  \
2884    gen_set_access_type(ctx, ACCESS_INT);                                     \
2885    EA = tcg_temp_new();                                                      \
2886    gen_addr_reg_index(ctx, EA);                                              \
2887    gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA);                       \
2888    tcg_temp_free(EA);                                                        \
2889}
2890#define GEN_LDX(name, ldop, opc2, opc3, type)                                 \
2891    GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2892
2893#define GEN_LDS(name, ldop, op, type)                                         \
2894GEN_LD(name, ldop, op | 0x20, type);                                          \
2895GEN_LDU(name, ldop, op | 0x21, type);                                         \
2896GEN_LDUX(name, ldop, 0x17, op | 0x01, type);                                  \
2897GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2898
2899/* lbz lbzu lbzux lbzx */
2900GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2901/* lha lhau lhaux lhax */
2902GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2903/* lhz lhzu lhzux lhzx */
2904GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2905/* lwz lwzu lwzux lwzx */
2906GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2907#if defined(TARGET_PPC64)
2908/* lwaux */
2909GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2910/* lwax */
2911GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2912/* ldux */
2913GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2914/* ldx */
2915GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2916
2917static void gen_ld(DisasContext *ctx)
2918{
2919    TCGv EA;
2920    if (Rc(ctx->opcode)) {
2921        if (unlikely(rA(ctx->opcode) == 0 ||
2922                     rA(ctx->opcode) == rD(ctx->opcode))) {
2923            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2924            return;
2925        }
2926    }
2927    gen_set_access_type(ctx, ACCESS_INT);
2928    EA = tcg_temp_new();
2929    gen_addr_imm_index(ctx, EA, 0x03);
2930    if (ctx->opcode & 0x02) {
2931        /* lwa (lwau is undefined) */
2932        gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2933    } else {
2934        /* ld - ldu */
2935        gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2936    }
2937    if (Rc(ctx->opcode))
2938        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2939    tcg_temp_free(EA);
2940}
2941
2942/* lq */
2943static void gen_lq(DisasContext *ctx)
2944{
2945    int ra, rd;
2946    TCGv EA;
2947
2948    /* lq is a legal user mode instruction starting in ISA 2.07 */
2949    bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2950    bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
2951
2952    if (!legal_in_user_mode && ctx->pr) {
2953        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2954        return;
2955    }
2956
2957    if (!le_is_supported && ctx->le_mode) {
2958        gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2959        return;
2960    }
2961
2962    ra = rA(ctx->opcode);
2963    rd = rD(ctx->opcode);
2964    if (unlikely((rd & 1) || rd == ra)) {
2965        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2966        return;
2967    }
2968
2969    gen_set_access_type(ctx, ACCESS_INT);
2970    EA = tcg_temp_new();
2971    gen_addr_imm_index(ctx, EA, 0x0F);
2972
2973    /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
2974       64-bit byteswap already. */
2975    if (unlikely(ctx->le_mode)) {
2976        gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2977        gen_addr_add(ctx, EA, EA, 8);
2978        gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2979    } else {
2980        gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2981        gen_addr_add(ctx, EA, EA, 8);
2982        gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2983    }
2984    tcg_temp_free(EA);
2985}
2986#endif
2987
2988/***                              Integer store                            ***/
2989#define GEN_ST(name, stop, opc, type)                                         \
2990static void glue(gen_, name)(DisasContext *ctx)                                       \
2991{                                                                             \
2992    TCGv EA;                                                                  \
2993    gen_set_access_type(ctx, ACCESS_INT);                                     \
2994    EA = tcg_temp_new();                                                      \
2995    gen_addr_imm_index(ctx, EA, 0);                                           \
2996    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
2997    tcg_temp_free(EA);                                                        \
2998}
2999
3000#define GEN_STU(name, stop, opc, type)                                        \
3001static void glue(gen_, stop##u)(DisasContext *ctx)                                    \
3002{                                                                             \
3003    TCGv EA;                                                                  \
3004    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3005        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3006        return;                                                               \
3007    }                                                                         \
3008    gen_set_access_type(ctx, ACCESS_INT);                                     \
3009    EA = tcg_temp_new();                                                      \
3010    if (type == PPC_64B)                                                      \
3011        gen_addr_imm_index(ctx, EA, 0x03);                                    \
3012    else                                                                      \
3013        gen_addr_imm_index(ctx, EA, 0);                                       \
3014    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3015    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3016    tcg_temp_free(EA);                                                        \
3017}
3018
3019#define GEN_STUX(name, stop, opc2, opc3, type)                                \
3020static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3021{                                                                             \
3022    TCGv EA;                                                                  \
3023    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3024        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3025        return;                                                               \
3026    }                                                                         \
3027    gen_set_access_type(ctx, ACCESS_INT);                                     \
3028    EA = tcg_temp_new();                                                      \
3029    gen_addr_reg_index(ctx, EA);                                              \
3030    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3031    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3032    tcg_temp_free(EA);                                                        \
3033}
3034
3035#define GEN_STX_E(name, stop, opc2, opc3, type, type2)                        \
3036static void glue(gen_, name##x)(DisasContext *ctx)                            \
3037{                                                                             \
3038    TCGv EA;                                                                  \
3039    gen_set_access_type(ctx, ACCESS_INT);                                     \
3040    EA = tcg_temp_new();                                                      \
3041    gen_addr_reg_index(ctx, EA);                                              \
3042    gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA);                       \
3043    tcg_temp_free(EA);                                                        \
3044}
3045#define GEN_STX(name, stop, opc2, opc3, type)                                 \
3046    GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
3047
3048#define GEN_STS(name, stop, op, type)                                         \
3049GEN_ST(name, stop, op | 0x20, type);                                          \
3050GEN_STU(name, stop, op | 0x21, type);                                         \
3051GEN_STUX(name, stop, 0x17, op | 0x01, type);                                  \
3052GEN_STX(name, stop, 0x17, op | 0x00, type)
3053
3054/* stb stbu stbux stbx */
3055GEN_STS(stb, st8, 0x06, PPC_INTEGER);
3056/* sth sthu sthux sthx */
3057GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
3058/* stw stwu stwux stwx */
3059GEN_STS(stw, st32, 0x04, PPC_INTEGER);
3060#if defined(TARGET_PPC64)
3061GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
3062GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
3063
3064static void gen_std(DisasContext *ctx)
3065{
3066    int rs;
3067    TCGv EA;
3068
3069    rs = rS(ctx->opcode);
3070    if ((ctx->opcode & 0x3) == 0x2) { /* stq */
3071
3072        bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3073        bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0;
3074
3075        if (!legal_in_user_mode && ctx->pr) {
3076            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3077            return;
3078        }
3079
3080        if (!le_is_supported && ctx->le_mode) {
3081            gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
3082            return;
3083        }
3084
3085        if (unlikely(rs & 1)) {
3086            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3087            return;
3088        }
3089        gen_set_access_type(ctx, ACCESS_INT);
3090        EA = tcg_temp_new();
3091        gen_addr_imm_index(ctx, EA, 0x03);
3092
3093        /* We only need to swap high and low halves. gen_qemu_st64 does
3094           necessary 64-bit byteswap already. */
3095        if (unlikely(ctx->le_mode)) {
3096            gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3097            gen_addr_add(ctx, EA, EA, 8);
3098            gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3099        } else {
3100            gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3101            gen_addr_add(ctx, EA, EA, 8);
3102            gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3103        }
3104        tcg_temp_free(EA);
3105    } else {
3106        /* std / stdu*/
3107        if (Rc(ctx->opcode)) {
3108            if (unlikely(rA(ctx->opcode) == 0)) {
3109                gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3110                return;
3111            }
3112        }
3113        gen_set_access_type(ctx, ACCESS_INT);
3114        EA = tcg_temp_new();
3115        gen_addr_imm_index(ctx, EA, 0x03);
3116        gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3117        if (Rc(ctx->opcode))
3118            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3119        tcg_temp_free(EA);
3120    }
3121}
3122#endif
3123/***                Integer load and store with byte reverse               ***/
3124
3125/* lhbrx */
3126static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3127{
3128    TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3129    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3130}
3131GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3132
3133/* lwbrx */
3134static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3135{
3136    TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3137    tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
3138}
3139GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3140
3141#if defined(TARGET_PPC64)
3142/* ldbrx */
3143static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3144{
3145    TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3146    tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
3147}
3148GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3149#endif  /* TARGET_PPC64 */
3150
3151/* sthbrx */
3152static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3153{
3154    TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3155    tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3156}
3157GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3158
3159/* stwbrx */
3160static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3161{
3162    TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3163    tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
3164}
3165GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3166
3167#if defined(TARGET_PPC64)
3168/* stdbrx */
3169static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3170{
3171    TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
3172    tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
3173}
3174GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3175#endif  /* TARGET_PPC64 */
3176
3177/***                    Integer load and store multiple                    ***/
3178
3179/* lmw */
3180static void gen_lmw(DisasContext *ctx)
3181{
3182    TCGv t0;
3183    TCGv_i32 t1;
3184    gen_set_access_type(ctx, ACCESS_INT);
3185    /* NIP cannot be restored if the memory exception comes from an helper */
3186    gen_update_nip(ctx, ctx->nip - 4);
3187    t0 = tcg_temp_new();
3188    t1 = tcg_const_i32(rD(ctx->opcode));
3189    gen_addr_imm_index(ctx, t0, 0);
3190    gen_helper_lmw(cpu_env, t0, t1);
3191    tcg_temp_free(t0);
3192    tcg_temp_free_i32(t1);
3193}
3194
3195/* stmw */
3196static void gen_stmw(DisasContext *ctx)
3197{
3198    TCGv t0;
3199    TCGv_i32 t1;
3200    gen_set_access_type(ctx, ACCESS_INT);
3201    /* NIP cannot be restored if the memory exception comes from an helper */
3202    gen_update_nip(ctx, ctx->nip - 4);
3203    t0 = tcg_temp_new();
3204    t1 = tcg_const_i32(rS(ctx->opcode));
3205    gen_addr_imm_index(ctx, t0, 0);
3206    gen_helper_stmw(cpu_env, t0, t1);
3207    tcg_temp_free(t0);
3208    tcg_temp_free_i32(t1);
3209}
3210
3211/***                    Integer load and store strings                     ***/
3212
3213/* lswi */
3214/* PowerPC32 specification says we must generate an exception if
3215 * rA is in the range of registers to be loaded.
3216 * In an other hand, IBM says this is valid, but rA won't be loaded.
3217 * For now, I'll follow the spec...
3218 */
3219static void gen_lswi(DisasContext *ctx)
3220{
3221    TCGv t0;
3222    TCGv_i32 t1, t2;
3223    int nb = NB(ctx->opcode);
3224    int start = rD(ctx->opcode);
3225    int ra = rA(ctx->opcode);
3226    int nr;
3227
3228    if (nb == 0)
3229        nb = 32;
3230    nr = (nb + 3) / 4;
3231    if (unlikely(lsw_reg_in_range(start, nr, ra))) {
3232        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3233        return;
3234    }
3235    gen_set_access_type(ctx, ACCESS_INT);
3236    /* NIP cannot be restored if the memory exception comes from an helper */
3237    gen_update_nip(ctx, ctx->nip - 4);
3238    t0 = tcg_temp_new();
3239    gen_addr_register(ctx, t0);
3240    t1 = tcg_const_i32(nb);
3241    t2 = tcg_const_i32(start);
3242    gen_helper_lsw(cpu_env, t0, t1, t2);
3243    tcg_temp_free(t0);
3244    tcg_temp_free_i32(t1);
3245    tcg_temp_free_i32(t2);
3246}
3247
3248/* lswx */
3249static void gen_lswx(DisasContext *ctx)
3250{
3251    TCGv t0;
3252    TCGv_i32 t1, t2, t3;
3253    gen_set_access_type(ctx, ACCESS_INT);
3254    /* NIP cannot be restored if the memory exception comes from an helper */
3255    gen_update_nip(ctx, ctx->nip - 4);
3256    t0 = tcg_temp_new();
3257    gen_addr_reg_index(ctx, t0);
3258    t1 = tcg_const_i32(rD(ctx->opcode));
3259    t2 = tcg_const_i32(rA(ctx->opcode));
3260    t3 = tcg_const_i32(rB(ctx->opcode));
3261    gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3262    tcg_temp_free(t0);
3263    tcg_temp_free_i32(t1);
3264    tcg_temp_free_i32(t2);
3265    tcg_temp_free_i32(t3);
3266}
3267
3268/* stswi */
3269static void gen_stswi(DisasContext *ctx)
3270{
3271    TCGv t0;
3272    TCGv_i32 t1, t2;
3273    int nb = NB(ctx->opcode);
3274    gen_set_access_type(ctx, ACCESS_INT);
3275    /* NIP cannot be restored if the memory exception comes from an helper */
3276    gen_update_nip(ctx, ctx->nip - 4);
3277    t0 = tcg_temp_new();
3278    gen_addr_register(ctx, t0);
3279    if (nb == 0)
3280        nb = 32;
3281    t1 = tcg_const_i32(nb);
3282    t2 = tcg_const_i32(rS(ctx->opcode));
3283    gen_helper_stsw(cpu_env, t0, t1, t2);
3284    tcg_temp_free(t0);
3285    tcg_temp_free_i32(t1);
3286    tcg_temp_free_i32(t2);
3287}
3288
3289/* stswx */
3290static void gen_stswx(DisasContext *ctx)
3291{
3292    TCGv t0;
3293    TCGv_i32 t1, t2;
3294    gen_set_access_type(ctx, ACCESS_INT);
3295    /* NIP cannot be restored if the memory exception comes from an helper */
3296    gen_update_nip(ctx, ctx->nip - 4);
3297    t0 = tcg_temp_new();
3298    gen_addr_reg_index(ctx, t0);
3299    t1 = tcg_temp_new_i32();
3300    tcg_gen_trunc_tl_i32(t1, cpu_xer);
3301    tcg_gen_andi_i32(t1, t1, 0x7F);
3302    t2 = tcg_const_i32(rS(ctx->opcode));
3303    gen_helper_stsw(cpu_env, t0, t1, t2);
3304    tcg_temp_free(t0);
3305    tcg_temp_free_i32(t1);
3306    tcg_temp_free_i32(t2);
3307}
3308
3309/***                        Memory synchronisation                         ***/
3310/* eieio */
3311static void gen_eieio(DisasContext *ctx)
3312{
3313}
3314
3315/* isync */
3316static void gen_isync(DisasContext *ctx)
3317{
3318    gen_stop_exception(ctx);
3319}
3320
3321#define LARX(name, len, loadop)                                      \
3322static void gen_##name(DisasContext *ctx)                            \
3323{                                                                    \
3324    TCGv t0;                                                         \
3325    TCGv gpr = cpu_gpr[rD(ctx->opcode)];                             \
3326    gen_set_access_type(ctx, ACCESS_RES);                            \
3327    t0 = tcg_temp_local_new();                                       \
3328    gen_addr_reg_index(ctx, t0);                                     \
3329    if ((len) > 1) {                                                 \
3330        gen_check_align(ctx, t0, (len)-1);                           \
3331    }                                                                \
3332    gen_qemu_##loadop(ctx, gpr, t0);                                 \
3333    tcg_gen_mov_tl(cpu_reserve, t0);                                 \
3334    tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3335    tcg_temp_free(t0);                                               \
3336}
3337
3338/* lwarx */
3339LARX(lbarx, 1, ld8u);
3340LARX(lharx, 2, ld16u);
3341LARX(lwarx, 4, ld32u);
3342
3343
3344#if defined(CONFIG_USER_ONLY)
3345static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3346                                  int reg, int size)
3347{
3348    TCGv t0 = tcg_temp_new();
3349    uint32_t save_exception = ctx->exception;
3350
3351    tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3352    tcg_gen_movi_tl(t0, (size << 5) | reg);
3353    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3354    tcg_temp_free(t0);
3355    gen_update_nip(ctx, ctx->nip-4);
3356    ctx->exception = POWERPC_EXCP_BRANCH;
3357    gen_exception(ctx, POWERPC_EXCP_STCX);
3358    ctx->exception = save_exception;
3359}
3360#else
3361static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3362                                  int reg, int size)
3363{
3364    TCGLabel *l1;
3365
3366    tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3367    l1 = gen_new_label();
3368    tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3369    tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3370#if defined(TARGET_PPC64)
3371    if (size == 8) {
3372        gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3373    } else
3374#endif
3375    if (size == 4) {
3376        gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3377    } else if (size == 2) {
3378        gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3379#if defined(TARGET_PPC64)
3380    } else if (size == 16) {
3381        TCGv gpr1, gpr2 , EA8;
3382        if (unlikely(ctx->le_mode)) {
3383            gpr1 = cpu_gpr[reg+1];
3384            gpr2 = cpu_gpr[reg];
3385        } else {
3386            gpr1 = cpu_gpr[reg];
3387            gpr2 = cpu_gpr[reg+1];
3388        }
3389        gen_qemu_st64(ctx, gpr1, EA);
3390        EA8 = tcg_temp_local_new();
3391        gen_addr_add(ctx, EA8, EA, 8);
3392        gen_qemu_st64(ctx, gpr2, EA8);
3393        tcg_temp_free(EA8);
3394#endif
3395    } else {
3396        gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3397    }
3398    gen_set_label(l1);
3399    tcg_gen_movi_tl(cpu_reserve, -1);
3400}
3401#endif
3402
3403#define STCX(name, len)                                   \
3404static void gen_##name(DisasContext *ctx)                 \
3405{                                                         \
3406    TCGv t0;                                              \
3407    if (unlikely((len == 16) && (rD(ctx->opcode) & 1))) { \
3408        gen_inval_exception(ctx,                          \
3409                            POWERPC_EXCP_INVAL_INVAL);    \
3410        return;                                           \
3411    }                                                     \
3412    gen_set_access_type(ctx, ACCESS_RES);                 \
3413    t0 = tcg_temp_local_new();                            \
3414    gen_addr_reg_index(ctx, t0);                          \
3415    if (len > 1) {                                        \
3416        gen_check_align(ctx, t0, (len)-1);                \
3417    }                                                     \
3418    gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3419    tcg_temp_free(t0);                                    \
3420}
3421
3422STCX(stbcx_, 1);
3423STCX(sthcx_, 2);
3424STCX(stwcx_, 4);
3425
3426#if defined(TARGET_PPC64)
3427/* ldarx */
3428LARX(ldarx, 8, ld64);
3429
3430/* lqarx */
3431static void gen_lqarx(DisasContext *ctx)
3432{
3433    TCGv EA;
3434    int rd = rD(ctx->opcode);
3435    TCGv gpr1, gpr2;
3436
3437    if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
3438                 (rd == rB(ctx->opcode)))) {
3439        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3440        return;
3441    }
3442
3443    gen_set_access_type(ctx, ACCESS_RES);
3444    EA = tcg_temp_local_new();
3445    gen_addr_reg_index(ctx, EA);
3446    gen_check_align(ctx, EA, 15);
3447    if (unlikely(ctx->le_mode)) {
3448        gpr1 = cpu_gpr[rd+1];
3449        gpr2 = cpu_gpr[rd];
3450    } else {
3451        gpr1 = cpu_gpr[rd];
3452        gpr2 = cpu_gpr[rd+1];
3453    }
3454    gen_qemu_ld64(ctx, gpr1, EA);
3455    tcg_gen_mov_tl(cpu_reserve, EA);
3456
3457    gen_addr_add(ctx, EA, EA, 8);
3458    gen_qemu_ld64(ctx, gpr2, EA);
3459
3460    tcg_gen_st_tl(gpr1, cpu_env, offsetof(CPUPPCState, reserve_val));
3461    tcg_gen_st_tl(gpr2, cpu_env, offsetof(CPUPPCState, reserve_val2));
3462
3463    tcg_temp_free(EA);
3464}
3465
3466/* stdcx. */
3467STCX(stdcx_, 8);
3468STCX(stqcx_, 16);
3469#endif /* defined(TARGET_PPC64) */
3470
3471/* sync */
3472static void gen_sync(DisasContext *ctx)
3473{
3474}
3475
3476/* wait */
3477static void gen_wait(DisasContext *ctx)
3478{
3479    TCGv_i32 t0 = tcg_temp_new_i32();
3480    tcg_gen_st_i32(t0, cpu_env,
3481                   -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3482    tcg_temp_free_i32(t0);
3483    /* Stop translation, as the CPU is supposed to sleep from now */
3484    gen_exception_err(ctx, EXCP_HLT, 1);
3485}
3486
3487/***                         Floating-point load                           ***/
3488#define GEN_LDF(name, ldop, opc, type)                                        \
3489static void glue(gen_, name)(DisasContext *ctx)                                       \
3490{                                                                             \
3491    TCGv EA;                                                                  \
3492    if (unlikely(!ctx->fpu_enabled)) {                                        \
3493        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3494        return;                                                               \
3495    }                                                                         \
3496    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3497    EA = tcg_temp_new();                                                      \
3498    gen_addr_imm_index(ctx, EA, 0);                                           \
3499    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3500    tcg_temp_free(EA);                                                        \
3501}
3502
3503#define GEN_LDUF(name, ldop, opc, type)                                       \
3504static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3505{                                                                             \
3506    TCGv EA;                                                                  \
3507    if (unlikely(!ctx->fpu_enabled)) {                                        \
3508        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3509        return;                                                               \
3510    }                                                                         \
3511    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3512        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3513        return;                                                               \
3514    }                                                                         \
3515    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3516    EA = tcg_temp_new();                                                      \
3517    gen_addr_imm_index(ctx, EA, 0);                                           \
3518    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3519    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3520    tcg_temp_free(EA);                                                        \
3521}
3522
3523#define GEN_LDUXF(name, ldop, opc, type)                                      \
3524static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3525{                                                                             \
3526    TCGv EA;                                                                  \
3527    if (unlikely(!ctx->fpu_enabled)) {                                        \
3528        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3529        return;                                                               \
3530    }                                                                         \
3531    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3532        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3533        return;                                                               \
3534    }                                                                         \
3535    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3536    EA = tcg_temp_new();                                                      \
3537    gen_addr_reg_index(ctx, EA);                                              \
3538    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3539    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3540    tcg_temp_free(EA);                                                        \
3541}
3542
3543#define GEN_LDXF(name, ldop, opc2, opc3, type)                                \
3544static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3545{                                                                             \
3546    TCGv EA;                                                                  \
3547    if (unlikely(!ctx->fpu_enabled)) {                                        \
3548        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3549        return;                                                               \
3550    }                                                                         \
3551    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3552    EA = tcg_temp_new();                                                      \
3553    gen_addr_reg_index(ctx, EA);                                              \
3554    gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA);                       \
3555    tcg_temp_free(EA);                                                        \
3556}
3557
3558#define GEN_LDFS(name, ldop, op, type)                                        \
3559GEN_LDF(name, ldop, op | 0x20, type);                                         \
3560GEN_LDUF(name, ldop, op | 0x21, type);                                        \
3561GEN_LDUXF(name, ldop, op | 0x01, type);                                       \
3562GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3563
3564static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3565{
3566    TCGv t0 = tcg_temp_new();
3567    TCGv_i32 t1 = tcg_temp_new_i32();
3568    gen_qemu_ld32u(ctx, t0, arg2);
3569    tcg_gen_trunc_tl_i32(t1, t0);
3570    tcg_temp_free(t0);
3571    gen_helper_float32_to_float64(arg1, cpu_env, t1);
3572    tcg_temp_free_i32(t1);
3573}
3574
3575 /* lfd lfdu lfdux lfdx */
3576GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3577 /* lfs lfsu lfsux lfsx */
3578GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3579
3580/* lfdp */
3581static void gen_lfdp(DisasContext *ctx)
3582{
3583    TCGv EA;
3584    if (unlikely(!ctx->fpu_enabled)) {
3585        gen_exception(ctx, POWERPC_EXCP_FPU);
3586        return;
3587    }
3588    gen_set_access_type(ctx, ACCESS_FLOAT);
3589    EA = tcg_temp_new();
3590    gen_addr_imm_index(ctx, EA, 0);
3591    /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3592       64-bit byteswap already. */
3593    if (unlikely(ctx->le_mode)) {
3594        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3595        tcg_gen_addi_tl(EA, EA, 8);
3596        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3597    } else {
3598        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3599        tcg_gen_addi_tl(EA, EA, 8);
3600        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3601    }
3602    tcg_temp_free(EA);
3603}
3604
3605/* lfdpx */
3606static void gen_lfdpx(DisasContext *ctx)
3607{
3608    TCGv EA;
3609    if (unlikely(!ctx->fpu_enabled)) {
3610        gen_exception(ctx, POWERPC_EXCP_FPU);
3611        return;
3612    }
3613    gen_set_access_type(ctx, ACCESS_FLOAT);
3614    EA = tcg_temp_new();
3615    gen_addr_reg_index(ctx, EA);
3616    /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
3617       64-bit byteswap already. */
3618    if (unlikely(ctx->le_mode)) {
3619        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3620        tcg_gen_addi_tl(EA, EA, 8);
3621        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3622    } else {
3623        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3624        tcg_gen_addi_tl(EA, EA, 8);
3625        gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3626    }
3627    tcg_temp_free(EA);
3628}
3629
3630/* lfiwax */
3631static void gen_lfiwax(DisasContext *ctx)
3632{
3633    TCGv EA;
3634    TCGv t0;
3635    if (unlikely(!ctx->fpu_enabled)) {
3636        gen_exception(ctx, POWERPC_EXCP_FPU);
3637        return;
3638    }
3639    gen_set_access_type(ctx, ACCESS_FLOAT);
3640    EA = tcg_temp_new();
3641    t0 = tcg_temp_new();
3642    gen_addr_reg_index(ctx, EA);
3643    gen_qemu_ld32s(ctx, t0, EA);
3644    tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3645    tcg_temp_free(EA);
3646    tcg_temp_free(t0);
3647}
3648
3649/* lfiwzx */
3650static void gen_lfiwzx(DisasContext *ctx)
3651{
3652    TCGv EA;
3653    if (unlikely(!ctx->fpu_enabled)) {
3654        gen_exception(ctx, POWERPC_EXCP_FPU);
3655        return;
3656    }
3657    gen_set_access_type(ctx, ACCESS_FLOAT);
3658    EA = tcg_temp_new();
3659    gen_addr_reg_index(ctx, EA);
3660    gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3661    tcg_temp_free(EA);
3662}
3663/***                         Floating-point store                          ***/
3664#define GEN_STF(name, stop, opc, type)                                        \
3665static void glue(gen_, name)(DisasContext *ctx)                                       \
3666{                                                                             \
3667    TCGv EA;                                                                  \
3668    if (unlikely(!ctx->fpu_enabled)) {                                        \
3669        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3670        return;                                                               \
3671    }                                                                         \
3672    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3673    EA = tcg_temp_new();                                                      \
3674    gen_addr_imm_index(ctx, EA, 0);                                           \
3675    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3676    tcg_temp_free(EA);                                                        \
3677}
3678
3679#define GEN_STUF(name, stop, opc, type)                                       \
3680static void glue(gen_, name##u)(DisasContext *ctx)                                    \
3681{                                                                             \
3682    TCGv EA;                                                                  \
3683    if (unlikely(!ctx->fpu_enabled)) {                                        \
3684        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3685        return;                                                               \
3686    }                                                                         \
3687    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3688        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3689        return;                                                               \
3690    }                                                                         \
3691    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3692    EA = tcg_temp_new();                                                      \
3693    gen_addr_imm_index(ctx, EA, 0);                                           \
3694    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3695    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3696    tcg_temp_free(EA);                                                        \
3697}
3698
3699#define GEN_STUXF(name, stop, opc, type)                                      \
3700static void glue(gen_, name##ux)(DisasContext *ctx)                                   \
3701{                                                                             \
3702    TCGv EA;                                                                  \
3703    if (unlikely(!ctx->fpu_enabled)) {                                        \
3704        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3705        return;                                                               \
3706    }                                                                         \
3707    if (unlikely(rA(ctx->opcode) == 0)) {                                     \
3708        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);                   \
3709        return;                                                               \
3710    }                                                                         \
3711    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3712    EA = tcg_temp_new();                                                      \
3713    gen_addr_reg_index(ctx, EA);                                              \
3714    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3715    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);                             \
3716    tcg_temp_free(EA);                                                        \
3717}
3718
3719#define GEN_STXF(name, stop, opc2, opc3, type)                                \
3720static void glue(gen_, name##x)(DisasContext *ctx)                                    \
3721{                                                                             \
3722    TCGv EA;                                                                  \
3723    if (unlikely(!ctx->fpu_enabled)) {                                        \
3724        gen_exception(ctx, POWERPC_EXCP_FPU);                                 \
3725        return;                                                               \
3726    }                                                                         \
3727    gen_set_access_type(ctx, ACCESS_FLOAT);                                   \
3728    EA = tcg_temp_new();                                                      \
3729    gen_addr_reg_index(ctx, EA);                                              \
3730    gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA);                       \
3731    tcg_temp_free(EA);                                                        \
3732}
3733
3734#define GEN_STFS(name, stop, op, type)                                        \
3735GEN_STF(name, stop, op | 0x20, type);                                         \
3736GEN_STUF(name, stop, op | 0x21, type);                                        \
3737GEN_STUXF(name, stop, op | 0x01, type);                                       \
3738GEN_STXF(name, stop, 0x17, op | 0x00, type)
3739
3740static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3741{
3742    TCGv_i32 t0 = tcg_temp_new_i32();
3743    TCGv t1 = tcg_temp_new();
3744    gen_helper_float64_to_float32(t0, cpu_env, arg1);
3745    tcg_gen_extu_i32_tl(t1, t0);
3746    tcg_temp_free_i32(t0);
3747    gen_qemu_st32(ctx, t1, arg2);
3748    tcg_temp_free(t1);
3749}
3750
3751/* stfd stfdu stfdux stfdx */
3752GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3753/* stfs stfsu stfsux stfsx */
3754GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3755
3756/* stfdp */
3757static void gen_stfdp(DisasContext *ctx)
3758{
3759    TCGv EA;
3760    if (unlikely(!ctx->fpu_enabled)) {
3761        gen_exception(ctx, POWERPC_EXCP_FPU);
3762        return;
3763    }
3764    gen_set_access_type(ctx, ACCESS_FLOAT);
3765    EA = tcg_temp_new();
3766    gen_addr_imm_index(ctx, EA, 0);
3767    /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3768       64-bit byteswap already. */
3769    if (unlikely(ctx->le_mode)) {
3770        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3771        tcg_gen_addi_tl(EA, EA, 8);
3772        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3773    } else {
3774        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3775        tcg_gen_addi_tl(EA, EA, 8);
3776        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3777    }
3778    tcg_temp_free(EA);
3779}
3780
3781/* stfdpx */
3782static void gen_stfdpx(DisasContext *ctx)
3783{
3784    TCGv EA;
3785    if (unlikely(!ctx->fpu_enabled)) {
3786        gen_exception(ctx, POWERPC_EXCP_FPU);
3787        return;
3788    }
3789    gen_set_access_type(ctx, ACCESS_FLOAT);
3790    EA = tcg_temp_new();
3791    gen_addr_reg_index(ctx, EA);
3792    /* We only need to swap high and low halves. gen_qemu_st64 does necessary
3793       64-bit byteswap already. */
3794    if (unlikely(ctx->le_mode)) {
3795        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3796        tcg_gen_addi_tl(EA, EA, 8);
3797        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3798    } else {
3799        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3800        tcg_gen_addi_tl(EA, EA, 8);
3801        gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3802    }
3803    tcg_temp_free(EA);
3804}
3805
3806/* Optional: */
3807static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3808{
3809    TCGv t0 = tcg_temp_new();
3810    tcg_gen_trunc_i64_tl(t0, arg1),
3811    gen_qemu_st32(ctx, t0, arg2);
3812    tcg_temp_free(t0);
3813}
3814/* stfiwx */
3815GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3816
3817static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3818{
3819#if defined(TARGET_PPC64)
3820    if (ctx->has_cfar)
3821        tcg_gen_movi_tl(cpu_cfar, nip);
3822#endif
3823}
3824
3825/***                                Branch                                 ***/
3826static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3827{
3828    TranslationBlock *tb;
3829    tb = ctx->tb;
3830    if (NARROW_MODE(ctx)) {
3831        dest = (uint32_t) dest;
3832    }
3833    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3834        likely(!ctx->singlestep_enabled)) {
3835        tcg_gen_goto_tb(n);
3836        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3837        tcg_gen_exit_tb((uintptr_t)tb + n);
3838    } else {
3839        tcg_gen_movi_tl(cpu_nip, dest & ~3);
3840        if (unlikely(ctx->singlestep_enabled)) {
3841            if ((ctx->singlestep_enabled &
3842                (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3843                (ctx->exception == POWERPC_EXCP_BRANCH ||
3844                 ctx->exception == POWERPC_EXCP_TRACE)) {
3845                target_ulong tmp = ctx->nip;
3846                ctx->nip = dest;
3847                gen_exception(ctx, POWERPC_EXCP_TRACE);
3848                ctx->nip = tmp;
3849            }
3850            if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3851                gen_debug_exception(ctx);
3852            }
3853        }
3854        tcg_gen_exit_tb(0);
3855    }
3856}
3857
3858static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3859{
3860    if (NARROW_MODE(ctx)) {
3861        nip = (uint32_t)nip;
3862    }
3863    tcg_gen_movi_tl(cpu_lr, nip);
3864}
3865
3866/* b ba bl bla */
3867static void gen_b(DisasContext *ctx)
3868{
3869    target_ulong li, target;
3870
3871    ctx->exception = POWERPC_EXCP_BRANCH;
3872    /* sign extend LI */
3873    li = LI(ctx->opcode);
3874    li = (li ^ 0x02000000) - 0x02000000;
3875    if (likely(AA(ctx->opcode) == 0)) {
3876        target = ctx->nip + li - 4;
3877    } else {
3878        target = li;
3879    }
3880    if (LK(ctx->opcode)) {
3881        gen_setlr(ctx, ctx->nip);
3882    }
3883    gen_update_cfar(ctx, ctx->nip);
3884    gen_goto_tb(ctx, 0, target);
3885}
3886
3887#define BCOND_IM  0
3888#define BCOND_LR  1
3889#define BCOND_CTR 2
3890#define BCOND_TAR 3
3891
3892static inline void gen_bcond(DisasContext *ctx, int type)
3893{
3894    uint32_t bo = BO(ctx->opcode);
3895    TCGLabel *l1;
3896    TCGv target;
3897
3898    ctx->exception = POWERPC_EXCP_BRANCH;
3899    if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3900        target = tcg_temp_local_new();
3901        if (type == BCOND_CTR)
3902            tcg_gen_mov_tl(target, cpu_ctr);
3903        else if (type == BCOND_TAR)
3904            gen_load_spr(target, SPR_TAR);
3905        else
3906            tcg_gen_mov_tl(target, cpu_lr);
3907    } else {
3908        TCGV_UNUSED(target);
3909    }
3910    if (LK(ctx->opcode))
3911        gen_setlr(ctx, ctx->nip);
3912    l1 = gen_new_label();
3913    if ((bo & 0x4) == 0) {
3914        /* Decrement and test CTR */
3915        TCGv temp = tcg_temp_new();
3916        if (unlikely(type == BCOND_CTR)) {
3917            gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3918            return;
3919        }
3920        tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3921        if (NARROW_MODE(ctx)) {
3922            tcg_gen_ext32u_tl(temp, cpu_ctr);
3923        } else {
3924            tcg_gen_mov_tl(temp, cpu_ctr);
3925        }
3926        if (bo & 0x2) {
3927            tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3928        } else {
3929            tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3930        }
3931        tcg_temp_free(temp);
3932    }
3933    if ((bo & 0x10) == 0) {
3934        /* Test CR */
3935        uint32_t bi = BI(ctx->opcode);
3936        uint32_t mask = 0x08 >> (bi & 0x03);
3937        TCGv_i32 temp = tcg_temp_new_i32();
3938
3939        if (bo & 0x8) {
3940            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3941            tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3942        } else {
3943            tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3944            tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3945        }
3946        tcg_temp_free_i32(temp);
3947    }
3948    gen_update_cfar(ctx, ctx->nip);
3949    if (type == BCOND_IM) {
3950        target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3951        if (likely(AA(ctx->opcode) == 0)) {
3952            gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3953        } else {
3954            gen_goto_tb(ctx, 0, li);
3955        }
3956        gen_set_label(l1);
3957        gen_goto_tb(ctx, 1, ctx->nip);
3958    } else {
3959        if (NARROW_MODE(ctx)) {
3960            tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3961        } else {
3962            tcg_gen_andi_tl(cpu_nip, target, ~3);
3963        }
3964        tcg_gen_exit_tb(0);
3965        gen_set_label(l1);
3966        gen_update_nip(ctx, ctx->nip);
3967        tcg_gen_exit_tb(0);
3968    }
3969    if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) {
3970        tcg_temp_free(target);
3971    }
3972}
3973
3974static void gen_bc(DisasContext *ctx)
3975{
3976    gen_bcond(ctx, BCOND_IM);
3977}
3978
3979static void gen_bcctr(DisasContext *ctx)
3980{
3981    gen_bcond(ctx, BCOND_CTR);
3982}
3983
3984static void gen_bclr(DisasContext *ctx)
3985{
3986    gen_bcond(ctx, BCOND_LR);
3987}
3988
3989static void gen_bctar(DisasContext *ctx)
3990{
3991    gen_bcond(ctx, BCOND_TAR);
3992}
3993
3994/***                      Condition register logical                       ***/
3995#define GEN_CRLOGIC(name, tcg_op, opc)                                        \
3996static void glue(gen_, name)(DisasContext *ctx)                                       \
3997{                                                                             \
3998    uint8_t bitmask;                                                          \
3999    int sh;                                                                   \
4000    TCGv_i32 t0, t1;                                                          \
4001    sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03);             \
4002    t0 = tcg_temp_new_i32();                                                  \
4003    if (sh > 0)                                                               \
4004        tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh);            \
4005    else if (sh < 0)                                                          \
4006        tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh);           \
4007    else                                                                      \
4008        tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]);                 \
4009    t1 = tcg_temp_new_i32();                                                  \
4010    sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03);             \
4011    if (sh > 0)                                                               \
4012        tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh);            \
4013    else if (sh < 0)                                                          \
4014        tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh);           \
4015    else                                                                      \
4016        tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]);                 \
4017    tcg_op(t0, t0, t1);                                                       \
4018    bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03);                             \
4019    tcg_gen_andi_i32(t0, t0, bitmask);                                        \
4020    tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask);          \
4021    tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1);                  \
4022    tcg_temp_free_i32(t0);                                                    \
4023    tcg_temp_free_i32(t1);                                                    \
4024}
4025
4026/* crand */
4027GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
4028/* crandc */
4029GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
4030/* creqv */
4031GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
4032/* crnand */
4033GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
4034/* crnor */
4035GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
4036/* cror */
4037GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
4038/* crorc */
4039GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
4040/* crxor */
4041GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
4042
4043/* mcrf */
4044static void gen_mcrf(DisasContext *ctx)
4045{
4046    tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
4047}
4048
4049/***                           System linkage                              ***/
4050
4051/* rfi (supervisor only) */
4052static void gen_rfi(DisasContext *ctx)
4053{
4054#if defined(CONFIG_USER_ONLY)
4055    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4056#else
4057    /* Restore CPU state */
4058    if (unlikely(ctx->pr)) {
4059        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4060        return;
4061    }
4062    gen_update_cfar(ctx, ctx->nip);
4063    gen_helper_rfi(cpu_env);
4064    gen_sync_exception(ctx);
4065#endif
4066}
4067
4068#if defined(TARGET_PPC64)
4069static void gen_rfid(DisasContext *ctx)
4070{
4071#if defined(CONFIG_USER_ONLY)
4072    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4073#else
4074    /* Restore CPU state */
4075    if (unlikely(ctx->pr)) {
4076        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4077        return;
4078    }
4079    gen_update_cfar(ctx, ctx->nip);
4080    gen_helper_rfid(cpu_env);
4081    gen_sync_exception(ctx);
4082#endif
4083}
4084
4085static void gen_hrfid(DisasContext *ctx)
4086{
4087#if defined(CONFIG_USER_ONLY)
4088    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4089#else
4090    /* Restore CPU state */
4091    if (unlikely(!ctx->hv)) {
4092        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4093        return;
4094    }
4095    gen_helper_hrfid(cpu_env);
4096    gen_sync_exception(ctx);
4097#endif
4098}
4099#endif
4100
4101/* sc */
4102#if defined(CONFIG_USER_ONLY)
4103#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
4104#else
4105#define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
4106#endif
4107static void gen_sc(DisasContext *ctx)
4108{
4109    uint32_t lev;
4110
4111    lev = (ctx->opcode >> 5) & 0x7F;
4112    gen_exception_err(ctx, POWERPC_SYSCALL, lev);
4113}
4114
4115/***                                Trap                                   ***/
4116
4117/* tw */
4118static void gen_tw(DisasContext *ctx)
4119{
4120    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4121    /* Update the nip since this might generate a trap exception */
4122    gen_update_nip(ctx, ctx->nip);
4123    gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4124                  t0);
4125    tcg_temp_free_i32(t0);
4126}
4127
4128/* twi */
4129static void gen_twi(DisasContext *ctx)
4130{
4131    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4132    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4133    /* Update the nip since this might generate a trap exception */
4134    gen_update_nip(ctx, ctx->nip);
4135    gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4136    tcg_temp_free(t0);
4137    tcg_temp_free_i32(t1);
4138}
4139
4140#if defined(TARGET_PPC64)
4141/* td */
4142static void gen_td(DisasContext *ctx)
4143{
4144    TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
4145    /* Update the nip since this might generate a trap exception */
4146    gen_update_nip(ctx, ctx->nip);
4147    gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
4148                  t0);
4149    tcg_temp_free_i32(t0);
4150}
4151
4152/* tdi */
4153static void gen_tdi(DisasContext *ctx)
4154{
4155    TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4156    TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4157    /* Update the nip since this might generate a trap exception */
4158    gen_update_nip(ctx, ctx->nip);
4159    gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4160    tcg_temp_free(t0);
4161    tcg_temp_free_i32(t1);
4162}
4163#endif
4164
4165/***                          Processor control                            ***/
4166
4167static void gen_read_xer(TCGv dst)
4168{
4169    TCGv t0 = tcg_temp_new();
4170    TCGv t1 = tcg_temp_new();
4171    TCGv t2 = tcg_temp_new();
4172    tcg_gen_mov_tl(dst, cpu_xer);
4173    tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4174    tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4175    tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4176    tcg_gen_or_tl(t0, t0, t1);
4177    tcg_gen_or_tl(dst, dst, t2);
4178    tcg_gen_or_tl(dst, dst, t0);
4179    tcg_temp_free(t0);
4180    tcg_temp_free(t1);
4181    tcg_temp_free(t2);
4182}
4183
4184static void gen_write_xer(TCGv src)
4185{
4186    tcg_gen_andi_tl(cpu_xer, src,
4187                    ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4188    tcg_gen_shri_tl(cpu_so, src, XER_SO);
4189    tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4190    tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4191    tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4192    tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4193    tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4194}
4195
4196/* mcrxr */
4197static void gen_mcrxr(DisasContext *ctx)
4198{
4199    TCGv_i32 t0 = tcg_temp_new_i32();
4200    TCGv_i32 t1 = tcg_temp_new_i32();
4201    TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4202
4203    tcg_gen_trunc_tl_i32(t0, cpu_so);
4204    tcg_gen_trunc_tl_i32(t1, cpu_ov);
4205    tcg_gen_trunc_tl_i32(dst, cpu_ca);
4206    tcg_gen_shli_i32(t0, t0, 3);
4207    tcg_gen_shli_i32(t1, t1, 2);
4208    tcg_gen_shli_i32(dst, dst, 1);
4209    tcg_gen_or_i32(dst, dst, t0);
4210    tcg_gen_or_i32(dst, dst, t1);
4211    tcg_temp_free_i32(t0);
4212    tcg_temp_free_i32(t1);
4213
4214    tcg_gen_movi_tl(cpu_so, 0);
4215    tcg_gen_movi_tl(cpu_ov, 0);
4216    tcg_gen_movi_tl(cpu_ca, 0);
4217}
4218
4219/* mfcr mfocrf */
4220static void gen_mfcr(DisasContext *ctx)
4221{
4222    uint32_t crm, crn;
4223
4224    if (likely(ctx->opcode & 0x00100000)) {
4225        crm = CRM(ctx->opcode);
4226        if (likely(crm && ((crm & (crm - 1)) == 0))) {
4227            crn = ctz32 (crm);
4228            tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4229            tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4230                            cpu_gpr[rD(ctx->opcode)], crn * 4);
4231        }
4232    } else {
4233        TCGv_i32 t0 = tcg_temp_new_i32();
4234        tcg_gen_mov_i32(t0, cpu_crf[0]);
4235        tcg_gen_shli_i32(t0, t0, 4);
4236        tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4237        tcg_gen_shli_i32(t0, t0, 4);
4238        tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4239        tcg_gen_shli_i32(t0, t0, 4);
4240        tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4241        tcg_gen_shli_i32(t0, t0, 4);
4242        tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4243        tcg_gen_shli_i32(t0, t0, 4);
4244        tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4245        tcg_gen_shli_i32(t0, t0, 4);
4246        tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4247        tcg_gen_shli_i32(t0, t0, 4);
4248        tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4249        tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4250        tcg_temp_free_i32(t0);
4251    }
4252}
4253
4254/* mfmsr */
4255static void gen_mfmsr(DisasContext *ctx)
4256{
4257#if defined(CONFIG_USER_ONLY)
4258    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4259#else
4260    if (unlikely(ctx->pr)) {
4261        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4262        return;
4263    }
4264    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4265#endif
4266}
4267
4268static void spr_noaccess(DisasContext *ctx, int gprn, int sprn)
4269{
4270#if 0
4271    sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4272    printf("ERROR: try to access SPR %d !\n", sprn);
4273#endif
4274}
4275#define SPR_NOACCESS (&spr_noaccess)
4276
4277/* mfspr */
4278static inline void gen_op_mfspr(DisasContext *ctx)
4279{
4280    void (*read_cb)(DisasContext *ctx, int gprn, int sprn);
4281    uint32_t sprn = SPR(ctx->opcode);
4282
4283#if defined(CONFIG_USER_ONLY)
4284    read_cb = ctx->spr_cb[sprn].uea_read;
4285#else
4286    if (ctx->pr) {
4287        read_cb = ctx->spr_cb[sprn].uea_read;
4288    } else if (ctx->hv) {
4289        read_cb = ctx->spr_cb[sprn].hea_read;
4290    } else {
4291        read_cb = ctx->spr_cb[sprn].oea_read;
4292    }
4293#endif
4294    if (likely(read_cb != NULL)) {
4295        if (likely(read_cb != SPR_NOACCESS)) {
4296            (*read_cb)(ctx, rD(ctx->opcode), sprn);
4297        } else {
4298            /* Privilege exception */
4299            /* This is a hack to avoid warnings when running Linux:
4300             * this OS breaks the PowerPC virtualisation model,
4301             * allowing userland application to read the PVR
4302             */
4303            if (sprn != SPR_PVR) {
4304                fprintf(stderr, "Trying to read privileged spr %d (0x%03x) at "
4305                        TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4306                if (qemu_log_separate()) {
4307                    qemu_log("Trying to read privileged spr %d (0x%03x) at "
4308                             TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4309                }
4310            }
4311            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4312        }
4313    } else {
4314        /* Not defined */
4315        fprintf(stderr, "Trying to read invalid spr %d (0x%03x) at "
4316                TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4317        if (qemu_log_separate()) {
4318            qemu_log("Trying to read invalid spr %d (0x%03x) at "
4319                     TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4320        }
4321        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4322    }
4323}
4324
4325static void gen_mfspr(DisasContext *ctx)
4326{
4327    gen_op_mfspr(ctx);
4328}
4329
4330/* mftb */
4331static void gen_mftb(DisasContext *ctx)
4332{
4333    gen_op_mfspr(ctx);
4334}
4335
4336/* mtcrf mtocrf*/
4337static void gen_mtcrf(DisasContext *ctx)
4338{
4339    uint32_t crm, crn;
4340
4341    crm = CRM(ctx->opcode);
4342    if (likely((ctx->opcode & 0x00100000))) {
4343        if (crm && ((crm & (crm - 1)) == 0)) {
4344            TCGv_i32 temp = tcg_temp_new_i32();
4345            crn = ctz32 (crm);
4346            tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4347            tcg_gen_shri_i32(temp, temp, crn * 4);
4348            tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4349            tcg_temp_free_i32(temp);
4350        }
4351    } else {
4352        TCGv_i32 temp = tcg_temp_new_i32();
4353        tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4354        for (crn = 0 ; crn < 8 ; crn++) {
4355            if (crm & (1 << crn)) {
4356                    tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4357                    tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4358            }
4359        }
4360        tcg_temp_free_i32(temp);
4361    }
4362}
4363
4364/* mtmsr */
4365#if defined(TARGET_PPC64)
4366static void gen_mtmsrd(DisasContext *ctx)
4367{
4368#if defined(CONFIG_USER_ONLY)
4369    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4370#else
4371    if (unlikely(ctx->pr)) {
4372        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4373        return;
4374    }
4375    if (ctx->opcode & 0x00010000) {
4376        /* Special form that does not need any synchronisation */
4377        TCGv t0 = tcg_temp_new();
4378        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4379        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4380        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4381        tcg_temp_free(t0);
4382    } else {
4383        /* XXX: we need to update nip before the store
4384         *      if we enter power saving mode, we will exit the loop
4385         *      directly from ppc_store_msr
4386         */
4387        gen_update_nip(ctx, ctx->nip);
4388        gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4389        /* Must stop the translation as machine state (may have) changed */
4390        /* Note that mtmsr is not always defined as context-synchronizing */
4391        gen_stop_exception(ctx);
4392    }
4393#endif
4394}
4395#endif
4396
4397static void gen_mtmsr(DisasContext *ctx)
4398{
4399#if defined(CONFIG_USER_ONLY)
4400    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4401#else
4402    if (unlikely(ctx->pr)) {
4403        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4404        return;
4405    }
4406    if (ctx->opcode & 0x00010000) {
4407        /* Special form that does not need any synchronisation */
4408        TCGv t0 = tcg_temp_new();
4409        tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4410        tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4411        tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4412        tcg_temp_free(t0);
4413    } else {
4414        TCGv msr = tcg_temp_new();
4415
4416        /* XXX: we need to update nip before the store
4417         *      if we enter power saving mode, we will exit the loop
4418         *      directly from ppc_store_msr
4419         */
4420        gen_update_nip(ctx, ctx->nip);
4421#if defined(TARGET_PPC64)
4422        tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4423#else
4424        tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4425#endif
4426        gen_helper_store_msr(cpu_env, msr);
4427        tcg_temp_free(msr);
4428        /* Must stop the translation as machine state (may have) changed */
4429        /* Note that mtmsr is not always defined as context-synchronizing */
4430        gen_stop_exception(ctx);
4431    }
4432#endif
4433}
4434
4435/* mtspr */
4436static void gen_mtspr(DisasContext *ctx)
4437{
4438    void (*write_cb)(DisasContext *ctx, int sprn, int gprn);
4439    uint32_t sprn = SPR(ctx->opcode);
4440
4441#if defined(CONFIG_USER_ONLY)
4442    write_cb = ctx->spr_cb[sprn].uea_write;
4443#else
4444    if (ctx->pr) {
4445        write_cb = ctx->spr_cb[sprn].uea_write;
4446    } else if (ctx->hv) {
4447        write_cb = ctx->spr_cb[sprn].hea_write;
4448    } else {
4449        write_cb = ctx->spr_cb[sprn].oea_write;
4450    }
4451#endif
4452    if (likely(write_cb != NULL)) {
4453        if (likely(write_cb != SPR_NOACCESS)) {
4454            (*write_cb)(ctx, sprn, rS(ctx->opcode));
4455        } else {
4456            /* Privilege exception */
4457            fprintf(stderr, "Trying to write privileged spr %d (0x%03x) at "
4458                    TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4459            if (qemu_log_separate()) {
4460                qemu_log("Trying to write privileged spr %d (0x%03x) at "
4461                         TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4462            }
4463            gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4464        }
4465    } else {
4466        /* Not defined */
4467        if (qemu_log_separate()) {
4468            qemu_log("Trying to write invalid spr %d (0x%03x) at "
4469                     TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4470        }
4471        fprintf(stderr, "Trying to write invalid spr %d (0x%03x) at "
4472                TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4473        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4474    }
4475}
4476
4477/***                         Cache management                              ***/
4478
4479/* dcbf */
4480static void gen_dcbf(DisasContext *ctx)
4481{
4482    /* XXX: specification says this is treated as a load by the MMU */
4483    TCGv t0;
4484    gen_set_access_type(ctx, ACCESS_CACHE);
4485    t0 = tcg_temp_new();
4486    gen_addr_reg_index(ctx, t0);
4487    gen_qemu_ld8u(ctx, t0, t0);
4488    tcg_temp_free(t0);
4489}
4490
4491/* dcbi (Supervisor only) */
4492static void gen_dcbi(DisasContext *ctx)
4493{
4494#if defined(CONFIG_USER_ONLY)
4495    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4496#else
4497    TCGv EA, val;
4498    if (unlikely(ctx->pr)) {
4499        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4500        return;
4501    }
4502    EA = tcg_temp_new();
4503    gen_set_access_type(ctx, ACCESS_CACHE);
4504    gen_addr_reg_index(ctx, EA);
4505    val = tcg_temp_new();
4506    /* XXX: specification says this should be treated as a store by the MMU */
4507    gen_qemu_ld8u(ctx, val, EA);
4508    gen_qemu_st8(ctx, val, EA);
4509    tcg_temp_free(val);
4510    tcg_temp_free(EA);
4511#endif
4512}
4513
4514/* dcdst */
4515static void gen_dcbst(DisasContext *ctx)
4516{
4517    /* XXX: specification say this is treated as a load by the MMU */
4518    TCGv t0;
4519    gen_set_access_type(ctx, ACCESS_CACHE);
4520    t0 = tcg_temp_new();
4521    gen_addr_reg_index(ctx, t0);
4522    gen_qemu_ld8u(ctx, t0, t0);
4523    tcg_temp_free(t0);
4524}
4525
4526/* dcbt */
4527static void gen_dcbt(DisasContext *ctx)
4528{
4529    /* interpreted as no-op */
4530    /* XXX: specification say this is treated as a load by the MMU
4531     *      but does not generate any exception
4532     */
4533}
4534
4535/* dcbtst */
4536static void gen_dcbtst(DisasContext *ctx)
4537{
4538    /* interpreted as no-op */
4539    /* XXX: specification say this is treated as a load by the MMU
4540     *      but does not generate any exception
4541     */
4542}
4543
4544/* dcbtls */
4545static void gen_dcbtls(DisasContext *ctx)
4546{
4547    /* Always fails locking the cache */
4548    TCGv t0 = tcg_temp_new();
4549    gen_load_spr(t0, SPR_Exxx_L1CSR0);
4550    tcg_gen_ori_tl(t0, t0, L1CSR0_CUL);
4551    gen_store_spr(SPR_Exxx_L1CSR0, t0);
4552    tcg_temp_free(t0);
4553}
4554
4555/* dcbz */
4556static void gen_dcbz(DisasContext *ctx)
4557{
4558    TCGv tcgv_addr;
4559    TCGv_i32 tcgv_is_dcbzl;
4560    int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4561
4562    gen_set_access_type(ctx, ACCESS_CACHE);
4563    /* NIP cannot be restored if the memory exception comes from an helper */
4564    gen_update_nip(ctx, ctx->nip - 4);
4565    tcgv_addr = tcg_temp_new();
4566    tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4567
4568    gen_addr_reg_index(ctx, tcgv_addr);
4569    gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4570
4571    tcg_temp_free(tcgv_addr);
4572    tcg_temp_free_i32(tcgv_is_dcbzl);
4573}
4574
4575/* dst / dstt */
4576static void gen_dst(DisasContext *ctx)
4577{
4578    if (rA(ctx->opcode) == 0) {
4579        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4580    } else {
4581        /* interpreted as no-op */
4582    }
4583}
4584
4585/* dstst /dststt */
4586static void gen_dstst(DisasContext *ctx)
4587{
4588    if (rA(ctx->opcode) == 0) {
4589        gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4590    } else {
4591        /* interpreted as no-op */
4592    }
4593
4594}
4595
4596/* dss / dssall */
4597static void gen_dss(DisasContext *ctx)
4598{
4599    /* interpreted as no-op */
4600}
4601
4602/* icbi */
4603static void gen_icbi(DisasContext *ctx)
4604{
4605    TCGv t0;
4606    gen_set_access_type(ctx, ACCESS_CACHE);
4607    /* NIP cannot be restored if the memory exception comes from an helper */
4608    gen_update_nip(ctx, ctx->nip - 4);
4609    t0 = tcg_temp_new();
4610    gen_addr_reg_index(ctx, t0);
4611    gen_helper_icbi(cpu_env, t0);
4612    tcg_temp_free(t0);
4613}
4614
4615/* Optional: */
4616/* dcba */
4617static void gen_dcba(DisasContext *ctx)
4618{
4619    /* interpreted as no-op */
4620    /* XXX: specification say this is treated as a store by the MMU
4621     *      but does not generate any exception
4622     */
4623}
4624
4625/***                    Segment register manipulation                      ***/
4626/* Supervisor only: */
4627
4628/* mfsr */
4629static void gen_mfsr(DisasContext *ctx)
4630{
4631#if defined(CONFIG_USER_ONLY)
4632    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4633#else
4634    TCGv t0;
4635    if (unlikely(ctx->pr)) {
4636        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4637        return;
4638    }
4639    t0 = tcg_const_tl(SR(ctx->opcode));
4640    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4641    tcg_temp_free(t0);
4642#endif
4643}
4644
4645/* mfsrin */
4646static void gen_mfsrin(DisasContext *ctx)
4647{
4648#if defined(CONFIG_USER_ONLY)
4649    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4650#else
4651    TCGv t0;
4652    if (unlikely(ctx->pr)) {
4653        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4654        return;
4655    }
4656    t0 = tcg_temp_new();
4657    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4658    tcg_gen_andi_tl(t0, t0, 0xF);
4659    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4660    tcg_temp_free(t0);
4661#endif
4662}
4663
4664/* mtsr */
4665static void gen_mtsr(DisasContext *ctx)
4666{
4667#if defined(CONFIG_USER_ONLY)
4668    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4669#else
4670    TCGv t0;
4671    if (unlikely(ctx->pr)) {
4672        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4673        return;
4674    }
4675    t0 = tcg_const_tl(SR(ctx->opcode));
4676    gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4677    tcg_temp_free(t0);
4678#endif
4679}
4680
4681/* mtsrin */
4682static void gen_mtsrin(DisasContext *ctx)
4683{
4684#if defined(CONFIG_USER_ONLY)
4685    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4686#else
4687    TCGv t0;
4688    if (unlikely(ctx->pr)) {
4689        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4690        return;
4691    }
4692    t0 = tcg_temp_new();
4693    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4694    tcg_gen_andi_tl(t0, t0, 0xF);
4695    gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4696    tcg_temp_free(t0);
4697#endif
4698}
4699
4700#if defined(TARGET_PPC64)
4701/* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4702
4703/* mfsr */
4704static void gen_mfsr_64b(DisasContext *ctx)
4705{
4706#if defined(CONFIG_USER_ONLY)
4707    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4708#else
4709    TCGv t0;
4710    if (unlikely(ctx->pr)) {
4711        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4712        return;
4713    }
4714    t0 = tcg_const_tl(SR(ctx->opcode));
4715    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4716    tcg_temp_free(t0);
4717#endif
4718}
4719
4720/* mfsrin */
4721static void gen_mfsrin_64b(DisasContext *ctx)
4722{
4723#if defined(CONFIG_USER_ONLY)
4724    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4725#else
4726    TCGv t0;
4727    if (unlikely(ctx->pr)) {
4728        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4729        return;
4730    }
4731    t0 = tcg_temp_new();
4732    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4733    tcg_gen_andi_tl(t0, t0, 0xF);
4734    gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4735    tcg_temp_free(t0);
4736#endif
4737}
4738
4739/* mtsr */
4740static void gen_mtsr_64b(DisasContext *ctx)
4741{
4742#if defined(CONFIG_USER_ONLY)
4743    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4744#else
4745    TCGv t0;
4746    if (unlikely(ctx->pr)) {
4747        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4748        return;
4749    }
4750    t0 = tcg_const_tl(SR(ctx->opcode));
4751    gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4752    tcg_temp_free(t0);
4753#endif
4754}
4755
4756/* mtsrin */
4757static void gen_mtsrin_64b(DisasContext *ctx)
4758{
4759#if defined(CONFIG_USER_ONLY)
4760    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4761#else
4762    TCGv t0;
4763    if (unlikely(ctx->pr)) {
4764        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4765        return;
4766    }
4767    t0 = tcg_temp_new();
4768    tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4769    tcg_gen_andi_tl(t0, t0, 0xF);
4770    gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4771    tcg_temp_free(t0);
4772#endif
4773}
4774
4775/* slbmte */
4776static void gen_slbmte(DisasContext *ctx)
4777{
4778#if defined(CONFIG_USER_ONLY)
4779    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4780#else
4781    if (unlikely(ctx->pr)) {
4782        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4783        return;
4784    }
4785    gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4786                         cpu_gpr[rS(ctx->opcode)]);
4787#endif
4788}
4789
4790static void gen_slbmfee(DisasContext *ctx)
4791{
4792#if defined(CONFIG_USER_ONLY)
4793    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4794#else
4795    if (unlikely(ctx->pr)) {
4796        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4797        return;
4798    }
4799    gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4800                             cpu_gpr[rB(ctx->opcode)]);
4801#endif
4802}
4803
4804static void gen_slbmfev(DisasContext *ctx)
4805{
4806#if defined(CONFIG_USER_ONLY)
4807    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4808#else
4809    if (unlikely(ctx->pr)) {
4810        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4811        return;
4812    }
4813    gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4814                             cpu_gpr[rB(ctx->opcode)]);
4815#endif
4816}
4817#endif /* defined(TARGET_PPC64) */
4818
4819/***                      Lookaside buffer management                      ***/
4820/* Optional & supervisor only: */
4821
4822/* tlbia */
4823static void gen_tlbia(DisasContext *ctx)
4824{
4825#if defined(CONFIG_USER_ONLY)
4826    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4827#else
4828    if (unlikely(ctx->pr)) {
4829        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4830        return;
4831    }
4832    gen_helper_tlbia(cpu_env);
4833#endif
4834}
4835
4836/* tlbiel */
4837static void gen_tlbiel(DisasContext *ctx)
4838{
4839#if defined(CONFIG_USER_ONLY)
4840    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4841#else
4842    if (unlikely(ctx->pr)) {
4843        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4844        return;
4845    }
4846    gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4847#endif
4848}
4849
4850/* tlbie */
4851static void gen_tlbie(DisasContext *ctx)
4852{
4853#if defined(CONFIG_USER_ONLY)
4854    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4855#else
4856    if (unlikely(ctx->pr)) {
4857        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4858        return;
4859    }
4860    if (NARROW_MODE(ctx)) {
4861        TCGv t0 = tcg_temp_new();
4862        tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4863        gen_helper_tlbie(cpu_env, t0);
4864        tcg_temp_free(t0);
4865    } else {
4866        gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4867    }
4868#endif
4869}
4870
4871/* tlbsync */
4872static void gen_tlbsync(DisasContext *ctx)
4873{
4874#if defined(CONFIG_USER_ONLY)
4875    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4876#else
4877    if (unlikely(ctx->pr)) {
4878        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4879        return;
4880    }
4881    /* This has no effect: it should ensure that all previous
4882     * tlbie have completed
4883     */
4884    gen_stop_exception(ctx);
4885#endif
4886}
4887
4888#if defined(TARGET_PPC64)
4889/* slbia */
4890static void gen_slbia(DisasContext *ctx)
4891{
4892#if defined(CONFIG_USER_ONLY)
4893    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4894#else
4895    if (unlikely(ctx->pr)) {
4896        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4897        return;
4898    }
4899    gen_helper_slbia(cpu_env);
4900#endif
4901}
4902
4903/* slbie */
4904static void gen_slbie(DisasContext *ctx)
4905{
4906#if defined(CONFIG_USER_ONLY)
4907    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4908#else
4909    if (unlikely(ctx->pr)) {
4910        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4911        return;
4912    }
4913    gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4914#endif
4915}
4916#endif
4917
4918/***                              External control                         ***/
4919/* Optional: */
4920
4921/* eciwx */
4922static void gen_eciwx(DisasContext *ctx)
4923{
4924    TCGv t0;
4925    /* Should check EAR[E] ! */
4926    gen_set_access_type(ctx, ACCESS_EXT);
4927    t0 = tcg_temp_new();
4928    gen_addr_reg_index(ctx, t0);
4929    gen_check_align(ctx, t0, 0x03);
4930    gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4931    tcg_temp_free(t0);
4932}
4933
4934/* ecowx */
4935static void gen_ecowx(DisasContext *ctx)
4936{
4937    TCGv t0;
4938    /* Should check EAR[E] ! */
4939    gen_set_access_type(ctx, ACCESS_EXT);
4940    t0 = tcg_temp_new();
4941    gen_addr_reg_index(ctx, t0);
4942    gen_check_align(ctx, t0, 0x03);
4943    gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4944    tcg_temp_free(t0);
4945}
4946
4947/* PowerPC 601 specific instructions */
4948
4949/* abs - abs. */
4950static void gen_abs(DisasContext *ctx)
4951{
4952    TCGLabel *l1 = gen_new_label();
4953    TCGLabel *l2 = gen_new_label();
4954    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4955    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4956    tcg_gen_br(l2);
4957    gen_set_label(l1);
4958    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4959    gen_set_label(l2);
4960    if (unlikely(Rc(ctx->opcode) != 0))
4961        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4962}
4963
4964/* abso - abso. */
4965static void gen_abso(DisasContext *ctx)
4966{
4967    TCGLabel *l1 = gen_new_label();
4968    TCGLabel *l2 = gen_new_label();
4969    TCGLabel *l3 = gen_new_label();
4970    /* Start with XER OV disabled, the most likely case */
4971    tcg_gen_movi_tl(cpu_ov, 0);
4972    tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4973    tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4974    tcg_gen_movi_tl(cpu_ov, 1);
4975    tcg_gen_movi_tl(cpu_so, 1);
4976    tcg_gen_br(l2);
4977    gen_set_label(l1);
4978    tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4979    tcg_gen_br(l3);
4980    gen_set_label(l2);
4981    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4982    gen_set_label(l3);
4983    if (unlikely(Rc(ctx->opcode) != 0))
4984        gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4985}
4986
4987/* clcs */
4988static void gen_clcs(DisasContext *ctx)
4989{
4990    TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4991    gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env,