qemu/target-ppc/translate_init.c
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   1/*
   2 *  PowerPC CPU initialization for qemu.
   3 *
   4 *  Copyright (c) 2003-2007 Jocelyn Mayer
   5 *  Copyright 2011 Freescale Semiconductor, Inc.
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "disas/bfd.h"
  23#include "exec/gdbstub.h"
  24#include <sysemu/kvm.h>
  25#include "kvm_ppc.h"
  26#include "sysemu/arch_init.h"
  27#include "sysemu/cpus.h"
  28#include "cpu-models.h"
  29#include "mmu-hash32.h"
  30#include "mmu-hash64.h"
  31#include "qemu/error-report.h"
  32#include "qapi/visitor.h"
  33#include "hw/qdev-properties.h"
  34
  35//#define PPC_DUMP_CPU
  36//#define PPC_DEBUG_SPR
  37//#define PPC_DUMP_SPR_ACCESSES
  38/* #define USE_APPLE_GDB */
  39
  40/* For user-mode emulation, we don't emulate any IRQ controller */
  41#if defined(CONFIG_USER_ONLY)
  42#define PPC_IRQ_INIT_FN(name)                                                 \
  43static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env)         \
  44{                                                                             \
  45}
  46#else
  47#define PPC_IRQ_INIT_FN(name)                                                 \
  48void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
  49#endif
  50
  51PPC_IRQ_INIT_FN(40x);
  52PPC_IRQ_INIT_FN(6xx);
  53PPC_IRQ_INIT_FN(970);
  54PPC_IRQ_INIT_FN(POWER7);
  55PPC_IRQ_INIT_FN(e500);
  56
  57/* Generic callbacks:
  58 * do nothing but store/retrieve spr value
  59 */
  60static void spr_load_dump_spr(int sprn)
  61{
  62#ifdef PPC_DUMP_SPR_ACCESSES
  63    TCGv_i32 t0 = tcg_const_i32(sprn);
  64    gen_helper_load_dump_spr(cpu_env, t0);
  65    tcg_temp_free_i32(t0);
  66#endif
  67}
  68
  69static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
  70{
  71    gen_load_spr(cpu_gpr[gprn], sprn);
  72    spr_load_dump_spr(sprn);
  73}
  74
  75static void spr_store_dump_spr(int sprn)
  76{
  77#ifdef PPC_DUMP_SPR_ACCESSES
  78    TCGv_i32 t0 = tcg_const_i32(sprn);
  79    gen_helper_store_dump_spr(cpu_env, t0);
  80    tcg_temp_free_i32(t0);
  81#endif
  82}
  83
  84static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
  85{
  86    gen_store_spr(sprn, cpu_gpr[gprn]);
  87    spr_store_dump_spr(sprn);
  88}
  89
  90#if !defined(CONFIG_USER_ONLY)
  91static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
  92{
  93#ifdef TARGET_PPC64
  94    TCGv t0 = tcg_temp_new();
  95    tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
  96    gen_store_spr(sprn, t0);
  97    tcg_temp_free(t0);
  98    spr_store_dump_spr(sprn);
  99#else
 100    spr_write_generic(ctx, sprn, gprn);
 101#endif
 102}
 103
 104static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
 105{
 106    TCGv t0 = tcg_temp_new();
 107    TCGv t1 = tcg_temp_new();
 108    gen_load_spr(t0, sprn);
 109    tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
 110    tcg_gen_and_tl(t0, t0, t1);
 111    gen_store_spr(sprn, t0);
 112    tcg_temp_free(t0);
 113    tcg_temp_free(t1);
 114}
 115
 116static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
 117{
 118}
 119
 120#endif
 121
 122/* SPR common to all PowerPC */
 123/* XER */
 124static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
 125{
 126    gen_read_xer(cpu_gpr[gprn]);
 127}
 128
 129static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
 130{
 131    gen_write_xer(cpu_gpr[gprn]);
 132}
 133
 134/* LR */
 135static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
 136{
 137    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
 138}
 139
 140static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
 141{
 142    tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
 143}
 144
 145/* CFAR */
 146#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 147static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
 148{
 149    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
 150}
 151
 152static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
 153{
 154    tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
 155}
 156#endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
 157
 158/* CTR */
 159static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
 160{
 161    tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
 162}
 163
 164static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
 165{
 166    tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
 167}
 168
 169/* User read access to SPR */
 170/* USPRx */
 171/* UMMCRx */
 172/* UPMCx */
 173/* USIA */
 174/* UDECR */
 175static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
 176{
 177    gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
 178}
 179
 180#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
 181static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
 182{
 183    gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
 184}
 185#endif
 186
 187/* SPR common to all non-embedded PowerPC */
 188/* DECR */
 189#if !defined(CONFIG_USER_ONLY)
 190static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
 191{
 192    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 193        gen_io_start();
 194    }
 195    gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
 196    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 197        gen_io_end();
 198        gen_stop_exception(ctx);
 199    }
 200}
 201
 202static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
 203{
 204    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 205        gen_io_start();
 206    }
 207    gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
 208    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 209        gen_io_end();
 210        gen_stop_exception(ctx);
 211    }
 212}
 213#endif
 214
 215/* SPR common to all non-embedded PowerPC, except 601 */
 216/* Time base */
 217static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
 218{
 219    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 220        gen_io_start();
 221    }
 222    gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
 223    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 224        gen_io_end();
 225        gen_stop_exception(ctx);
 226    }
 227}
 228
 229static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
 230{
 231    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 232        gen_io_start();
 233    }
 234    gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
 235    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 236        gen_io_end();
 237        gen_stop_exception(ctx);
 238    }
 239}
 240
 241__attribute__ (( unused ))
 242static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
 243{
 244    gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
 245}
 246
 247__attribute__ (( unused ))
 248static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
 249{
 250    gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
 251}
 252
 253#if !defined(CONFIG_USER_ONLY)
 254static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
 255{
 256    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 257        gen_io_start();
 258    }
 259    gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
 260    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 261        gen_io_end();
 262        gen_stop_exception(ctx);
 263    }
 264}
 265
 266static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
 267{
 268    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 269        gen_io_start();
 270    }
 271    gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
 272    if (ctx->tb->cflags & CF_USE_ICOUNT) {
 273        gen_io_end();
 274        gen_stop_exception(ctx);
 275    }
 276}
 277
 278__attribute__ (( unused ))
 279static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
 280{
 281    gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
 282}
 283
 284__attribute__ (( unused ))
 285static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
 286{
 287    gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
 288}
 289
 290#if defined(TARGET_PPC64)
 291__attribute__ (( unused ))
 292static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
 293{
 294    gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
 295}
 296#endif
 297#endif
 298
 299#if !defined(CONFIG_USER_ONLY)
 300/* IBAT0U...IBAT0U */
 301/* IBAT0L...IBAT7L */
 302static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
 303{
 304    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 305}
 306
 307static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
 308{
 309    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
 310}
 311
 312static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
 313{
 314    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 315    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 316    tcg_temp_free_i32(t0);
 317}
 318
 319static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
 320{
 321    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
 322    gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
 323    tcg_temp_free_i32(t0);
 324}
 325
 326static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
 327{
 328    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
 329    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 330    tcg_temp_free_i32(t0);
 331}
 332
 333static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
 334{
 335    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
 336    gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
 337    tcg_temp_free_i32(t0);
 338}
 339
 340/* DBAT0U...DBAT7U */
 341/* DBAT0L...DBAT7L */
 342static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
 343{
 344    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
 345}
 346
 347static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
 348{
 349    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
 350}
 351
 352static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
 353{
 354    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
 355    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 356    tcg_temp_free_i32(t0);
 357}
 358
 359static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
 360{
 361    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
 362    gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
 363    tcg_temp_free_i32(t0);
 364}
 365
 366static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
 367{
 368    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
 369    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 370    tcg_temp_free_i32(t0);
 371}
 372
 373static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
 374{
 375    TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
 376    gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
 377    tcg_temp_free_i32(t0);
 378}
 379
 380/* SDR1 */
 381static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
 382{
 383    gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
 384}
 385
 386/* 64 bits PowerPC specific SPRs */
 387#if defined(TARGET_PPC64)
 388static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
 389{
 390    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
 391}
 392
 393static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
 394{
 395    TCGv t0 = tcg_temp_new();
 396    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
 397    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 398    tcg_temp_free(t0);
 399}
 400#endif
 401#endif
 402
 403/* PowerPC 601 specific registers */
 404/* RTC */
 405static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
 406{
 407    gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
 408}
 409
 410static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
 411{
 412    gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
 413}
 414
 415#if !defined(CONFIG_USER_ONLY)
 416static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
 417{
 418    gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
 419}
 420
 421static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
 422{
 423    gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
 424}
 425
 426static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
 427{
 428    gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
 429    /* Must stop the translation as endianness may have changed */
 430    gen_stop_exception(ctx);
 431}
 432#endif
 433
 434/* Unified bats */
 435#if !defined(CONFIG_USER_ONLY)
 436static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
 437{
 438    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
 439}
 440
 441static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
 442{
 443    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 444    gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
 445    tcg_temp_free_i32(t0);
 446}
 447
 448static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
 449{
 450    TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
 451    gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
 452    tcg_temp_free_i32(t0);
 453}
 454#endif
 455
 456/* PowerPC 40x specific registers */
 457#if !defined(CONFIG_USER_ONLY)
 458static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
 459{
 460    gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
 461}
 462
 463static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
 464{
 465    gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
 466}
 467
 468static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
 469{
 470    gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
 471    /* We must stop translation as we may have rebooted */
 472    gen_stop_exception(ctx);
 473}
 474
 475static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
 476{
 477    gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
 478}
 479
 480static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
 481{
 482    gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
 483}
 484
 485static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
 486{
 487    gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
 488}
 489#endif
 490
 491/* PowerPC 403 specific registers */
 492/* PBL1 / PBU1 / PBL2 / PBU2 */
 493#if !defined(CONFIG_USER_ONLY)
 494static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
 495{
 496    tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
 497}
 498
 499static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
 500{
 501    TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
 502    gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
 503    tcg_temp_free_i32(t0);
 504}
 505
 506static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
 507{
 508    TCGv t0 = tcg_temp_new();
 509    tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
 510    gen_store_spr(SPR_PIR, t0);
 511    tcg_temp_free(t0);
 512}
 513#endif
 514
 515/* SPE specific registers */
 516static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
 517{
 518    TCGv_i32 t0 = tcg_temp_new_i32();
 519    tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 520    tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
 521    tcg_temp_free_i32(t0);
 522}
 523
 524static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
 525{
 526    TCGv_i32 t0 = tcg_temp_new_i32();
 527    tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
 528    tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
 529    tcg_temp_free_i32(t0);
 530}
 531
 532#if !defined(CONFIG_USER_ONLY)
 533/* Callback used to write the exception vector base */
 534static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
 535{
 536    TCGv t0 = tcg_temp_new();
 537    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
 538    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 539    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
 540    gen_store_spr(sprn, t0);
 541    tcg_temp_free(t0);
 542}
 543
 544static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
 545{
 546    int sprn_offs;
 547
 548    if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
 549        sprn_offs = sprn - SPR_BOOKE_IVOR0;
 550    } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
 551        sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
 552    } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
 553        sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
 554    } else {
 555        printf("Trying to write an unknown exception vector %d %03x\n",
 556               sprn, sprn);
 557        gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
 558        return;
 559    }
 560
 561    TCGv t0 = tcg_temp_new();
 562    tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
 563    tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
 564    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
 565    gen_store_spr(sprn, t0);
 566    tcg_temp_free(t0);
 567}
 568#endif
 569
 570static inline void vscr_init (CPUPPCState *env, uint32_t val)
 571{
 572    env->vscr = val;
 573    /* Altivec always uses round-to-nearest */
 574    set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
 575    set_flush_to_zero(vscr_nj, &env->vec_status);
 576}
 577
 578#ifdef CONFIG_USER_ONLY
 579#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 580                         oea_read, oea_write, one_reg_id, initial_value)       \
 581    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 582#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 583                            oea_read, oea_write, hea_read, hea_write,          \
 584                            one_reg_id, initial_value)                         \
 585    _spr_register(env, num, name, uea_read, uea_write, initial_value)
 586#else
 587#if !defined(CONFIG_KVM)
 588#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 589                         oea_read, oea_write, one_reg_id, initial_value)       \
 590    _spr_register(env, num, name, uea_read, uea_write,                         \
 591                  oea_read, oea_write, oea_read, oea_write, initial_value)
 592#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 593                            oea_read, oea_write, hea_read, hea_write,          \
 594                            one_reg_id, initial_value)                         \
 595    _spr_register(env, num, name, uea_read, uea_write,                         \
 596                  oea_read, oea_write, hea_read, hea_write, initial_value)
 597#else
 598#define spr_register_kvm(env, num, name, uea_read, uea_write,                  \
 599                         oea_read, oea_write, one_reg_id, initial_value)       \
 600    _spr_register(env, num, name, uea_read, uea_write,                         \
 601                  oea_read, oea_write, oea_read, oea_write,                    \
 602                  one_reg_id, initial_value)
 603#define spr_register_kvm_hv(env, num, name, uea_read, uea_write,               \
 604                            oea_read, oea_write, hea_read, hea_write,          \
 605                            one_reg_id, initial_value)                         \
 606    _spr_register(env, num, name, uea_read, uea_write,                         \
 607                  oea_read, oea_write, hea_read, hea_write,                    \
 608                  one_reg_id, initial_value)
 609#endif
 610#endif
 611
 612#define spr_register(env, num, name, uea_read, uea_write,                      \
 613                     oea_read, oea_write, initial_value)                       \
 614    spr_register_kvm(env, num, name, uea_read, uea_write,                      \
 615                     oea_read, oea_write, 0, initial_value)
 616
 617#define spr_register_hv(env, num, name, uea_read, uea_write,                   \
 618                        oea_read, oea_write, hea_read, hea_write,              \
 619                        initial_value)                                         \
 620    spr_register_kvm_hv(env, num, name, uea_read, uea_write,                   \
 621                        oea_read, oea_write, hea_read, hea_write,              \
 622                        0, initial_value)
 623
 624static inline void _spr_register(CPUPPCState *env, int num,
 625                                 const char *name,
 626                                 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
 627                                 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
 628#if !defined(CONFIG_USER_ONLY)
 629
 630                                 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
 631                                 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
 632                                 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
 633                                 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
 634#endif
 635#if defined(CONFIG_KVM)
 636                                 uint64_t one_reg_id,
 637#endif
 638                                 target_ulong initial_value)
 639{
 640    ppc_spr_t *spr;
 641
 642    spr = &env->spr_cb[num];
 643    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
 644#if !defined(CONFIG_USER_ONLY)
 645        spr->oea_read != NULL || spr->oea_write != NULL ||
 646#endif
 647        spr->uea_read != NULL || spr->uea_write != NULL) {
 648        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
 649        exit(1);
 650    }
 651#if defined(PPC_DEBUG_SPR)
 652    printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
 653           name, initial_value);
 654#endif
 655    spr->name = name;
 656    spr->uea_read = uea_read;
 657    spr->uea_write = uea_write;
 658#if !defined(CONFIG_USER_ONLY)
 659    spr->oea_read = oea_read;
 660    spr->oea_write = oea_write;
 661    spr->hea_read = hea_read;
 662    spr->hea_write = hea_write;
 663#endif
 664#if defined(CONFIG_KVM)
 665    spr->one_reg_id = one_reg_id,
 666#endif
 667    env->spr[num] = spr->default_value = initial_value;
 668}
 669
 670/* Generic PowerPC SPRs */
 671static void gen_spr_generic (CPUPPCState *env)
 672{
 673    /* Integer processing */
 674    spr_register(env, SPR_XER, "XER",
 675                 &spr_read_xer, &spr_write_xer,
 676                 &spr_read_xer, &spr_write_xer,
 677                 0x00000000);
 678    /* Branch contol */
 679    spr_register(env, SPR_LR, "LR",
 680                 &spr_read_lr, &spr_write_lr,
 681                 &spr_read_lr, &spr_write_lr,
 682                 0x00000000);
 683    spr_register(env, SPR_CTR, "CTR",
 684                 &spr_read_ctr, &spr_write_ctr,
 685                 &spr_read_ctr, &spr_write_ctr,
 686                 0x00000000);
 687    /* Interrupt processing */
 688    spr_register(env, SPR_SRR0, "SRR0",
 689                 SPR_NOACCESS, SPR_NOACCESS,
 690                 &spr_read_generic, &spr_write_generic,
 691                 0x00000000);
 692    spr_register(env, SPR_SRR1, "SRR1",
 693                 SPR_NOACCESS, SPR_NOACCESS,
 694                 &spr_read_generic, &spr_write_generic,
 695                 0x00000000);
 696    /* Processor control */
 697    spr_register(env, SPR_SPRG0, "SPRG0",
 698                 SPR_NOACCESS, SPR_NOACCESS,
 699                 &spr_read_generic, &spr_write_generic,
 700                 0x00000000);
 701    spr_register(env, SPR_SPRG1, "SPRG1",
 702                 SPR_NOACCESS, SPR_NOACCESS,
 703                 &spr_read_generic, &spr_write_generic,
 704                 0x00000000);
 705    spr_register(env, SPR_SPRG2, "SPRG2",
 706                 SPR_NOACCESS, SPR_NOACCESS,
 707                 &spr_read_generic, &spr_write_generic,
 708                 0x00000000);
 709    spr_register(env, SPR_SPRG3, "SPRG3",
 710                 SPR_NOACCESS, SPR_NOACCESS,
 711                 &spr_read_generic, &spr_write_generic,
 712                 0x00000000);
 713}
 714
 715/* SPR common to all non-embedded PowerPC, including 601 */
 716static void gen_spr_ne_601 (CPUPPCState *env)
 717{
 718    /* Exception processing */
 719    spr_register_kvm(env, SPR_DSISR, "DSISR",
 720                     SPR_NOACCESS, SPR_NOACCESS,
 721                     &spr_read_generic, &spr_write_generic,
 722                     KVM_REG_PPC_DSISR, 0x00000000);
 723    spr_register_kvm(env, SPR_DAR, "DAR",
 724                     SPR_NOACCESS, SPR_NOACCESS,
 725                     &spr_read_generic, &spr_write_generic,
 726                     KVM_REG_PPC_DAR, 0x00000000);
 727    /* Timer */
 728    spr_register(env, SPR_DECR, "DECR",
 729                 SPR_NOACCESS, SPR_NOACCESS,
 730                 &spr_read_decr, &spr_write_decr,
 731                 0x00000000);
 732    /* Memory management */
 733    spr_register(env, SPR_SDR1, "SDR1",
 734                 SPR_NOACCESS, SPR_NOACCESS,
 735                 &spr_read_generic, &spr_write_sdr1,
 736                 0x00000000);
 737}
 738
 739/* BATs 0-3 */
 740static void gen_low_BATs (CPUPPCState *env)
 741{
 742#if !defined(CONFIG_USER_ONLY)
 743    spr_register(env, SPR_IBAT0U, "IBAT0U",
 744                 SPR_NOACCESS, SPR_NOACCESS,
 745                 &spr_read_ibat, &spr_write_ibatu,
 746                 0x00000000);
 747    spr_register(env, SPR_IBAT0L, "IBAT0L",
 748                 SPR_NOACCESS, SPR_NOACCESS,
 749                 &spr_read_ibat, &spr_write_ibatl,
 750                 0x00000000);
 751    spr_register(env, SPR_IBAT1U, "IBAT1U",
 752                 SPR_NOACCESS, SPR_NOACCESS,
 753                 &spr_read_ibat, &spr_write_ibatu,
 754                 0x00000000);
 755    spr_register(env, SPR_IBAT1L, "IBAT1L",
 756                 SPR_NOACCESS, SPR_NOACCESS,
 757                 &spr_read_ibat, &spr_write_ibatl,
 758                 0x00000000);
 759    spr_register(env, SPR_IBAT2U, "IBAT2U",
 760                 SPR_NOACCESS, SPR_NOACCESS,
 761                 &spr_read_ibat, &spr_write_ibatu,
 762                 0x00000000);
 763    spr_register(env, SPR_IBAT2L, "IBAT2L",
 764                 SPR_NOACCESS, SPR_NOACCESS,
 765                 &spr_read_ibat, &spr_write_ibatl,
 766                 0x00000000);
 767    spr_register(env, SPR_IBAT3U, "IBAT3U",
 768                 SPR_NOACCESS, SPR_NOACCESS,
 769                 &spr_read_ibat, &spr_write_ibatu,
 770                 0x00000000);
 771    spr_register(env, SPR_IBAT3L, "IBAT3L",
 772                 SPR_NOACCESS, SPR_NOACCESS,
 773                 &spr_read_ibat, &spr_write_ibatl,
 774                 0x00000000);
 775    spr_register(env, SPR_DBAT0U, "DBAT0U",
 776                 SPR_NOACCESS, SPR_NOACCESS,
 777                 &spr_read_dbat, &spr_write_dbatu,
 778                 0x00000000);
 779    spr_register(env, SPR_DBAT0L, "DBAT0L",
 780                 SPR_NOACCESS, SPR_NOACCESS,
 781                 &spr_read_dbat, &spr_write_dbatl,
 782                 0x00000000);
 783    spr_register(env, SPR_DBAT1U, "DBAT1U",
 784                 SPR_NOACCESS, SPR_NOACCESS,
 785                 &spr_read_dbat, &spr_write_dbatu,
 786                 0x00000000);
 787    spr_register(env, SPR_DBAT1L, "DBAT1L",
 788                 SPR_NOACCESS, SPR_NOACCESS,
 789                 &spr_read_dbat, &spr_write_dbatl,
 790                 0x00000000);
 791    spr_register(env, SPR_DBAT2U, "DBAT2U",
 792                 SPR_NOACCESS, SPR_NOACCESS,
 793                 &spr_read_dbat, &spr_write_dbatu,
 794                 0x00000000);
 795    spr_register(env, SPR_DBAT2L, "DBAT2L",
 796                 SPR_NOACCESS, SPR_NOACCESS,
 797                 &spr_read_dbat, &spr_write_dbatl,
 798                 0x00000000);
 799    spr_register(env, SPR_DBAT3U, "DBAT3U",
 800                 SPR_NOACCESS, SPR_NOACCESS,
 801                 &spr_read_dbat, &spr_write_dbatu,
 802                 0x00000000);
 803    spr_register(env, SPR_DBAT3L, "DBAT3L",
 804                 SPR_NOACCESS, SPR_NOACCESS,
 805                 &spr_read_dbat, &spr_write_dbatl,
 806                 0x00000000);
 807    env->nb_BATs += 4;
 808#endif
 809}
 810
 811/* BATs 4-7 */
 812static void gen_high_BATs (CPUPPCState *env)
 813{
 814#if !defined(CONFIG_USER_ONLY)
 815    spr_register(env, SPR_IBAT4U, "IBAT4U",
 816                 SPR_NOACCESS, SPR_NOACCESS,
 817                 &spr_read_ibat_h, &spr_write_ibatu_h,
 818                 0x00000000);
 819    spr_register(env, SPR_IBAT4L, "IBAT4L",
 820                 SPR_NOACCESS, SPR_NOACCESS,
 821                 &spr_read_ibat_h, &spr_write_ibatl_h,
 822                 0x00000000);
 823    spr_register(env, SPR_IBAT5U, "IBAT5U",
 824                 SPR_NOACCESS, SPR_NOACCESS,
 825                 &spr_read_ibat_h, &spr_write_ibatu_h,
 826                 0x00000000);
 827    spr_register(env, SPR_IBAT5L, "IBAT5L",
 828                 SPR_NOACCESS, SPR_NOACCESS,
 829                 &spr_read_ibat_h, &spr_write_ibatl_h,
 830                 0x00000000);
 831    spr_register(env, SPR_IBAT6U, "IBAT6U",
 832                 SPR_NOACCESS, SPR_NOACCESS,
 833                 &spr_read_ibat_h, &spr_write_ibatu_h,
 834                 0x00000000);
 835    spr_register(env, SPR_IBAT6L, "IBAT6L",
 836                 SPR_NOACCESS, SPR_NOACCESS,
 837                 &spr_read_ibat_h, &spr_write_ibatl_h,
 838                 0x00000000);
 839    spr_register(env, SPR_IBAT7U, "IBAT7U",
 840                 SPR_NOACCESS, SPR_NOACCESS,
 841                 &spr_read_ibat_h, &spr_write_ibatu_h,
 842                 0x00000000);
 843    spr_register(env, SPR_IBAT7L, "IBAT7L",
 844                 SPR_NOACCESS, SPR_NOACCESS,
 845                 &spr_read_ibat_h, &spr_write_ibatl_h,
 846                 0x00000000);
 847    spr_register(env, SPR_DBAT4U, "DBAT4U",
 848                 SPR_NOACCESS, SPR_NOACCESS,
 849                 &spr_read_dbat_h, &spr_write_dbatu_h,
 850                 0x00000000);
 851    spr_register(env, SPR_DBAT4L, "DBAT4L",
 852                 SPR_NOACCESS, SPR_NOACCESS,
 853                 &spr_read_dbat_h, &spr_write_dbatl_h,
 854                 0x00000000);
 855    spr_register(env, SPR_DBAT5U, "DBAT5U",
 856                 SPR_NOACCESS, SPR_NOACCESS,
 857                 &spr_read_dbat_h, &spr_write_dbatu_h,
 858                 0x00000000);
 859    spr_register(env, SPR_DBAT5L, "DBAT5L",
 860                 SPR_NOACCESS, SPR_NOACCESS,
 861                 &spr_read_dbat_h, &spr_write_dbatl_h,
 862                 0x00000000);
 863    spr_register(env, SPR_DBAT6U, "DBAT6U",
 864                 SPR_NOACCESS, SPR_NOACCESS,
 865                 &spr_read_dbat_h, &spr_write_dbatu_h,
 866                 0x00000000);
 867    spr_register(env, SPR_DBAT6L, "DBAT6L",
 868                 SPR_NOACCESS, SPR_NOACCESS,
 869                 &spr_read_dbat_h, &spr_write_dbatl_h,
 870                 0x00000000);
 871    spr_register(env, SPR_DBAT7U, "DBAT7U",
 872                 SPR_NOACCESS, SPR_NOACCESS,
 873                 &spr_read_dbat_h, &spr_write_dbatu_h,
 874                 0x00000000);
 875    spr_register(env, SPR_DBAT7L, "DBAT7L",
 876                 SPR_NOACCESS, SPR_NOACCESS,
 877                 &spr_read_dbat_h, &spr_write_dbatl_h,
 878                 0x00000000);
 879    env->nb_BATs += 4;
 880#endif
 881}
 882
 883/* Generic PowerPC time base */
 884static void gen_tbl (CPUPPCState *env)
 885{
 886    spr_register(env, SPR_VTBL,  "TBL",
 887                 &spr_read_tbl, SPR_NOACCESS,
 888                 &spr_read_tbl, SPR_NOACCESS,
 889                 0x00000000);
 890    spr_register(env, SPR_TBL,   "TBL",
 891                 &spr_read_tbl, SPR_NOACCESS,
 892                 &spr_read_tbl, &spr_write_tbl,
 893                 0x00000000);
 894    spr_register(env, SPR_VTBU,  "TBU",
 895                 &spr_read_tbu, SPR_NOACCESS,
 896                 &spr_read_tbu, SPR_NOACCESS,
 897                 0x00000000);
 898    spr_register(env, SPR_TBU,   "TBU",
 899                 &spr_read_tbu, SPR_NOACCESS,
 900                 &spr_read_tbu, &spr_write_tbu,
 901                 0x00000000);
 902}
 903
 904/* Softare table search registers */
 905static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
 906{
 907#if !defined(CONFIG_USER_ONLY)
 908    env->nb_tlb = nb_tlbs;
 909    env->nb_ways = nb_ways;
 910    env->id_tlbs = 1;
 911    env->tlb_type = TLB_6XX;
 912    spr_register(env, SPR_DMISS, "DMISS",
 913                 SPR_NOACCESS, SPR_NOACCESS,
 914                 &spr_read_generic, SPR_NOACCESS,
 915                 0x00000000);
 916    spr_register(env, SPR_DCMP, "DCMP",
 917                 SPR_NOACCESS, SPR_NOACCESS,
 918                 &spr_read_generic, SPR_NOACCESS,
 919                 0x00000000);
 920    spr_register(env, SPR_HASH1, "HASH1",
 921                 SPR_NOACCESS, SPR_NOACCESS,
 922                 &spr_read_generic, SPR_NOACCESS,
 923                 0x00000000);
 924    spr_register(env, SPR_HASH2, "HASH2",
 925                 SPR_NOACCESS, SPR_NOACCESS,
 926                 &spr_read_generic, SPR_NOACCESS,
 927                 0x00000000);
 928    spr_register(env, SPR_IMISS, "IMISS",
 929                 SPR_NOACCESS, SPR_NOACCESS,
 930                 &spr_read_generic, SPR_NOACCESS,
 931                 0x00000000);
 932    spr_register(env, SPR_ICMP, "ICMP",
 933                 SPR_NOACCESS, SPR_NOACCESS,
 934                 &spr_read_generic, SPR_NOACCESS,
 935                 0x00000000);
 936    spr_register(env, SPR_RPA, "RPA",
 937                 SPR_NOACCESS, SPR_NOACCESS,
 938                 &spr_read_generic, &spr_write_generic,
 939                 0x00000000);
 940#endif
 941}
 942
 943/* SPR common to MPC755 and G2 */
 944static void gen_spr_G2_755 (CPUPPCState *env)
 945{
 946    /* SGPRs */
 947    spr_register(env, SPR_SPRG4, "SPRG4",
 948                 SPR_NOACCESS, SPR_NOACCESS,
 949                 &spr_read_generic, &spr_write_generic,
 950                 0x00000000);
 951    spr_register(env, SPR_SPRG5, "SPRG5",
 952                 SPR_NOACCESS, SPR_NOACCESS,
 953                 &spr_read_generic, &spr_write_generic,
 954                 0x00000000);
 955    spr_register(env, SPR_SPRG6, "SPRG6",
 956                 SPR_NOACCESS, SPR_NOACCESS,
 957                 &spr_read_generic, &spr_write_generic,
 958                 0x00000000);
 959    spr_register(env, SPR_SPRG7, "SPRG7",
 960                 SPR_NOACCESS, SPR_NOACCESS,
 961                 &spr_read_generic, &spr_write_generic,
 962                 0x00000000);
 963}
 964
 965/* SPR common to all 7xx PowerPC implementations */
 966static void gen_spr_7xx (CPUPPCState *env)
 967{
 968    /* Breakpoints */
 969    /* XXX : not implemented */
 970    spr_register_kvm(env, SPR_DABR, "DABR",
 971                     SPR_NOACCESS, SPR_NOACCESS,
 972                     &spr_read_generic, &spr_write_generic,
 973                     KVM_REG_PPC_DABR, 0x00000000);
 974    /* XXX : not implemented */
 975    spr_register(env, SPR_IABR, "IABR",
 976                 SPR_NOACCESS, SPR_NOACCESS,
 977                 &spr_read_generic, &spr_write_generic,
 978                 0x00000000);
 979    /* Cache management */
 980    /* XXX : not implemented */
 981    spr_register(env, SPR_ICTC, "ICTC",
 982                 SPR_NOACCESS, SPR_NOACCESS,
 983                 &spr_read_generic, &spr_write_generic,
 984                 0x00000000);
 985    /* Performance monitors */
 986    /* XXX : not implemented */
 987    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
 988                 SPR_NOACCESS, SPR_NOACCESS,
 989                 &spr_read_generic, &spr_write_generic,
 990                 0x00000000);
 991    /* XXX : not implemented */
 992    spr_register(env, SPR_7XX_MMCR1, "MMCR1",
 993                 SPR_NOACCESS, SPR_NOACCESS,
 994                 &spr_read_generic, &spr_write_generic,
 995                 0x00000000);
 996    /* XXX : not implemented */
 997    spr_register(env, SPR_7XX_PMC1, "PMC1",
 998                 SPR_NOACCESS, SPR_NOACCESS,
 999                 &spr_read_generic, &spr_write_generic,
1000                 0x00000000);
1001    /* XXX : not implemented */
1002    spr_register(env, SPR_7XX_PMC2, "PMC2",
1003                 SPR_NOACCESS, SPR_NOACCESS,
1004                 &spr_read_generic, &spr_write_generic,
1005                 0x00000000);
1006    /* XXX : not implemented */
1007    spr_register(env, SPR_7XX_PMC3, "PMC3",
1008                 SPR_NOACCESS, SPR_NOACCESS,
1009                 &spr_read_generic, &spr_write_generic,
1010                 0x00000000);
1011    /* XXX : not implemented */
1012    spr_register(env, SPR_7XX_PMC4, "PMC4",
1013                 SPR_NOACCESS, SPR_NOACCESS,
1014                 &spr_read_generic, &spr_write_generic,
1015                 0x00000000);
1016    /* XXX : not implemented */
1017    spr_register(env, SPR_7XX_SIAR, "SIAR",
1018                 SPR_NOACCESS, SPR_NOACCESS,
1019                 &spr_read_generic, SPR_NOACCESS,
1020                 0x00000000);
1021    /* XXX : not implemented */
1022    spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1023                 &spr_read_ureg, SPR_NOACCESS,
1024                 &spr_read_ureg, SPR_NOACCESS,
1025                 0x00000000);
1026    /* XXX : not implemented */
1027    spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1028                 &spr_read_ureg, SPR_NOACCESS,
1029                 &spr_read_ureg, SPR_NOACCESS,
1030                 0x00000000);
1031    /* XXX : not implemented */
1032    spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1033                 &spr_read_ureg, SPR_NOACCESS,
1034                 &spr_read_ureg, SPR_NOACCESS,
1035                 0x00000000);
1036    /* XXX : not implemented */
1037    spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1038                 &spr_read_ureg, SPR_NOACCESS,
1039                 &spr_read_ureg, SPR_NOACCESS,
1040                 0x00000000);
1041    /* XXX : not implemented */
1042    spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1043                 &spr_read_ureg, SPR_NOACCESS,
1044                 &spr_read_ureg, SPR_NOACCESS,
1045                 0x00000000);
1046    /* XXX : not implemented */
1047    spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1048                 &spr_read_ureg, SPR_NOACCESS,
1049                 &spr_read_ureg, SPR_NOACCESS,
1050                 0x00000000);
1051    /* XXX : not implemented */
1052    spr_register(env, SPR_7XX_USIAR, "USIAR",
1053                 &spr_read_ureg, SPR_NOACCESS,
1054                 &spr_read_ureg, SPR_NOACCESS,
1055                 0x00000000);
1056    /* External access control */
1057    /* XXX : not implemented */
1058    spr_register(env, SPR_EAR, "EAR",
1059                 SPR_NOACCESS, SPR_NOACCESS,
1060                 &spr_read_generic, &spr_write_generic,
1061                 0x00000000);
1062}
1063
1064#ifdef TARGET_PPC64
1065#ifndef CONFIG_USER_ONLY
1066static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1067{
1068    TCGv t0 = tcg_temp_new();
1069    TCGv t1 = tcg_temp_new();
1070    TCGv t2 = tcg_temp_new();
1071
1072    /* Note, the HV=1 PR=0 case is handled earlier by simply using
1073     * spr_write_generic for HV mode in the SPR table
1074     */
1075
1076    /* Build insertion mask into t1 based on context */
1077    if (ctx->pr) {
1078        gen_load_spr(t1, SPR_UAMOR);
1079    } else {
1080        gen_load_spr(t1, SPR_AMOR);
1081    }
1082
1083    /* Mask new bits into t2 */
1084    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1085
1086    /* Load AMR and clear new bits in t0 */
1087    gen_load_spr(t0, SPR_AMR);
1088    tcg_gen_andc_tl(t0, t0, t1);
1089
1090    /* Or'in new bits and write it out */
1091    tcg_gen_or_tl(t0, t0, t2);
1092    gen_store_spr(SPR_AMR, t0);
1093    spr_store_dump_spr(SPR_AMR);
1094
1095    tcg_temp_free(t0);
1096    tcg_temp_free(t1);
1097    tcg_temp_free(t2);
1098}
1099
1100static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1101{
1102    TCGv t0 = tcg_temp_new();
1103    TCGv t1 = tcg_temp_new();
1104    TCGv t2 = tcg_temp_new();
1105
1106    /* Note, the HV=1 case is handled earlier by simply using
1107     * spr_write_generic for HV mode in the SPR table
1108     */
1109
1110    /* Build insertion mask into t1 based on context */
1111    gen_load_spr(t1, SPR_AMOR);
1112
1113    /* Mask new bits into t2 */
1114    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1115
1116    /* Load AMR and clear new bits in t0 */
1117    gen_load_spr(t0, SPR_UAMOR);
1118    tcg_gen_andc_tl(t0, t0, t1);
1119
1120    /* Or'in new bits and write it out */
1121    tcg_gen_or_tl(t0, t0, t2);
1122    gen_store_spr(SPR_UAMOR, t0);
1123    spr_store_dump_spr(SPR_UAMOR);
1124
1125    tcg_temp_free(t0);
1126    tcg_temp_free(t1);
1127    tcg_temp_free(t2);
1128}
1129
1130static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1131{
1132    TCGv t0 = tcg_temp_new();
1133    TCGv t1 = tcg_temp_new();
1134    TCGv t2 = tcg_temp_new();
1135
1136    /* Note, the HV=1 case is handled earlier by simply using
1137     * spr_write_generic for HV mode in the SPR table
1138     */
1139
1140    /* Build insertion mask into t1 based on context */
1141    gen_load_spr(t1, SPR_AMOR);
1142
1143    /* Mask new bits into t2 */
1144    tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1145
1146    /* Load AMR and clear new bits in t0 */
1147    gen_load_spr(t0, SPR_IAMR);
1148    tcg_gen_andc_tl(t0, t0, t1);
1149
1150    /* Or'in new bits and write it out */
1151    tcg_gen_or_tl(t0, t0, t2);
1152    gen_store_spr(SPR_IAMR, t0);
1153    spr_store_dump_spr(SPR_IAMR);
1154
1155    tcg_temp_free(t0);
1156    tcg_temp_free(t1);
1157    tcg_temp_free(t2);
1158}
1159#endif /* CONFIG_USER_ONLY */
1160
1161static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1162{
1163#ifndef CONFIG_USER_ONLY
1164    /* Virtual Page Class Key protection */
1165    /* The AMR is accessible either via SPR 13 or SPR 29.  13 is
1166     * userspace accessible, 29 is privileged.  So we only need to set
1167     * the kvm ONE_REG id on one of them, we use 29 */
1168    spr_register(env, SPR_UAMR, "UAMR",
1169                 &spr_read_generic, &spr_write_amr,
1170                 &spr_read_generic, &spr_write_amr,
1171                 0);
1172    spr_register_kvm_hv(env, SPR_AMR, "AMR",
1173                     SPR_NOACCESS, SPR_NOACCESS,
1174                     &spr_read_generic, &spr_write_amr,
1175                     &spr_read_generic, &spr_write_generic,
1176                     KVM_REG_PPC_AMR, 0);
1177    spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1178                     SPR_NOACCESS, SPR_NOACCESS,
1179                     &spr_read_generic, &spr_write_uamor,
1180                     &spr_read_generic, &spr_write_generic,
1181                     KVM_REG_PPC_UAMOR, 0);
1182    spr_register_hv(env, SPR_AMOR, "AMOR",
1183                    SPR_NOACCESS, SPR_NOACCESS,
1184                    SPR_NOACCESS, SPR_NOACCESS,
1185                    &spr_read_generic, &spr_write_generic,
1186                    0);
1187    if (has_iamr) {
1188        spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1189                            SPR_NOACCESS, SPR_NOACCESS,
1190                            &spr_read_generic, &spr_write_iamr,
1191                            &spr_read_generic, &spr_write_generic,
1192                            KVM_REG_PPC_IAMR, 0);
1193    }
1194#endif /* !CONFIG_USER_ONLY */
1195}
1196#endif /* TARGET_PPC64 */
1197
1198static void gen_spr_thrm (CPUPPCState *env)
1199{
1200    /* Thermal management */
1201    /* XXX : not implemented */
1202    spr_register(env, SPR_THRM1, "THRM1",
1203                 SPR_NOACCESS, SPR_NOACCESS,
1204                 &spr_read_generic, &spr_write_generic,
1205                 0x00000000);
1206    /* XXX : not implemented */
1207    spr_register(env, SPR_THRM2, "THRM2",
1208                 SPR_NOACCESS, SPR_NOACCESS,
1209                 &spr_read_generic, &spr_write_generic,
1210                 0x00000000);
1211    /* XXX : not implemented */
1212    spr_register(env, SPR_THRM3, "THRM3",
1213                 SPR_NOACCESS, SPR_NOACCESS,
1214                 &spr_read_generic, &spr_write_generic,
1215                 0x00000000);
1216}
1217
1218/* SPR specific to PowerPC 604 implementation */
1219static void gen_spr_604 (CPUPPCState *env)
1220{
1221    /* Processor identification */
1222    spr_register(env, SPR_PIR, "PIR",
1223                 SPR_NOACCESS, SPR_NOACCESS,
1224                 &spr_read_generic, &spr_write_pir,
1225                 0x00000000);
1226    /* Breakpoints */
1227    /* XXX : not implemented */
1228    spr_register(env, SPR_IABR, "IABR",
1229                 SPR_NOACCESS, SPR_NOACCESS,
1230                 &spr_read_generic, &spr_write_generic,
1231                 0x00000000);
1232    /* XXX : not implemented */
1233    spr_register_kvm(env, SPR_DABR, "DABR",
1234                     SPR_NOACCESS, SPR_NOACCESS,
1235                     &spr_read_generic, &spr_write_generic,
1236                     KVM_REG_PPC_DABR, 0x00000000);
1237    /* Performance counters */
1238    /* XXX : not implemented */
1239    spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1240                 SPR_NOACCESS, SPR_NOACCESS,
1241                 &spr_read_generic, &spr_write_generic,
1242                 0x00000000);
1243    /* XXX : not implemented */
1244    spr_register(env, SPR_7XX_PMC1, "PMC1",
1245                 SPR_NOACCESS, SPR_NOACCESS,
1246                 &spr_read_generic, &spr_write_generic,
1247                 0x00000000);
1248    /* XXX : not implemented */
1249    spr_register(env, SPR_7XX_PMC2, "PMC2",
1250                 SPR_NOACCESS, SPR_NOACCESS,
1251                 &spr_read_generic, &spr_write_generic,
1252                 0x00000000);
1253    /* XXX : not implemented */
1254    spr_register(env, SPR_7XX_SIAR, "SIAR",
1255                 SPR_NOACCESS, SPR_NOACCESS,
1256                 &spr_read_generic, SPR_NOACCESS,
1257                 0x00000000);
1258    /* XXX : not implemented */
1259    spr_register(env, SPR_SDA, "SDA",
1260                 SPR_NOACCESS, SPR_NOACCESS,
1261                 &spr_read_generic, SPR_NOACCESS,
1262                 0x00000000);
1263    /* External access control */
1264    /* XXX : not implemented */
1265    spr_register(env, SPR_EAR, "EAR",
1266                 SPR_NOACCESS, SPR_NOACCESS,
1267                 &spr_read_generic, &spr_write_generic,
1268                 0x00000000);
1269}
1270
1271/* SPR specific to PowerPC 603 implementation */
1272static void gen_spr_603 (CPUPPCState *env)
1273{
1274    /* External access control */
1275    /* XXX : not implemented */
1276    spr_register(env, SPR_EAR, "EAR",
1277                 SPR_NOACCESS, SPR_NOACCESS,
1278                 &spr_read_generic, &spr_write_generic,
1279                 0x00000000);
1280    /* Breakpoints */
1281    /* XXX : not implemented */
1282    spr_register(env, SPR_IABR, "IABR",
1283                 SPR_NOACCESS, SPR_NOACCESS,
1284                 &spr_read_generic, &spr_write_generic,
1285                 0x00000000);
1286
1287}
1288
1289/* SPR specific to PowerPC G2 implementation */
1290static void gen_spr_G2 (CPUPPCState *env)
1291{
1292    /* Memory base address */
1293    /* MBAR */
1294    /* XXX : not implemented */
1295    spr_register(env, SPR_MBAR, "MBAR",
1296                 SPR_NOACCESS, SPR_NOACCESS,
1297                 &spr_read_generic, &spr_write_generic,
1298                 0x00000000);
1299    /* Exception processing */
1300    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1301                 SPR_NOACCESS, SPR_NOACCESS,
1302                 &spr_read_generic, &spr_write_generic,
1303                 0x00000000);
1304    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1305                 SPR_NOACCESS, SPR_NOACCESS,
1306                 &spr_read_generic, &spr_write_generic,
1307                 0x00000000);
1308    /* Breakpoints */
1309    /* XXX : not implemented */
1310    spr_register(env, SPR_DABR, "DABR",
1311                 SPR_NOACCESS, SPR_NOACCESS,
1312                 &spr_read_generic, &spr_write_generic,
1313                 0x00000000);
1314    /* XXX : not implemented */
1315    spr_register(env, SPR_DABR2, "DABR2",
1316                 SPR_NOACCESS, SPR_NOACCESS,
1317                 &spr_read_generic, &spr_write_generic,
1318                 0x00000000);
1319    /* XXX : not implemented */
1320    spr_register(env, SPR_IABR, "IABR",
1321                 SPR_NOACCESS, SPR_NOACCESS,
1322                 &spr_read_generic, &spr_write_generic,
1323                 0x00000000);
1324    /* XXX : not implemented */
1325    spr_register(env, SPR_IABR2, "IABR2",
1326                 SPR_NOACCESS, SPR_NOACCESS,
1327                 &spr_read_generic, &spr_write_generic,
1328                 0x00000000);
1329    /* XXX : not implemented */
1330    spr_register(env, SPR_IBCR, "IBCR",
1331                 SPR_NOACCESS, SPR_NOACCESS,
1332                 &spr_read_generic, &spr_write_generic,
1333                 0x00000000);
1334    /* XXX : not implemented */
1335    spr_register(env, SPR_DBCR, "DBCR",
1336                 SPR_NOACCESS, SPR_NOACCESS,
1337                 &spr_read_generic, &spr_write_generic,
1338                 0x00000000);
1339}
1340
1341/* SPR specific to PowerPC 602 implementation */
1342static void gen_spr_602 (CPUPPCState *env)
1343{
1344    /* ESA registers */
1345    /* XXX : not implemented */
1346    spr_register(env, SPR_SER, "SER",
1347                 SPR_NOACCESS, SPR_NOACCESS,
1348                 &spr_read_generic, &spr_write_generic,
1349                 0x00000000);
1350    /* XXX : not implemented */
1351    spr_register(env, SPR_SEBR, "SEBR",
1352                 SPR_NOACCESS, SPR_NOACCESS,
1353                 &spr_read_generic, &spr_write_generic,
1354                 0x00000000);
1355    /* XXX : not implemented */
1356    spr_register(env, SPR_ESASRR, "ESASRR",
1357                 SPR_NOACCESS, SPR_NOACCESS,
1358                 &spr_read_generic, &spr_write_generic,
1359                 0x00000000);
1360    /* Floating point status */
1361    /* XXX : not implemented */
1362    spr_register(env, SPR_SP, "SP",
1363                 SPR_NOACCESS, SPR_NOACCESS,
1364                 &spr_read_generic, &spr_write_generic,
1365                 0x00000000);
1366    /* XXX : not implemented */
1367    spr_register(env, SPR_LT, "LT",
1368                 SPR_NOACCESS, SPR_NOACCESS,
1369                 &spr_read_generic, &spr_write_generic,
1370                 0x00000000);
1371    /* Watchdog timer */
1372    /* XXX : not implemented */
1373    spr_register(env, SPR_TCR, "TCR",
1374                 SPR_NOACCESS, SPR_NOACCESS,
1375                 &spr_read_generic, &spr_write_generic,
1376                 0x00000000);
1377    /* Interrupt base */
1378    spr_register(env, SPR_IBR, "IBR",
1379                 SPR_NOACCESS, SPR_NOACCESS,
1380                 &spr_read_generic, &spr_write_generic,
1381                 0x00000000);
1382    /* XXX : not implemented */
1383    spr_register(env, SPR_IABR, "IABR",
1384                 SPR_NOACCESS, SPR_NOACCESS,
1385                 &spr_read_generic, &spr_write_generic,
1386                 0x00000000);
1387}
1388
1389/* SPR specific to PowerPC 601 implementation */
1390static void gen_spr_601 (CPUPPCState *env)
1391{
1392    /* Multiplication/division register */
1393    /* MQ */
1394    spr_register(env, SPR_MQ, "MQ",
1395                 &spr_read_generic, &spr_write_generic,
1396                 &spr_read_generic, &spr_write_generic,
1397                 0x00000000);
1398    /* RTC registers */
1399    spr_register(env, SPR_601_RTCU, "RTCU",
1400                 SPR_NOACCESS, SPR_NOACCESS,
1401                 SPR_NOACCESS, &spr_write_601_rtcu,
1402                 0x00000000);
1403    spr_register(env, SPR_601_VRTCU, "RTCU",
1404                 &spr_read_601_rtcu, SPR_NOACCESS,
1405                 &spr_read_601_rtcu, SPR_NOACCESS,
1406                 0x00000000);
1407    spr_register(env, SPR_601_RTCL, "RTCL",
1408                 SPR_NOACCESS, SPR_NOACCESS,
1409                 SPR_NOACCESS, &spr_write_601_rtcl,
1410                 0x00000000);
1411    spr_register(env, SPR_601_VRTCL, "RTCL",
1412                 &spr_read_601_rtcl, SPR_NOACCESS,
1413                 &spr_read_601_rtcl, SPR_NOACCESS,
1414                 0x00000000);
1415    /* Timer */
1416#if 0 /* ? */
1417    spr_register(env, SPR_601_UDECR, "UDECR",
1418                 &spr_read_decr, SPR_NOACCESS,
1419                 &spr_read_decr, SPR_NOACCESS,
1420                 0x00000000);
1421#endif
1422    /* External access control */
1423    /* XXX : not implemented */
1424    spr_register(env, SPR_EAR, "EAR",
1425                 SPR_NOACCESS, SPR_NOACCESS,
1426                 &spr_read_generic, &spr_write_generic,
1427                 0x00000000);
1428    /* Memory management */
1429#if !defined(CONFIG_USER_ONLY)
1430    spr_register(env, SPR_IBAT0U, "IBAT0U",
1431                 SPR_NOACCESS, SPR_NOACCESS,
1432                 &spr_read_601_ubat, &spr_write_601_ubatu,
1433                 0x00000000);
1434    spr_register(env, SPR_IBAT0L, "IBAT0L",
1435                 SPR_NOACCESS, SPR_NOACCESS,
1436                 &spr_read_601_ubat, &spr_write_601_ubatl,
1437                 0x00000000);
1438    spr_register(env, SPR_IBAT1U, "IBAT1U",
1439                 SPR_NOACCESS, SPR_NOACCESS,
1440                 &spr_read_601_ubat, &spr_write_601_ubatu,
1441                 0x00000000);
1442    spr_register(env, SPR_IBAT1L, "IBAT1L",
1443                 SPR_NOACCESS, SPR_NOACCESS,
1444                 &spr_read_601_ubat, &spr_write_601_ubatl,
1445                 0x00000000);
1446    spr_register(env, SPR_IBAT2U, "IBAT2U",
1447                 SPR_NOACCESS, SPR_NOACCESS,
1448                 &spr_read_601_ubat, &spr_write_601_ubatu,
1449                 0x00000000);
1450    spr_register(env, SPR_IBAT2L, "IBAT2L",
1451                 SPR_NOACCESS, SPR_NOACCESS,
1452                 &spr_read_601_ubat, &spr_write_601_ubatl,
1453                 0x00000000);
1454    spr_register(env, SPR_IBAT3U, "IBAT3U",
1455                 SPR_NOACCESS, SPR_NOACCESS,
1456                 &spr_read_601_ubat, &spr_write_601_ubatu,
1457                 0x00000000);
1458    spr_register(env, SPR_IBAT3L, "IBAT3L",
1459                 SPR_NOACCESS, SPR_NOACCESS,
1460                 &spr_read_601_ubat, &spr_write_601_ubatl,
1461                 0x00000000);
1462    env->nb_BATs = 4;
1463#endif
1464}
1465
1466static void gen_spr_74xx (CPUPPCState *env)
1467{
1468    /* Processor identification */
1469    spr_register(env, SPR_PIR, "PIR",
1470                 SPR_NOACCESS, SPR_NOACCESS,
1471                 &spr_read_generic, &spr_write_pir,
1472                 0x00000000);
1473    /* XXX : not implemented */
1474    spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1475                 SPR_NOACCESS, SPR_NOACCESS,
1476                 &spr_read_generic, &spr_write_generic,
1477                 0x00000000);
1478    /* XXX : not implemented */
1479    spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1480                 &spr_read_ureg, SPR_NOACCESS,
1481                 &spr_read_ureg, SPR_NOACCESS,
1482                 0x00000000);
1483    /* XXX: not implemented */
1484    spr_register(env, SPR_BAMR, "BAMR",
1485                 SPR_NOACCESS, SPR_NOACCESS,
1486                 &spr_read_generic, &spr_write_generic,
1487                 0x00000000);
1488    /* XXX : not implemented */
1489    spr_register(env, SPR_MSSCR0, "MSSCR0",
1490                 SPR_NOACCESS, SPR_NOACCESS,
1491                 &spr_read_generic, &spr_write_generic,
1492                 0x00000000);
1493    /* Hardware implementation registers */
1494    /* XXX : not implemented */
1495    spr_register(env, SPR_HID0, "HID0",
1496                 SPR_NOACCESS, SPR_NOACCESS,
1497                 &spr_read_generic, &spr_write_generic,
1498                 0x00000000);
1499    /* XXX : not implemented */
1500    spr_register(env, SPR_HID1, "HID1",
1501                 SPR_NOACCESS, SPR_NOACCESS,
1502                 &spr_read_generic, &spr_write_generic,
1503                 0x00000000);
1504    /* Altivec */
1505    spr_register(env, SPR_VRSAVE, "VRSAVE",
1506                 &spr_read_generic, &spr_write_generic,
1507                 &spr_read_generic, &spr_write_generic,
1508                 0x00000000);
1509    /* XXX : not implemented */
1510    spr_register(env, SPR_L2CR, "L2CR",
1511                 SPR_NOACCESS, SPR_NOACCESS,
1512                 &spr_read_generic, spr_access_nop,
1513                 0x00000000);
1514    /* Not strictly an SPR */
1515    vscr_init(env, 0x00010000);
1516}
1517
1518static void gen_l3_ctrl (CPUPPCState *env)
1519{
1520    /* L3CR */
1521    /* XXX : not implemented */
1522    spr_register(env, SPR_L3CR, "L3CR",
1523                 SPR_NOACCESS, SPR_NOACCESS,
1524                 &spr_read_generic, &spr_write_generic,
1525                 0x00000000);
1526    /* L3ITCR0 */
1527    /* XXX : not implemented */
1528    spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1529                 SPR_NOACCESS, SPR_NOACCESS,
1530                 &spr_read_generic, &spr_write_generic,
1531                 0x00000000);
1532    /* L3PM */
1533    /* XXX : not implemented */
1534    spr_register(env, SPR_L3PM, "L3PM",
1535                 SPR_NOACCESS, SPR_NOACCESS,
1536                 &spr_read_generic, &spr_write_generic,
1537                 0x00000000);
1538}
1539
1540static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1541{
1542#if !defined(CONFIG_USER_ONLY)
1543    env->nb_tlb = nb_tlbs;
1544    env->nb_ways = nb_ways;
1545    env->id_tlbs = 1;
1546    env->tlb_type = TLB_6XX;
1547    /* XXX : not implemented */
1548    spr_register(env, SPR_PTEHI, "PTEHI",
1549                 SPR_NOACCESS, SPR_NOACCESS,
1550                 &spr_read_generic, &spr_write_generic,
1551                 0x00000000);
1552    /* XXX : not implemented */
1553    spr_register(env, SPR_PTELO, "PTELO",
1554                 SPR_NOACCESS, SPR_NOACCESS,
1555                 &spr_read_generic, &spr_write_generic,
1556                 0x00000000);
1557    /* XXX : not implemented */
1558    spr_register(env, SPR_TLBMISS, "TLBMISS",
1559                 SPR_NOACCESS, SPR_NOACCESS,
1560                 &spr_read_generic, &spr_write_generic,
1561                 0x00000000);
1562#endif
1563}
1564
1565#if !defined(CONFIG_USER_ONLY)
1566static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1567{
1568    TCGv t0 = tcg_temp_new();
1569
1570    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1571    gen_store_spr(sprn, t0);
1572    tcg_temp_free(t0);
1573}
1574
1575static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1576{
1577    TCGv t0 = tcg_temp_new();
1578
1579    tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1580    gen_store_spr(sprn, t0);
1581    tcg_temp_free(t0);
1582}
1583
1584static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1585{
1586    gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1587}
1588
1589static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1590{
1591    TCGv_i32 t0 = tcg_const_i32(sprn);
1592    gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1593    tcg_temp_free_i32(t0);
1594}
1595#endif
1596
1597static void gen_spr_usprgh (CPUPPCState *env)
1598{
1599    spr_register(env, SPR_USPRG4, "USPRG4",
1600                 &spr_read_ureg, SPR_NOACCESS,
1601                 &spr_read_ureg, SPR_NOACCESS,
1602                 0x00000000);
1603    spr_register(env, SPR_USPRG5, "USPRG5",
1604                 &spr_read_ureg, SPR_NOACCESS,
1605                 &spr_read_ureg, SPR_NOACCESS,
1606                 0x00000000);
1607    spr_register(env, SPR_USPRG6, "USPRG6",
1608                 &spr_read_ureg, SPR_NOACCESS,
1609                 &spr_read_ureg, SPR_NOACCESS,
1610                 0x00000000);
1611    spr_register(env, SPR_USPRG7, "USPRG7",
1612                 &spr_read_ureg, SPR_NOACCESS,
1613                 &spr_read_ureg, SPR_NOACCESS,
1614                 0x00000000);
1615}
1616
1617/* PowerPC BookE SPR */
1618static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1619{
1620    const char *ivor_names[64] = {
1621        "IVOR0",  "IVOR1",  "IVOR2",  "IVOR3",
1622        "IVOR4",  "IVOR5",  "IVOR6",  "IVOR7",
1623        "IVOR8",  "IVOR9",  "IVOR10", "IVOR11",
1624        "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1625        "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1626        "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1627        "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1628        "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1629        "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1630        "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1631        "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1632        "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1633        "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1634        "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1635        "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1636        "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1637    };
1638#define SPR_BOOKE_IVORxx (-1)
1639    int ivor_sprn[64] = {
1640        SPR_BOOKE_IVOR0,  SPR_BOOKE_IVOR1,  SPR_BOOKE_IVOR2,  SPR_BOOKE_IVOR3,
1641        SPR_BOOKE_IVOR4,  SPR_BOOKE_IVOR5,  SPR_BOOKE_IVOR6,  SPR_BOOKE_IVOR7,
1642        SPR_BOOKE_IVOR8,  SPR_BOOKE_IVOR9,  SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1643        SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1644        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1645        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1646        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1647        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1648        SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1649        SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1650        SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1651        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1652        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1653        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1654        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1655        SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1656    };
1657    int i;
1658
1659    /* Interrupt processing */
1660    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1661                 SPR_NOACCESS, SPR_NOACCESS,
1662                 &spr_read_generic, &spr_write_generic,
1663                 0x00000000);
1664    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1665                 SPR_NOACCESS, SPR_NOACCESS,
1666                 &spr_read_generic, &spr_write_generic,
1667                 0x00000000);
1668    /* Debug */
1669    /* XXX : not implemented */
1670    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1671                 SPR_NOACCESS, SPR_NOACCESS,
1672                 &spr_read_generic, &spr_write_generic,
1673                 0x00000000);
1674    /* XXX : not implemented */
1675    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1676                 SPR_NOACCESS, SPR_NOACCESS,
1677                 &spr_read_generic, &spr_write_generic,
1678                 0x00000000);
1679    /* XXX : not implemented */
1680    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1681                 SPR_NOACCESS, SPR_NOACCESS,
1682                 &spr_read_generic, &spr_write_generic,
1683                 0x00000000);
1684    /* XXX : not implemented */
1685    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1686                 SPR_NOACCESS, SPR_NOACCESS,
1687                 &spr_read_generic, &spr_write_generic,
1688                 0x00000000);
1689    /* XXX : not implemented */
1690    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1691                 SPR_NOACCESS, SPR_NOACCESS,
1692                 &spr_read_generic, &spr_write_40x_dbcr0,
1693                 0x00000000);
1694    /* XXX : not implemented */
1695    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1696                 SPR_NOACCESS, SPR_NOACCESS,
1697                 &spr_read_generic, &spr_write_generic,
1698                 0x00000000);
1699    /* XXX : not implemented */
1700    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1701                 SPR_NOACCESS, SPR_NOACCESS,
1702                 &spr_read_generic, &spr_write_generic,
1703                 0x00000000);
1704    /* XXX : not implemented */
1705    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1706                 SPR_NOACCESS, SPR_NOACCESS,
1707                 &spr_read_generic, &spr_write_clear,
1708                 0x00000000);
1709    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1710                 SPR_NOACCESS, SPR_NOACCESS,
1711                 &spr_read_generic, &spr_write_generic,
1712                 0x00000000);
1713    spr_register(env, SPR_BOOKE_ESR, "ESR",
1714                 SPR_NOACCESS, SPR_NOACCESS,
1715                 &spr_read_generic, &spr_write_generic,
1716                 0x00000000);
1717    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1718                 SPR_NOACCESS, SPR_NOACCESS,
1719                 &spr_read_generic, &spr_write_excp_prefix,
1720                 0x00000000);
1721    /* Exception vectors */
1722    for (i = 0; i < 64; i++) {
1723        if (ivor_mask & (1ULL << i)) {
1724            if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1725                fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1726                exit(1);
1727            }
1728            spr_register(env, ivor_sprn[i], ivor_names[i],
1729                         SPR_NOACCESS, SPR_NOACCESS,
1730                         &spr_read_generic, &spr_write_excp_vector,
1731                         0x00000000);
1732        }
1733    }
1734    spr_register(env, SPR_BOOKE_PID, "PID",
1735                 SPR_NOACCESS, SPR_NOACCESS,
1736                 &spr_read_generic, &spr_write_booke_pid,
1737                 0x00000000);
1738    spr_register(env, SPR_BOOKE_TCR, "TCR",
1739                 SPR_NOACCESS, SPR_NOACCESS,
1740                 &spr_read_generic, &spr_write_booke_tcr,
1741                 0x00000000);
1742    spr_register(env, SPR_BOOKE_TSR, "TSR",
1743                 SPR_NOACCESS, SPR_NOACCESS,
1744                 &spr_read_generic, &spr_write_booke_tsr,
1745                 0x00000000);
1746    /* Timer */
1747    spr_register(env, SPR_DECR, "DECR",
1748                 SPR_NOACCESS, SPR_NOACCESS,
1749                 &spr_read_decr, &spr_write_decr,
1750                 0x00000000);
1751    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1752                 SPR_NOACCESS, SPR_NOACCESS,
1753                 SPR_NOACCESS, &spr_write_generic,
1754                 0x00000000);
1755    /* SPRGs */
1756    spr_register(env, SPR_USPRG0, "USPRG0",
1757                 &spr_read_generic, &spr_write_generic,
1758                 &spr_read_generic, &spr_write_generic,
1759                 0x00000000);
1760    spr_register(env, SPR_SPRG4, "SPRG4",
1761                 SPR_NOACCESS, SPR_NOACCESS,
1762                 &spr_read_generic, &spr_write_generic,
1763                 0x00000000);
1764    spr_register(env, SPR_SPRG5, "SPRG5",
1765                 SPR_NOACCESS, SPR_NOACCESS,
1766                 &spr_read_generic, &spr_write_generic,
1767                 0x00000000);
1768    spr_register(env, SPR_SPRG6, "SPRG6",
1769                 SPR_NOACCESS, SPR_NOACCESS,
1770                 &spr_read_generic, &spr_write_generic,
1771                 0x00000000);
1772    spr_register(env, SPR_SPRG7, "SPRG7",
1773                 SPR_NOACCESS, SPR_NOACCESS,
1774                 &spr_read_generic, &spr_write_generic,
1775                 0x00000000);
1776}
1777
1778static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1779                                   uint32_t maxsize, uint32_t flags,
1780                                   uint32_t nentries)
1781{
1782    return (assoc << TLBnCFG_ASSOC_SHIFT) |
1783           (minsize << TLBnCFG_MINSIZE_SHIFT) |
1784           (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1785           flags | nentries;
1786}
1787
1788/* BookE 2.06 storage control registers */
1789static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1790                              uint32_t *tlbncfg)
1791{
1792#if !defined(CONFIG_USER_ONLY)
1793    const char *mas_names[8] = {
1794        "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1795    };
1796    int mas_sprn[8] = {
1797        SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1798        SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1799    };
1800    int i;
1801
1802    /* TLB assist registers */
1803    /* XXX : not implemented */
1804    for (i = 0; i < 8; i++) {
1805        void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1806        if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1807            uea_write = &spr_write_generic;
1808        }
1809        if (mas_mask & (1 << i)) {
1810            spr_register(env, mas_sprn[i], mas_names[i],
1811                         SPR_NOACCESS, SPR_NOACCESS,
1812                         &spr_read_generic, uea_write,
1813                         0x00000000);
1814        }
1815    }
1816    if (env->nb_pids > 1) {
1817        /* XXX : not implemented */
1818        spr_register(env, SPR_BOOKE_PID1, "PID1",
1819                     SPR_NOACCESS, SPR_NOACCESS,
1820                     &spr_read_generic, &spr_write_booke_pid,
1821                     0x00000000);
1822    }
1823    if (env->nb_pids > 2) {
1824        /* XXX : not implemented */
1825        spr_register(env, SPR_BOOKE_PID2, "PID2",
1826                     SPR_NOACCESS, SPR_NOACCESS,
1827                     &spr_read_generic, &spr_write_booke_pid,
1828                     0x00000000);
1829    }
1830    /* XXX : not implemented */
1831    spr_register(env, SPR_MMUCFG, "MMUCFG",
1832                 SPR_NOACCESS, SPR_NOACCESS,
1833                 &spr_read_generic, SPR_NOACCESS,
1834                 0x00000000); /* TOFIX */
1835    switch (env->nb_ways) {
1836    case 4:
1837        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1838                     SPR_NOACCESS, SPR_NOACCESS,
1839                     &spr_read_generic, SPR_NOACCESS,
1840                     tlbncfg[3]);
1841        /* Fallthru */
1842    case 3:
1843        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1844                     SPR_NOACCESS, SPR_NOACCESS,
1845                     &spr_read_generic, SPR_NOACCESS,
1846                     tlbncfg[2]);
1847        /* Fallthru */
1848    case 2:
1849        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1850                     SPR_NOACCESS, SPR_NOACCESS,
1851                     &spr_read_generic, SPR_NOACCESS,
1852                     tlbncfg[1]);
1853        /* Fallthru */
1854    case 1:
1855        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1856                     SPR_NOACCESS, SPR_NOACCESS,
1857                     &spr_read_generic, SPR_NOACCESS,
1858                     tlbncfg[0]);
1859        /* Fallthru */
1860    case 0:
1861    default:
1862        break;
1863    }
1864#endif
1865
1866    gen_spr_usprgh(env);
1867}
1868
1869/* SPR specific to PowerPC 440 implementation */
1870static void gen_spr_440 (CPUPPCState *env)
1871{
1872    /* Cache control */
1873    /* XXX : not implemented */
1874    spr_register(env, SPR_440_DNV0, "DNV0",
1875                 SPR_NOACCESS, SPR_NOACCESS,
1876                 &spr_read_generic, &spr_write_generic,
1877                 0x00000000);
1878    /* XXX : not implemented */
1879    spr_register(env, SPR_440_DNV1, "DNV1",
1880                 SPR_NOACCESS, SPR_NOACCESS,
1881                 &spr_read_generic, &spr_write_generic,
1882                 0x00000000);
1883    /* XXX : not implemented */
1884    spr_register(env, SPR_440_DNV2, "DNV2",
1885                 SPR_NOACCESS, SPR_NOACCESS,
1886                 &spr_read_generic, &spr_write_generic,
1887                 0x00000000);
1888    /* XXX : not implemented */
1889    spr_register(env, SPR_440_DNV3, "DNV3",
1890                 SPR_NOACCESS, SPR_NOACCESS,
1891                 &spr_read_generic, &spr_write_generic,
1892                 0x00000000);
1893    /* XXX : not implemented */
1894    spr_register(env, SPR_440_DTV0, "DTV0",
1895                 SPR_NOACCESS, SPR_NOACCESS,
1896                 &spr_read_generic, &spr_write_generic,
1897                 0x00000000);
1898    /* XXX : not implemented */
1899    spr_register(env, SPR_440_DTV1, "DTV1",
1900                 SPR_NOACCESS, SPR_NOACCESS,
1901                 &spr_read_generic, &spr_write_generic,
1902                 0x00000000);
1903    /* XXX : not implemented */
1904    spr_register(env, SPR_440_DTV2, "DTV2",
1905                 SPR_NOACCESS, SPR_NOACCESS,
1906                 &spr_read_generic, &spr_write_generic,
1907                 0x00000000);
1908    /* XXX : not implemented */
1909    spr_register(env, SPR_440_DTV3, "DTV3",
1910                 SPR_NOACCESS, SPR_NOACCESS,
1911                 &spr_read_generic, &spr_write_generic,
1912                 0x00000000);
1913    /* XXX : not implemented */
1914    spr_register(env, SPR_440_DVLIM, "DVLIM",
1915                 SPR_NOACCESS, SPR_NOACCESS,
1916                 &spr_read_generic, &spr_write_generic,
1917                 0x00000000);
1918    /* XXX : not implemented */
1919    spr_register(env, SPR_440_INV0, "INV0",
1920                 SPR_NOACCESS, SPR_NOACCESS,
1921                 &spr_read_generic, &spr_write_generic,
1922                 0x00000000);
1923    /* XXX : not implemented */
1924    spr_register(env, SPR_440_INV1, "INV1",
1925                 SPR_NOACCESS, SPR_NOACCESS,
1926                 &spr_read_generic, &spr_write_generic,
1927                 0x00000000);
1928    /* XXX : not implemented */
1929    spr_register(env, SPR_440_INV2, "INV2",
1930                 SPR_NOACCESS, SPR_NOACCESS,
1931                 &spr_read_generic, &spr_write_generic,
1932                 0x00000000);
1933    /* XXX : not implemented */
1934    spr_register(env, SPR_440_INV3, "INV3",
1935                 SPR_NOACCESS, SPR_NOACCESS,
1936                 &spr_read_generic, &spr_write_generic,
1937                 0x00000000);
1938    /* XXX : not implemented */
1939    spr_register(env, SPR_440_ITV0, "ITV0",
1940                 SPR_NOACCESS, SPR_NOACCESS,
1941                 &spr_read_generic, &spr_write_generic,
1942                 0x00000000);
1943    /* XXX : not implemented */
1944    spr_register(env, SPR_440_ITV1, "ITV1",
1945                 SPR_NOACCESS, SPR_NOACCESS,
1946                 &spr_read_generic, &spr_write_generic,
1947                 0x00000000);
1948    /* XXX : not implemented */
1949    spr_register(env, SPR_440_ITV2, "ITV2",
1950                 SPR_NOACCESS, SPR_NOACCESS,
1951                 &spr_read_generic, &spr_write_generic,
1952                 0x00000000);
1953    /* XXX : not implemented */
1954    spr_register(env, SPR_440_ITV3, "ITV3",
1955                 SPR_NOACCESS, SPR_NOACCESS,
1956                 &spr_read_generic, &spr_write_generic,
1957                 0x00000000);
1958    /* XXX : not implemented */
1959    spr_register(env, SPR_440_IVLIM, "IVLIM",
1960                 SPR_NOACCESS, SPR_NOACCESS,
1961                 &spr_read_generic, &spr_write_generic,
1962                 0x00000000);
1963    /* Cache debug */
1964    /* XXX : not implemented */
1965    spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1966                 SPR_NOACCESS, SPR_NOACCESS,
1967                 &spr_read_generic, SPR_NOACCESS,
1968                 0x00000000);
1969    /* XXX : not implemented */
1970    spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1971                 SPR_NOACCESS, SPR_NOACCESS,
1972                 &spr_read_generic, SPR_NOACCESS,
1973                 0x00000000);
1974    /* XXX : not implemented */
1975    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1976                 SPR_NOACCESS, SPR_NOACCESS,
1977                 &spr_read_generic, SPR_NOACCESS,
1978                 0x00000000);
1979    /* XXX : not implemented */
1980    spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1981                 SPR_NOACCESS, SPR_NOACCESS,
1982                 &spr_read_generic, SPR_NOACCESS,
1983                 0x00000000);
1984    /* XXX : not implemented */
1985    spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1986                 SPR_NOACCESS, SPR_NOACCESS,
1987                 &spr_read_generic, SPR_NOACCESS,
1988                 0x00000000);
1989    /* XXX : not implemented */
1990    spr_register(env, SPR_440_DBDR, "DBDR",
1991                 SPR_NOACCESS, SPR_NOACCESS,
1992                 &spr_read_generic, &spr_write_generic,
1993                 0x00000000);
1994    /* Processor control */
1995    spr_register(env, SPR_4xx_CCR0, "CCR0",
1996                 SPR_NOACCESS, SPR_NOACCESS,
1997                 &spr_read_generic, &spr_write_generic,
1998                 0x00000000);
1999    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2000                 SPR_NOACCESS, SPR_NOACCESS,
2001                 &spr_read_generic, SPR_NOACCESS,
2002                 0x00000000);
2003    /* Storage control */
2004    spr_register(env, SPR_440_MMUCR, "MMUCR",
2005                 SPR_NOACCESS, SPR_NOACCESS,
2006                 &spr_read_generic, &spr_write_generic,
2007                 0x00000000);
2008}
2009
2010/* SPR shared between PowerPC 40x implementations */
2011static void gen_spr_40x (CPUPPCState *env)
2012{
2013    /* Cache */
2014    /* not emulated, as QEMU do not emulate caches */
2015    spr_register(env, SPR_40x_DCCR, "DCCR",
2016                 SPR_NOACCESS, SPR_NOACCESS,
2017                 &spr_read_generic, &spr_write_generic,
2018                 0x00000000);
2019    /* not emulated, as QEMU do not emulate caches */
2020    spr_register(env, SPR_40x_ICCR, "ICCR",
2021                 SPR_NOACCESS, SPR_NOACCESS,
2022                 &spr_read_generic, &spr_write_generic,
2023                 0x00000000);
2024    /* not emulated, as QEMU do not emulate caches */
2025    spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2026                 SPR_NOACCESS, SPR_NOACCESS,
2027                 &spr_read_generic, SPR_NOACCESS,
2028                 0x00000000);
2029    /* Exception */
2030    spr_register(env, SPR_40x_DEAR, "DEAR",
2031                 SPR_NOACCESS, SPR_NOACCESS,
2032                 &spr_read_generic, &spr_write_generic,
2033                 0x00000000);
2034    spr_register(env, SPR_40x_ESR, "ESR",
2035                 SPR_NOACCESS, SPR_NOACCESS,
2036                 &spr_read_generic, &spr_write_generic,
2037                 0x00000000);
2038    spr_register(env, SPR_40x_EVPR, "EVPR",
2039                 SPR_NOACCESS, SPR_NOACCESS,
2040                 &spr_read_generic, &spr_write_excp_prefix,
2041                 0x00000000);
2042    spr_register(env, SPR_40x_SRR2, "SRR2",
2043                 &spr_read_generic, &spr_write_generic,
2044                 &spr_read_generic, &spr_write_generic,
2045                 0x00000000);
2046    spr_register(env, SPR_40x_SRR3, "SRR3",
2047                 &spr_read_generic, &spr_write_generic,
2048                 &spr_read_generic, &spr_write_generic,
2049                 0x00000000);
2050    /* Timers */
2051    spr_register(env, SPR_40x_PIT, "PIT",
2052                 SPR_NOACCESS, SPR_NOACCESS,
2053                 &spr_read_40x_pit, &spr_write_40x_pit,
2054                 0x00000000);
2055    spr_register(env, SPR_40x_TCR, "TCR",
2056                 SPR_NOACCESS, SPR_NOACCESS,
2057                 &spr_read_generic, &spr_write_booke_tcr,
2058                 0x00000000);
2059    spr_register(env, SPR_40x_TSR, "TSR",
2060                 SPR_NOACCESS, SPR_NOACCESS,
2061                 &spr_read_generic, &spr_write_booke_tsr,
2062                 0x00000000);
2063}
2064
2065/* SPR specific to PowerPC 405 implementation */
2066static void gen_spr_405 (CPUPPCState *env)
2067{
2068    /* MMU */
2069    spr_register(env, SPR_40x_PID, "PID",
2070                 SPR_NOACCESS, SPR_NOACCESS,
2071                 &spr_read_generic, &spr_write_generic,
2072                 0x00000000);
2073    spr_register(env, SPR_4xx_CCR0, "CCR0",
2074                 SPR_NOACCESS, SPR_NOACCESS,
2075                 &spr_read_generic, &spr_write_generic,
2076                 0x00700000);
2077    /* Debug interface */
2078    /* XXX : not implemented */
2079    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2080                 SPR_NOACCESS, SPR_NOACCESS,
2081                 &spr_read_generic, &spr_write_40x_dbcr0,
2082                 0x00000000);
2083    /* XXX : not implemented */
2084    spr_register(env, SPR_405_DBCR1, "DBCR1",
2085                 SPR_NOACCESS, SPR_NOACCESS,
2086                 &spr_read_generic, &spr_write_generic,
2087                 0x00000000);
2088    /* XXX : not implemented */
2089    spr_register(env, SPR_40x_DBSR, "DBSR",
2090                 SPR_NOACCESS, SPR_NOACCESS,
2091                 &spr_read_generic, &spr_write_clear,
2092                 /* Last reset was system reset */
2093                 0x00000300);
2094    /* XXX : not implemented */
2095    spr_register(env, SPR_40x_DAC1, "DAC1",
2096                 SPR_NOACCESS, SPR_NOACCESS,
2097                 &spr_read_generic, &spr_write_generic,
2098                 0x00000000);
2099    spr_register(env, SPR_40x_DAC2, "DAC2",
2100                 SPR_NOACCESS, SPR_NOACCESS,
2101                 &spr_read_generic, &spr_write_generic,
2102                 0x00000000);
2103    /* XXX : not implemented */
2104    spr_register(env, SPR_405_DVC1, "DVC1",
2105                 SPR_NOACCESS, SPR_NOACCESS,
2106                 &spr_read_generic, &spr_write_generic,
2107                 0x00000000);
2108    /* XXX : not implemented */
2109    spr_register(env, SPR_405_DVC2, "DVC2",
2110                 SPR_NOACCESS, SPR_NOACCESS,
2111                 &spr_read_generic, &spr_write_generic,
2112                 0x00000000);
2113    /* XXX : not implemented */
2114    spr_register(env, SPR_40x_IAC1, "IAC1",
2115                 SPR_NOACCESS, SPR_NOACCESS,
2116                 &spr_read_generic, &spr_write_generic,
2117                 0x00000000);
2118    spr_register(env, SPR_40x_IAC2, "IAC2",
2119                 SPR_NOACCESS, SPR_NOACCESS,
2120                 &spr_read_generic, &spr_write_generic,
2121                 0x00000000);
2122    /* XXX : not implemented */
2123    spr_register(env, SPR_405_IAC3, "IAC3",
2124                 SPR_NOACCESS, SPR_NOACCESS,
2125                 &spr_read_generic, &spr_write_generic,
2126                 0x00000000);
2127    /* XXX : not implemented */
2128    spr_register(env, SPR_405_IAC4, "IAC4",
2129                 SPR_NOACCESS, SPR_NOACCESS,
2130                 &spr_read_generic, &spr_write_generic,
2131                 0x00000000);
2132    /* Storage control */
2133    /* XXX: TODO: not implemented */
2134    spr_register(env, SPR_405_SLER, "SLER",
2135                 SPR_NOACCESS, SPR_NOACCESS,
2136                 &spr_read_generic, &spr_write_40x_sler,
2137                 0x00000000);
2138    spr_register(env, SPR_40x_ZPR, "ZPR",
2139                 SPR_NOACCESS, SPR_NOACCESS,
2140                 &spr_read_generic, &spr_write_generic,
2141                 0x00000000);
2142    /* XXX : not implemented */
2143    spr_register(env, SPR_405_SU0R, "SU0R",
2144                 SPR_NOACCESS, SPR_NOACCESS,
2145                 &spr_read_generic, &spr_write_generic,
2146                 0x00000000);
2147    /* SPRG */
2148    spr_register(env, SPR_USPRG0, "USPRG0",
2149                 &spr_read_ureg, SPR_NOACCESS,
2150                 &spr_read_ureg, SPR_NOACCESS,
2151                 0x00000000);
2152    spr_register(env, SPR_SPRG4, "SPRG4",
2153                 SPR_NOACCESS, SPR_NOACCESS,
2154                 &spr_read_generic, &spr_write_generic,
2155                 0x00000000);
2156    spr_register(env, SPR_SPRG5, "SPRG5",
2157                 SPR_NOACCESS, SPR_NOACCESS,
2158                 spr_read_generic, &spr_write_generic,
2159                 0x00000000);
2160    spr_register(env, SPR_SPRG6, "SPRG6",
2161                 SPR_NOACCESS, SPR_NOACCESS,
2162                 spr_read_generic, &spr_write_generic,
2163                 0x00000000);
2164    spr_register(env, SPR_SPRG7, "SPRG7",
2165                 SPR_NOACCESS, SPR_NOACCESS,
2166                 spr_read_generic, &spr_write_generic,
2167                 0x00000000);
2168    gen_spr_usprgh(env);
2169}
2170
2171/* SPR shared between PowerPC 401 & 403 implementations */
2172static void gen_spr_401_403 (CPUPPCState *env)
2173{
2174    /* Time base */
2175    spr_register(env, SPR_403_VTBL,  "TBL",
2176                 &spr_read_tbl, SPR_NOACCESS,
2177                 &spr_read_tbl, SPR_NOACCESS,
2178                 0x00000000);
2179    spr_register(env, SPR_403_TBL,   "TBL",
2180                 SPR_NOACCESS, SPR_NOACCESS,
2181                 SPR_NOACCESS, &spr_write_tbl,
2182                 0x00000000);
2183    spr_register(env, SPR_403_VTBU,  "TBU",
2184                 &spr_read_tbu, SPR_NOACCESS,
2185                 &spr_read_tbu, SPR_NOACCESS,
2186                 0x00000000);
2187    spr_register(env, SPR_403_TBU,   "TBU",
2188                 SPR_NOACCESS, SPR_NOACCESS,
2189                 SPR_NOACCESS, &spr_write_tbu,
2190                 0x00000000);
2191    /* Debug */
2192    /* not emulated, as QEMU do not emulate caches */
2193    spr_register(env, SPR_403_CDBCR, "CDBCR",
2194                 SPR_NOACCESS, SPR_NOACCESS,
2195                 &spr_read_generic, &spr_write_generic,
2196                 0x00000000);
2197}
2198
2199/* SPR specific to PowerPC 401 implementation */
2200static void gen_spr_401 (CPUPPCState *env)
2201{
2202    /* Debug interface */
2203    /* XXX : not implemented */
2204    spr_register(env, SPR_40x_DBCR0, "DBCR",
2205                 SPR_NOACCESS, SPR_NOACCESS,
2206                 &spr_read_generic, &spr_write_40x_dbcr0,
2207                 0x00000000);
2208    /* XXX : not implemented */
2209    spr_register(env, SPR_40x_DBSR, "DBSR",
2210                 SPR_NOACCESS, SPR_NOACCESS,
2211                 &spr_read_generic, &spr_write_clear,
2212                 /* Last reset was system reset */
2213                 0x00000300);
2214    /* XXX : not implemented */
2215    spr_register(env, SPR_40x_DAC1, "DAC",
2216                 SPR_NOACCESS, SPR_NOACCESS,
2217                 &spr_read_generic, &spr_write_generic,
2218                 0x00000000);
2219    /* XXX : not implemented */
2220    spr_register(env, SPR_40x_IAC1, "IAC",
2221                 SPR_NOACCESS, SPR_NOACCESS,
2222                 &spr_read_generic, &spr_write_generic,
2223                 0x00000000);
2224    /* Storage control */
2225    /* XXX: TODO: not implemented */
2226    spr_register(env, SPR_405_SLER, "SLER",
2227                 SPR_NOACCESS, SPR_NOACCESS,
2228                 &spr_read_generic, &spr_write_40x_sler,
2229                 0x00000000);
2230    /* not emulated, as QEMU never does speculative access */
2231    spr_register(env, SPR_40x_SGR, "SGR",
2232                 SPR_NOACCESS, SPR_NOACCESS,
2233                 &spr_read_generic, &spr_write_generic,
2234                 0xFFFFFFFF);
2235    /* not emulated, as QEMU do not emulate caches */
2236    spr_register(env, SPR_40x_DCWR, "DCWR",
2237                 SPR_NOACCESS, SPR_NOACCESS,
2238                 &spr_read_generic, &spr_write_generic,
2239                 0x00000000);
2240}
2241
2242static void gen_spr_401x2 (CPUPPCState *env)
2243{
2244    gen_spr_401(env);
2245    spr_register(env, SPR_40x_PID, "PID",
2246                 SPR_NOACCESS, SPR_NOACCESS,
2247                 &spr_read_generic, &spr_write_generic,
2248                 0x00000000);
2249    spr_register(env, SPR_40x_ZPR, "ZPR",
2250                 SPR_NOACCESS, SPR_NOACCESS,
2251                 &spr_read_generic, &spr_write_generic,
2252                 0x00000000);
2253}
2254
2255/* SPR specific to PowerPC 403 implementation */
2256static void gen_spr_403 (CPUPPCState *env)
2257{
2258    /* Debug interface */
2259    /* XXX : not implemented */
2260    spr_register(env, SPR_40x_DBCR0, "DBCR0",
2261                 SPR_NOACCESS, SPR_NOACCESS,
2262                 &spr_read_generic, &spr_write_40x_dbcr0,
2263                 0x00000000);
2264    /* XXX : not implemented */
2265    spr_register(env, SPR_40x_DBSR, "DBSR",
2266                 SPR_NOACCESS, SPR_NOACCESS,
2267                 &spr_read_generic, &spr_write_clear,
2268                 /* Last reset was system reset */
2269                 0x00000300);
2270    /* XXX : not implemented */
2271    spr_register(env, SPR_40x_DAC1, "DAC1",
2272                 SPR_NOACCESS, SPR_NOACCESS,
2273                 &spr_read_generic, &spr_write_generic,
2274                 0x00000000);
2275    /* XXX : not implemented */
2276    spr_register(env, SPR_40x_DAC2, "DAC2",
2277                 SPR_NOACCESS, SPR_NOACCESS,
2278                 &spr_read_generic, &spr_write_generic,
2279                 0x00000000);
2280    /* XXX : not implemented */
2281    spr_register(env, SPR_40x_IAC1, "IAC1",
2282                 SPR_NOACCESS, SPR_NOACCESS,
2283                 &spr_read_generic, &spr_write_generic,
2284                 0x00000000);
2285    /* XXX : not implemented */
2286    spr_register(env, SPR_40x_IAC2, "IAC2",
2287                 SPR_NOACCESS, SPR_NOACCESS,
2288                 &spr_read_generic, &spr_write_generic,
2289                 0x00000000);
2290}
2291
2292static void gen_spr_403_real (CPUPPCState *env)
2293{
2294    spr_register(env, SPR_403_PBL1,  "PBL1",
2295                 SPR_NOACCESS, SPR_NOACCESS,
2296                 &spr_read_403_pbr, &spr_write_403_pbr,
2297                 0x00000000);
2298    spr_register(env, SPR_403_PBU1,  "PBU1",
2299                 SPR_NOACCESS, SPR_NOACCESS,
2300                 &spr_read_403_pbr, &spr_write_403_pbr,
2301                 0x00000000);
2302    spr_register(env, SPR_403_PBL2,  "PBL2",
2303                 SPR_NOACCESS, SPR_NOACCESS,
2304                 &spr_read_403_pbr, &spr_write_403_pbr,
2305                 0x00000000);
2306    spr_register(env, SPR_403_PBU2,  "PBU2",
2307                 SPR_NOACCESS, SPR_NOACCESS,
2308                 &spr_read_403_pbr, &spr_write_403_pbr,
2309                 0x00000000);
2310}
2311
2312static void gen_spr_403_mmu (CPUPPCState *env)
2313{
2314    /* MMU */
2315    spr_register(env, SPR_40x_PID, "PID",
2316                 SPR_NOACCESS, SPR_NOACCESS,
2317                 &spr_read_generic, &spr_write_generic,
2318                 0x00000000);
2319    spr_register(env, SPR_40x_ZPR, "ZPR",
2320                 SPR_NOACCESS, SPR_NOACCESS,
2321                 &spr_read_generic, &spr_write_generic,
2322                 0x00000000);
2323}
2324
2325/* SPR specific to PowerPC compression coprocessor extension */
2326static void gen_spr_compress (CPUPPCState *env)
2327{
2328    /* XXX : not implemented */
2329    spr_register(env, SPR_401_SKR, "SKR",
2330                 SPR_NOACCESS, SPR_NOACCESS,
2331                 &spr_read_generic, &spr_write_generic,
2332                 0x00000000);
2333}
2334
2335static void gen_spr_5xx_8xx (CPUPPCState *env)
2336{
2337    /* Exception processing */
2338    spr_register_kvm(env, SPR_DSISR, "DSISR",
2339                     SPR_NOACCESS, SPR_NOACCESS,
2340                     &spr_read_generic, &spr_write_generic,
2341                     KVM_REG_PPC_DSISR, 0x00000000);
2342    spr_register_kvm(env, SPR_DAR, "DAR",
2343                     SPR_NOACCESS, SPR_NOACCESS,
2344                     &spr_read_generic, &spr_write_generic,
2345                     KVM_REG_PPC_DAR, 0x00000000);
2346    /* Timer */
2347    spr_register(env, SPR_DECR, "DECR",
2348                 SPR_NOACCESS, SPR_NOACCESS,
2349                 &spr_read_decr, &spr_write_decr,
2350                 0x00000000);
2351    /* XXX : not implemented */
2352    spr_register(env, SPR_MPC_EIE, "EIE",
2353                 SPR_NOACCESS, SPR_NOACCESS,
2354                 &spr_read_generic, &spr_write_generic,
2355                 0x00000000);
2356    /* XXX : not implemented */
2357    spr_register(env, SPR_MPC_EID, "EID",
2358                 SPR_NOACCESS, SPR_NOACCESS,
2359                 &spr_read_generic, &spr_write_generic,
2360                 0x00000000);
2361    /* XXX : not implemented */
2362    spr_register(env, SPR_MPC_NRI, "NRI",
2363                 SPR_NOACCESS, SPR_NOACCESS,
2364                 &spr_read_generic, &spr_write_generic,
2365                 0x00000000);
2366    /* XXX : not implemented */
2367    spr_register(env, SPR_MPC_CMPA, "CMPA",
2368                 SPR_NOACCESS, SPR_NOACCESS,
2369                 &spr_read_generic, &spr_write_generic,
2370                 0x00000000);
2371    /* XXX : not implemented */
2372    spr_register(env, SPR_MPC_CMPB, "CMPB",
2373                 SPR_NOACCESS, SPR_NOACCESS,
2374                 &spr_read_generic, &spr_write_generic,
2375                 0x00000000);
2376    /* XXX : not implemented */
2377    spr_register(env, SPR_MPC_CMPC, "CMPC",
2378                 SPR_NOACCESS, SPR_NOACCESS,
2379                 &spr_read_generic, &spr_write_generic,
2380                 0x00000000);
2381    /* XXX : not implemented */
2382    spr_register(env, SPR_MPC_CMPD, "CMPD",
2383                 SPR_NOACCESS, SPR_NOACCESS,
2384                 &spr_read_generic, &spr_write_generic,
2385                 0x00000000);
2386    /* XXX : not implemented */
2387    spr_register(env, SPR_MPC_ECR, "ECR",
2388                 SPR_NOACCESS, SPR_NOACCESS,
2389                 &spr_read_generic, &spr_write_generic,
2390                 0x00000000);
2391    /* XXX : not implemented */
2392    spr_register(env, SPR_MPC_DER, "DER",
2393                 SPR_NOACCESS, SPR_NOACCESS,
2394                 &spr_read_generic, &spr_write_generic,
2395                 0x00000000);
2396    /* XXX : not implemented */
2397    spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2398                 SPR_NOACCESS, SPR_NOACCESS,
2399                 &spr_read_generic, &spr_write_generic,
2400                 0x00000000);
2401    /* XXX : not implemented */
2402    spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2403                 SPR_NOACCESS, SPR_NOACCESS,
2404                 &spr_read_generic, &spr_write_generic,
2405                 0x00000000);
2406    /* XXX : not implemented */
2407    spr_register(env, SPR_MPC_CMPE, "CMPE",
2408                 SPR_NOACCESS, SPR_NOACCESS,
2409                 &spr_read_generic, &spr_write_generic,
2410                 0x00000000);
2411    /* XXX : not implemented */
2412    spr_register(env, SPR_MPC_CMPF, "CMPF",
2413                 SPR_NOACCESS, SPR_NOACCESS,
2414                 &spr_read_generic, &spr_write_generic,
2415                 0x00000000);
2416    /* XXX : not implemented */
2417    spr_register(env, SPR_MPC_CMPG, "CMPG",
2418                 SPR_NOACCESS, SPR_NOACCESS,
2419                 &spr_read_generic, &spr_write_generic,
2420                 0x00000000);
2421    /* XXX : not implemented */
2422    spr_register(env, SPR_MPC_CMPH, "CMPH",
2423                 SPR_NOACCESS, SPR_NOACCESS,
2424                 &spr_read_generic, &spr_write_generic,
2425                 0x00000000);
2426    /* XXX : not implemented */
2427    spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2428                 SPR_NOACCESS, SPR_NOACCESS,
2429                 &spr_read_generic, &spr_write_generic,
2430                 0x00000000);
2431    /* XXX : not implemented */
2432    spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2433                 SPR_NOACCESS, SPR_NOACCESS,
2434                 &spr_read_generic, &spr_write_generic,
2435                 0x00000000);
2436    /* XXX : not implemented */
2437    spr_register(env, SPR_MPC_BAR, "BAR",
2438                 SPR_NOACCESS, SPR_NOACCESS,
2439                 &spr_read_generic, &spr_write_generic,
2440                 0x00000000);
2441    /* XXX : not implemented */
2442    spr_register(env, SPR_MPC_DPDR, "DPDR",
2443                 SPR_NOACCESS, SPR_NOACCESS,
2444                 &spr_read_generic, &spr_write_generic,
2445                 0x00000000);
2446    /* XXX : not implemented */
2447    spr_register(env, SPR_MPC_IMMR, "IMMR",
2448                 SPR_NOACCESS, SPR_NOACCESS,
2449                 &spr_read_generic, &spr_write_generic,
2450                 0x00000000);
2451}
2452
2453static void gen_spr_5xx (CPUPPCState *env)
2454{
2455    /* XXX : not implemented */
2456    spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2457                 SPR_NOACCESS, SPR_NOACCESS,
2458                 &spr_read_generic, &spr_write_generic,
2459                 0x00000000);
2460    /* XXX : not implemented */
2461    spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2462                 SPR_NOACCESS, SPR_NOACCESS,
2463                 &spr_read_generic, &spr_write_generic,
2464                 0x00000000);
2465    /* XXX : not implemented */
2466    spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2467                 SPR_NOACCESS, SPR_NOACCESS,
2468                 &spr_read_generic, &spr_write_generic,
2469                 0x00000000);
2470    /* XXX : not implemented */
2471    spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2472                 SPR_NOACCESS, SPR_NOACCESS,
2473                 &spr_read_generic, &spr_write_generic,
2474                 0x00000000);
2475    /* XXX : not implemented */
2476    spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2477                 SPR_NOACCESS, SPR_NOACCESS,
2478                 &spr_read_generic, &spr_write_generic,
2479                 0x00000000);
2480    /* XXX : not implemented */
2481    spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2482                 SPR_NOACCESS, SPR_NOACCESS,
2483                 &spr_read_generic, &spr_write_generic,
2484                 0x00000000);
2485    /* XXX : not implemented */
2486    spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2487                 SPR_NOACCESS, SPR_NOACCESS,
2488                 &spr_read_generic, &spr_write_generic,
2489                 0x00000000);
2490    /* XXX : not implemented */
2491    spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2492                 SPR_NOACCESS, SPR_NOACCESS,
2493                 &spr_read_generic, &spr_write_generic,
2494                 0x00000000);
2495    /* XXX : not implemented */
2496    spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2497                 SPR_NOACCESS, SPR_NOACCESS,
2498                 &spr_read_generic, &spr_write_generic,
2499                 0x00000000);
2500    /* XXX : not implemented */
2501    spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2502                 SPR_NOACCESS, SPR_NOACCESS,
2503                 &spr_read_generic, &spr_write_generic,
2504                 0x00000000);
2505    /* XXX : not implemented */
2506    spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2507                 SPR_NOACCESS, SPR_NOACCESS,
2508                 &spr_read_generic, &spr_write_generic,
2509                 0x00000000);
2510    /* XXX : not implemented */
2511    spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2512                 SPR_NOACCESS, SPR_NOACCESS,
2513                 &spr_read_generic, &spr_write_generic,
2514                 0x00000000);
2515    /* XXX : not implemented */
2516    spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2517                 SPR_NOACCESS, SPR_NOACCESS,
2518                 &spr_read_generic, &spr_write_generic,
2519                 0x00000000);
2520    /* XXX : not implemented */
2521    spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2522                 SPR_NOACCESS, SPR_NOACCESS,
2523                 &spr_read_generic, &spr_write_generic,
2524                 0x00000000);
2525    /* XXX : not implemented */
2526    spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2527                 SPR_NOACCESS, SPR_NOACCESS,
2528                 &spr_read_generic, &spr_write_generic,
2529                 0x00000000);
2530    /* XXX : not implemented */
2531    spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2532                 SPR_NOACCESS, SPR_NOACCESS,
2533                 &spr_read_generic, &spr_write_generic,
2534                 0x00000000);
2535    /* XXX : not implemented */
2536    spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2537                 SPR_NOACCESS, SPR_NOACCESS,
2538                 &spr_read_generic, &spr_write_generic,
2539                 0x00000000);
2540    /* XXX : not implemented */
2541    spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2542                 SPR_NOACCESS, SPR_NOACCESS,
2543                 &spr_read_generic, &spr_write_generic,
2544                 0x00000000);
2545    /* XXX : not implemented */
2546    spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2547                 SPR_NOACCESS, SPR_NOACCESS,
2548                 &spr_read_generic, &spr_write_generic,
2549                 0x00000000);
2550    /* XXX : not implemented */
2551    spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2552                 SPR_NOACCESS, SPR_NOACCESS,
2553                 &spr_read_generic, &spr_write_generic,
2554                 0x00000000);
2555    /* XXX : not implemented */
2556    spr_register(env, SPR_RCPU_FPECR, "FPECR",
2557                 SPR_NOACCESS, SPR_NOACCESS,
2558                 &spr_read_generic, &spr_write_generic,
2559                 0x00000000);
2560}
2561
2562static void gen_spr_8xx (CPUPPCState *env)
2563{
2564    /* XXX : not implemented */
2565    spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2566                 SPR_NOACCESS, SPR_NOACCESS,
2567                 &spr_read_generic, &spr_write_generic,
2568                 0x00000000);
2569    /* XXX : not implemented */
2570    spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2571                 SPR_NOACCESS, SPR_NOACCESS,
2572                 &spr_read_generic, &spr_write_generic,
2573                 0x00000000);
2574    /* XXX : not implemented */
2575    spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2576                 SPR_NOACCESS, SPR_NOACCESS,
2577                 &spr_read_generic, &spr_write_generic,
2578                 0x00000000);
2579    /* XXX : not implemented */
2580    spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2581                 SPR_NOACCESS, SPR_NOACCESS,
2582                 &spr_read_generic, &spr_write_generic,
2583                 0x00000000);
2584    /* XXX : not implemented */
2585    spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2586                 SPR_NOACCESS, SPR_NOACCESS,
2587                 &spr_read_generic, &spr_write_generic,
2588                 0x00000000);
2589    /* XXX : not implemented */
2590    spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2591                 SPR_NOACCESS, SPR_NOACCESS,
2592                 &spr_read_generic, &spr_write_generic,
2593                 0x00000000);
2594    /* XXX : not implemented */
2595    spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2596                 SPR_NOACCESS, SPR_NOACCESS,
2597                 &spr_read_generic, &spr_write_generic,
2598                 0x00000000);
2599    /* XXX : not implemented */
2600    spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2601                 SPR_NOACCESS, SPR_NOACCESS,
2602                 &spr_read_generic, &spr_write_generic,
2603                 0x00000000);
2604    /* XXX : not implemented */
2605    spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2606                 SPR_NOACCESS, SPR_NOACCESS,
2607                 &spr_read_generic, &spr_write_generic,
2608                 0x00000000);
2609    /* XXX : not implemented */
2610    spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2611                 SPR_NOACCESS, SPR_NOACCESS,
2612                 &spr_read_generic, &spr_write_generic,
2613                 0x00000000);
2614    /* XXX : not implemented */
2615    spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2616                 SPR_NOACCESS, SPR_NOACCESS,
2617                 &spr_read_generic, &spr_write_generic,
2618                 0x00000000);
2619    /* XXX : not implemented */
2620    spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2621                 SPR_NOACCESS, SPR_NOACCESS,
2622                 &spr_read_generic, &spr_write_generic,
2623                 0x00000000);
2624    /* XXX : not implemented */
2625    spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2626                 SPR_NOACCESS, SPR_NOACCESS,
2627                 &spr_read_generic, &spr_write_generic,
2628                 0x00000000);
2629    /* XXX : not implemented */
2630    spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2631                 SPR_NOACCESS, SPR_NOACCESS,
2632                 &spr_read_generic, &spr_write_generic,
2633                 0x00000000);
2634    /* XXX : not implemented */
2635    spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2636                 SPR_NOACCESS, SPR_NOACCESS,
2637                 &spr_read_generic, &spr_write_generic,
2638                 0x00000000);
2639    /* XXX : not implemented */
2640    spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2641                 SPR_NOACCESS, SPR_NOACCESS,
2642                 &spr_read_generic, &spr_write_generic,
2643                 0x00000000);
2644    /* XXX : not implemented */
2645    spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2646                 SPR_NOACCESS, SPR_NOACCESS,
2647                 &spr_read_generic, &spr_write_generic,
2648                 0x00000000);
2649    /* XXX : not implemented */
2650    spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2651                 SPR_NOACCESS, SPR_NOACCESS,
2652                 &spr_read_generic, &spr_write_generic,
2653                 0x00000000);
2654    /* XXX : not implemented */
2655    spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2656                 SPR_NOACCESS, SPR_NOACCESS,
2657                 &spr_read_generic, &spr_write_generic,
2658                 0x00000000);
2659    /* XXX : not implemented */
2660    spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2661                 SPR_NOACCESS, SPR_NOACCESS,
2662                 &spr_read_generic, &spr_write_generic,
2663                 0x00000000);
2664    /* XXX : not implemented */
2665    spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2666                 SPR_NOACCESS, SPR_NOACCESS,
2667                 &spr_read_generic, &spr_write_generic,
2668                 0x00000000);
2669    /* XXX : not implemented */
2670    spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2671                 SPR_NOACCESS, SPR_NOACCESS,
2672                 &spr_read_generic, &spr_write_generic,
2673                 0x00000000);
2674    /* XXX : not implemented */
2675    spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2676                 SPR_NOACCESS, SPR_NOACCESS,
2677                 &spr_read_generic, &spr_write_generic,
2678                 0x00000000);
2679    /* XXX : not implemented */
2680    spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2681                 SPR_NOACCESS, SPR_NOACCESS,
2682                 &spr_read_generic, &spr_write_generic,
2683                 0x00000000);
2684    /* XXX : not implemented */
2685    spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2686                 SPR_NOACCESS, SPR_NOACCESS,
2687                 &spr_read_generic, &spr_write_generic,
2688                 0x00000000);
2689}
2690
2691// XXX: TODO
2692/*
2693 * AMR     => SPR 29 (Power 2.04)
2694 * CTRL    => SPR 136 (Power 2.04)
2695 * CTRL    => SPR 152 (Power 2.04)
2696 * SCOMC   => SPR 276 (64 bits ?)
2697 * SCOMD   => SPR 277 (64 bits ?)
2698 * TBU40   => SPR 286 (Power 2.04 hypv)
2699 * HSPRG0  => SPR 304 (Power 2.04 hypv)
2700 * HSPRG1  => SPR 305 (Power 2.04 hypv)
2701 * HDSISR  => SPR 306 (Power 2.04 hypv)
2702 * HDAR    => SPR 307 (Power 2.04 hypv)
2703 * PURR    => SPR 309 (Power 2.04 hypv)
2704 * HDEC    => SPR 310 (Power 2.04 hypv)
2705 * HIOR    => SPR 311 (hypv)
2706 * RMOR    => SPR 312 (970)
2707 * HRMOR   => SPR 313 (Power 2.04 hypv)
2708 * HSRR0   => SPR 314 (Power 2.04 hypv)
2709 * HSRR1   => SPR 315 (Power 2.04 hypv)
2710 * LPIDR   => SPR 317 (970)
2711 * EPR     => SPR 702 (Power 2.04 emb)
2712 * perf    => 768-783 (Power 2.04)
2713 * perf    => 784-799 (Power 2.04)
2714 * PPR     => SPR 896 (Power 2.04)
2715 * EPLC    => SPR 947 (Power 2.04 emb)
2716 * EPSC    => SPR 948 (Power 2.04 emb)
2717 * DABRX   => 1015    (Power 2.04 hypv)
2718 * FPECR   => SPR 1022 (?)
2719 * ... and more (thermal management, performance counters, ...)
2720 */
2721
2722/*****************************************************************************/
2723/* Exception vectors models                                                  */
2724static void init_excp_4xx_real (CPUPPCState *env)
2725{
2726#if !defined(CONFIG_USER_ONLY)
2727    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2728    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2729    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2730    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2731    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2732    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2733    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2734    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2735    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2736    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2737    env->ivor_mask = 0x0000FFF0UL;
2738    env->ivpr_mask = 0xFFFF0000UL;
2739    /* Hardware reset vector */
2740    env->hreset_vector = 0xFFFFFFFCUL;
2741#endif
2742}
2743
2744static void init_excp_4xx_softmmu (CPUPPCState *env)
2745{
2746#if !defined(CONFIG_USER_ONLY)
2747    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2748    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2749    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2750    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2751    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2752    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2753    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2754    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2755    env->excp_vectors[POWERPC_EXCP_PIT]      = 0x00001000;
2756    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00001010;
2757    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001020;
2758    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001100;
2759    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001200;
2760    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00002000;
2761    env->ivor_mask = 0x0000FFF0UL;
2762    env->ivpr_mask = 0xFFFF0000UL;
2763    /* Hardware reset vector */
2764    env->hreset_vector = 0xFFFFFFFCUL;
2765#endif
2766}
2767
2768static void init_excp_MPC5xx (CPUPPCState *env)
2769{
2770#if !defined(CONFIG_USER_ONLY)
2771    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2772    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2773    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2774    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2775    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2776    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2777    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2778    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2779    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2780    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2781    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2782    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2783    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2784    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2785    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2786    env->ivor_mask = 0x0000FFF0UL;
2787    env->ivpr_mask = 0xFFFF0000UL;
2788    /* Hardware reset vector */
2789    env->hreset_vector = 0x00000100UL;
2790#endif
2791}
2792
2793static void init_excp_MPC8xx (CPUPPCState *env)
2794{
2795#if !defined(CONFIG_USER_ONLY)
2796    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2797    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2798    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2799    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2800    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2801    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2802    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2803    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000900;
2804    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2805    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2806    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2807    env->excp_vectors[POWERPC_EXCP_FPA]      = 0x00000E00;
2808    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001000;
2809    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00001100;
2810    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00001200;
2811    env->excp_vectors[POWERPC_EXCP_ITLBE]    = 0x00001300;
2812    env->excp_vectors[POWERPC_EXCP_DTLBE]    = 0x00001400;
2813    env->excp_vectors[POWERPC_EXCP_DABR]     = 0x00001C00;
2814    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001C00;
2815    env->excp_vectors[POWERPC_EXCP_MEXTBR]   = 0x00001E00;
2816    env->excp_vectors[POWERPC_EXCP_NMEXTBR]  = 0x00001F00;
2817    env->ivor_mask = 0x0000FFF0UL;
2818    env->ivpr_mask = 0xFFFF0000UL;
2819    /* Hardware reset vector */
2820    env->hreset_vector = 0x00000100UL;
2821#endif
2822}
2823
2824static void init_excp_G2 (CPUPPCState *env)
2825{
2826#if !defined(CONFIG_USER_ONLY)
2827    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2828    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2829    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2830    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2831    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2832    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2833    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2834    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2835    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2836    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2837    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2838    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2839    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2840    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2841    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2842    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2843    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2844    /* Hardware reset vector */
2845    env->hreset_vector = 0x00000100UL;
2846#endif
2847}
2848
2849static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2850{
2851#if !defined(CONFIG_USER_ONLY)
2852    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000FFC;
2853    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2854    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2855    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2856    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2857    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2858    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2859    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2860    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2861    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2862    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2863    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2864    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2865    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2866    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2867    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2868    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2869    env->excp_vectors[POWERPC_EXCP_SPEU]     = 0x00000000;
2870    env->excp_vectors[POWERPC_EXCP_EFPDI]    = 0x00000000;
2871    env->excp_vectors[POWERPC_EXCP_EFPRI]    = 0x00000000;
2872    env->ivor_mask = 0x0000FFF7UL;
2873    env->ivpr_mask = ivpr_mask;
2874    /* Hardware reset vector */
2875    env->hreset_vector = 0xFFFFFFFCUL;
2876#endif
2877}
2878
2879static void init_excp_BookE (CPUPPCState *env)
2880{
2881#if !defined(CONFIG_USER_ONLY)
2882    env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2883    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000000;
2884    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000000;
2885    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000000;
2886    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2887    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000000;
2888    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000000;
2889    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000000;
2890    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000000;
2891    env->excp_vectors[POWERPC_EXCP_APU]      = 0x00000000;
2892    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000000;
2893    env->excp_vectors[POWERPC_EXCP_FIT]      = 0x00000000;
2894    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00000000;
2895    env->excp_vectors[POWERPC_EXCP_DTLB]     = 0x00000000;
2896    env->excp_vectors[POWERPC_EXCP_ITLB]     = 0x00000000;
2897    env->excp_vectors[POWERPC_EXCP_DEBUG]    = 0x00000000;
2898    env->ivor_mask = 0x0000FFF0UL;
2899    env->ivpr_mask = 0xFFFF0000UL;
2900    /* Hardware reset vector */
2901    env->hreset_vector = 0xFFFFFFFCUL;
2902#endif
2903}
2904
2905static void init_excp_601 (CPUPPCState *env)
2906{
2907#if !defined(CONFIG_USER_ONLY)
2908    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2909    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2910    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2911    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2912    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2913    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2914    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2915    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2916    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2917    env->excp_vectors[POWERPC_EXCP_IO]       = 0x00000A00;
2918    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2919    env->excp_vectors[POWERPC_EXCP_RUNM]     = 0x00002000;
2920    /* Hardware reset vector */
2921    env->hreset_vector = 0x00000100UL;
2922#endif
2923}
2924
2925static void init_excp_602 (CPUPPCState *env)
2926{
2927#if !defined(CONFIG_USER_ONLY)
2928    /* XXX: exception prefix has a special behavior on 602 */
2929    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2930    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2931    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2932    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2933    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2935    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2936    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2937    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2938    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2939    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2940    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2941    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2942    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2943    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2944    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2945    env->excp_vectors[POWERPC_EXCP_WDT]      = 0x00001500;
2946    env->excp_vectors[POWERPC_EXCP_EMUL]     = 0x00001600;
2947    /* Hardware reset vector */
2948    env->hreset_vector = 0x00000100UL;
2949#endif
2950}
2951
2952static void init_excp_603 (CPUPPCState *env)
2953{
2954#if !defined(CONFIG_USER_ONLY)
2955    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2956    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2957    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2958    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2959    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2960    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2961    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2962    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2963    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2964    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2965    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2966    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
2967    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
2968    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
2969    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2970    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2971    /* Hardware reset vector */
2972    env->hreset_vector = 0x00000100UL;
2973#endif
2974}
2975
2976static void init_excp_604 (CPUPPCState *env)
2977{
2978#if !defined(CONFIG_USER_ONLY)
2979    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
2980    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
2981    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
2982    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
2983    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2984    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
2985    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
2986    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
2987    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
2988    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
2989    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
2990    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
2991    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
2992    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
2993    /* Hardware reset vector */
2994    env->hreset_vector = 0x00000100UL;
2995#endif
2996}
2997
2998static void init_excp_7x0 (CPUPPCState *env)
2999{
3000#if !defined(CONFIG_USER_ONLY)
3001    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3002    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3003    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3004    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3005    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3006    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3007    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3008    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3009    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3010    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3011    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3012    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3013    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3014    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3015    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3016    /* Hardware reset vector */
3017    env->hreset_vector = 0x00000100UL;
3018#endif
3019}
3020
3021static void init_excp_750cl (CPUPPCState *env)
3022{
3023#if !defined(CONFIG_USER_ONLY)
3024    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3025    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3026    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3027    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3028    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3029    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3030    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3031    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3032    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3033    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3034    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3035    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3036    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3037    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3038    /* Hardware reset vector */
3039    env->hreset_vector = 0x00000100UL;
3040#endif
3041}
3042
3043static void init_excp_750cx (CPUPPCState *env)
3044{
3045#if !defined(CONFIG_USER_ONLY)
3046    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3047    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3048    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3049    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3050    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3051    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3052    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3053    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3054    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3055    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3056    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3057    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3058    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3059    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3060    /* Hardware reset vector */
3061    env->hreset_vector = 0x00000100UL;
3062#endif
3063}
3064
3065/* XXX: Check if this is correct */
3066static void init_excp_7x5 (CPUPPCState *env)
3067{
3068#if !defined(CONFIG_USER_ONLY)
3069    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3070    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3071    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3072    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3073    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3074    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3075    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3076    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3077    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3078    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3079    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3080    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3081    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3082    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3083    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3084    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3085    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3086    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3087    /* Hardware reset vector */
3088    env->hreset_vector = 0x00000100UL;
3089#endif
3090}
3091
3092static void init_excp_7400 (CPUPPCState *env)
3093{
3094#if !defined(CONFIG_USER_ONLY)
3095    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3096    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3097    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3098    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3099    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3100    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3101    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3102    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3103    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3104    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3105    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3106    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3107    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3108    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3109    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3110    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3111    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001700;
3112    /* Hardware reset vector */
3113    env->hreset_vector = 0x00000100UL;
3114#endif
3115}
3116
3117static void init_excp_7450 (CPUPPCState *env)
3118{
3119#if !defined(CONFIG_USER_ONLY)
3120    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3121    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3122    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3123    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3124    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3125    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3126    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3127    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3128    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3129    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3130    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3131    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3132    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3133    env->excp_vectors[POWERPC_EXCP_IFTLB]    = 0x00001000;
3134    env->excp_vectors[POWERPC_EXCP_DLTLB]    = 0x00001100;
3135    env->excp_vectors[POWERPC_EXCP_DSTLB]    = 0x00001200;
3136    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3137    env->excp_vectors[POWERPC_EXCP_SMI]      = 0x00001400;
3138    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001600;
3139    /* Hardware reset vector */
3140    env->hreset_vector = 0x00000100UL;
3141#endif
3142}
3143
3144#if defined (TARGET_PPC64)
3145static void init_excp_970 (CPUPPCState *env)
3146{
3147#if !defined(CONFIG_USER_ONLY)
3148    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3149    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3150    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3151    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3152    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3153    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3154    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3155    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3156    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3157    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3158    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3159    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3160    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3161    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3162    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3163    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3164    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3165    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3166    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3167    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3168    /* Hardware reset vector */
3169    env->hreset_vector = 0x0000000000000100ULL;
3170#endif
3171}
3172
3173static void init_excp_POWER7 (CPUPPCState *env)
3174{
3175#if !defined(CONFIG_USER_ONLY)
3176    env->excp_vectors[POWERPC_EXCP_RESET]    = 0x00000100;
3177    env->excp_vectors[POWERPC_EXCP_MCHECK]   = 0x00000200;
3178    env->excp_vectors[POWERPC_EXCP_DSI]      = 0x00000300;
3179    env->excp_vectors[POWERPC_EXCP_DSEG]     = 0x00000380;
3180    env->excp_vectors[POWERPC_EXCP_ISI]      = 0x00000400;
3181    env->excp_vectors[POWERPC_EXCP_ISEG]     = 0x00000480;
3182    env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3183    env->excp_vectors[POWERPC_EXCP_ALIGN]    = 0x00000600;
3184    env->excp_vectors[POWERPC_EXCP_PROGRAM]  = 0x00000700;
3185    env->excp_vectors[POWERPC_EXCP_FPU]      = 0x00000800;
3186    env->excp_vectors[POWERPC_EXCP_DECR]     = 0x00000900;
3187    env->excp_vectors[POWERPC_EXCP_HDECR]    = 0x00000980;
3188    env->excp_vectors[POWERPC_EXCP_SYSCALL]  = 0x00000C00;
3189    env->excp_vectors[POWERPC_EXCP_TRACE]    = 0x00000D00;
3190    env->excp_vectors[POWERPC_EXCP_PERFM]    = 0x00000F00;
3191    env->excp_vectors[POWERPC_EXCP_VPU]      = 0x00000F20;
3192    env->excp_vectors[POWERPC_EXCP_VSXU]     = 0x00000F40;
3193    env->excp_vectors[POWERPC_EXCP_FU]       = 0x00000F60;
3194    env->excp_vectors[POWERPC_EXCP_IABR]     = 0x00001300;
3195    env->excp_vectors[POWERPC_EXCP_MAINT]    = 0x00001600;
3196    env->excp_vectors[POWERPC_EXCP_VPUA]     = 0x00001700;
3197    env->excp_vectors[POWERPC_EXCP_THERM]    = 0x00001800;
3198    /* Hardware reset vector */
3199    env->hreset_vector = 0x0000000000000100ULL;
3200#endif
3201}
3202#endif
3203
3204/*****************************************************************************/
3205/* Power management enable checks                                            */
3206static int check_pow_none (CPUPPCState *env)
3207{
3208    return 0;
3209}
3210
3211static int check_pow_nocheck (CPUPPCState *env)
3212{
3213    return 1;
3214}
3215
3216static int check_pow_hid0 (CPUPPCState *env)
3217{
3218    if (env->spr[SPR_HID0] & 0x00E00000)
3219        return 1;
3220
3221    return 0;
3222}
3223
3224static int check_pow_hid0_74xx (CPUPPCState *env)
3225{
3226    if (env->spr[SPR_HID0] & 0x00600000)
3227        return 1;
3228
3229    return 0;
3230}
3231
3232static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3233{
3234    return true;
3235}
3236
3237#ifdef TARGET_PPC64
3238static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3239{
3240    return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3241}
3242#endif
3243
3244/*****************************************************************************/
3245/* PowerPC implementations definitions                                       */
3246
3247#define POWERPC_FAMILY(_name)                                               \
3248    static void                                                             \
3249    glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3250                                                                            \
3251    static const TypeInfo                                                   \
3252    glue(glue(ppc_, _name), _cpu_family_type_info) = {                      \
3253        .name = stringify(_name) "-family-" TYPE_POWERPC_CPU,               \
3254        .parent = TYPE_POWERPC_CPU,                                         \
3255        .abstract = true,                                                   \
3256        .class_init = glue(glue(ppc_, _name), _cpu_family_class_init),      \
3257    };                                                                      \
3258                                                                            \
3259    static void glue(glue(ppc_, _name), _cpu_family_register_types)(void)   \
3260    {                                                                       \
3261        type_register_static(                                               \
3262            &glue(glue(ppc_, _name), _cpu_family_type_info));               \
3263    }                                                                       \
3264                                                                            \
3265    type_init(glue(glue(ppc_, _name), _cpu_family_register_types))          \
3266                                                                            \
3267    static void glue(glue(ppc_, _name), _cpu_family_class_init)
3268
3269static void init_proc_401 (CPUPPCState *env)
3270{
3271    gen_spr_40x(env);
3272    gen_spr_401_403(env);
3273    gen_spr_401(env);
3274    init_excp_4xx_real(env);
3275    env->dcache_line_size = 32;
3276    env->icache_line_size = 32;
3277    /* Allocate hardware IRQ controller */
3278    ppc40x_irq_init(env);
3279
3280    SET_FIT_PERIOD(12, 16, 20, 24);
3281    SET_WDT_PERIOD(16, 20, 24, 28);
3282}
3283
3284POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3285{
3286    DeviceClass *dc = DEVICE_CLASS(oc);
3287    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3288
3289    dc->desc = "PowerPC 401";
3290    pcc->init_proc = init_proc_401;
3291    pcc->check_pow = check_pow_nocheck;
3292    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3293                       PPC_WRTEE | PPC_DCR |
3294                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3295                       PPC_CACHE_DCBZ |
3296                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3297                       PPC_4xx_COMMON | PPC_40x_EXCP;
3298    pcc->msr_mask = (1ull << MSR_KEY) |
3299                    (1ull << MSR_POW) |
3300                    (1ull << MSR_CE) |
3301                    (1ull << MSR_ILE) |
3302                    (1ull << MSR_EE) |
3303                    (1ull << MSR_PR) |
3304                    (1ull << MSR_ME) |
3305                    (1ull << MSR_DE) |
3306                    (1ull << MSR_LE);
3307    pcc->mmu_model = POWERPC_MMU_REAL;
3308    pcc->excp_model = POWERPC_EXCP_40x;
3309    pcc->bus_model = PPC_FLAGS_INPUT_401;
3310    pcc->bfd_mach = bfd_mach_ppc_403;
3311    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3312                 POWERPC_FLAG_BUS_CLK;
3313}
3314
3315static void init_proc_401x2 (CPUPPCState *env)
3316{
3317    gen_spr_40x(env);
3318    gen_spr_401_403(env);
3319    gen_spr_401x2(env);
3320    gen_spr_compress(env);
3321    /* Memory management */
3322#if !defined(CONFIG_USER_ONLY)
3323    env->nb_tlb = 64;
3324    env->nb_ways = 1;
3325    env->id_tlbs = 0;
3326    env->tlb_type = TLB_EMB;
3327#endif
3328    init_excp_4xx_softmmu(env);
3329    env->dcache_line_size = 32;
3330    env->icache_line_size = 32;
3331    /* Allocate hardware IRQ controller */
3332    ppc40x_irq_init(env);
3333
3334    SET_FIT_PERIOD(12, 16, 20, 24);
3335    SET_WDT_PERIOD(16, 20, 24, 28);
3336}
3337
3338POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3339{
3340    DeviceClass *dc = DEVICE_CLASS(oc);
3341    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3342
3343    dc->desc = "PowerPC 401x2";
3344    pcc->init_proc = init_proc_401x2;
3345    pcc->check_pow = check_pow_nocheck;
3346    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3347                       PPC_DCR | PPC_WRTEE |
3348                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3349                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3350                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3351                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3352                       PPC_4xx_COMMON | PPC_40x_EXCP;
3353    pcc->msr_mask = (1ull << 20) |
3354                    (1ull << MSR_KEY) |
3355                    (1ull << MSR_POW) |
3356                    (1ull << MSR_CE) |
3357                    (1ull << MSR_ILE) |
3358                    (1ull << MSR_EE) |
3359                    (1ull << MSR_PR) |
3360                    (1ull << MSR_ME) |
3361                    (1ull << MSR_DE) |
3362                    (1ull << MSR_IR) |
3363                    (1ull << MSR_DR) |
3364                    (1ull << MSR_LE);
3365    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3366    pcc->excp_model = POWERPC_EXCP_40x;
3367    pcc->bus_model = PPC_FLAGS_INPUT_401;
3368    pcc->bfd_mach = bfd_mach_ppc_403;
3369    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3370                 POWERPC_FLAG_BUS_CLK;
3371}
3372
3373static void init_proc_401x3 (CPUPPCState *env)
3374{
3375    gen_spr_40x(env);
3376    gen_spr_401_403(env);
3377    gen_spr_401(env);
3378    gen_spr_401x2(env);
3379    gen_spr_compress(env);
3380    init_excp_4xx_softmmu(env);
3381    env->dcache_line_size = 32;
3382    env->icache_line_size = 32;
3383    /* Allocate hardware IRQ controller */
3384    ppc40x_irq_init(env);
3385
3386    SET_FIT_PERIOD(12, 16, 20, 24);
3387    SET_WDT_PERIOD(16, 20, 24, 28);
3388}
3389
3390POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3391{
3392    DeviceClass *dc = DEVICE_CLASS(oc);
3393    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3394
3395    dc->desc = "PowerPC 401x3";
3396    pcc->init_proc = init_proc_401x3;
3397    pcc->check_pow = check_pow_nocheck;
3398    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3399                       PPC_DCR | PPC_WRTEE |
3400                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3401                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3402                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3403                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3404                       PPC_4xx_COMMON | PPC_40x_EXCP;
3405    pcc->msr_mask = (1ull << 20) |
3406                    (1ull << MSR_KEY) |
3407                    (1ull << MSR_POW) |
3408                    (1ull << MSR_CE) |
3409                    (1ull << MSR_ILE) |
3410                    (1ull << MSR_EE) |
3411                    (1ull << MSR_PR) |
3412                    (1ull << MSR_ME) |
3413                    (1ull << MSR_DWE) |
3414                    (1ull << MSR_DE) |
3415                    (1ull << MSR_IR) |
3416                    (1ull << MSR_DR) |
3417                    (1ull << MSR_LE);
3418    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3419    pcc->excp_model = POWERPC_EXCP_40x;
3420    pcc->bus_model = PPC_FLAGS_INPUT_401;
3421    pcc->bfd_mach = bfd_mach_ppc_403;
3422    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3423                 POWERPC_FLAG_BUS_CLK;
3424}
3425
3426static void init_proc_IOP480 (CPUPPCState *env)
3427{
3428    gen_spr_40x(env);
3429    gen_spr_401_403(env);
3430    gen_spr_401x2(env);
3431    gen_spr_compress(env);
3432    /* Memory management */
3433#if !defined(CONFIG_USER_ONLY)
3434    env->nb_tlb = 64;
3435    env->nb_ways = 1;
3436    env->id_tlbs = 0;
3437    env->tlb_type = TLB_EMB;
3438#endif
3439    init_excp_4xx_softmmu(env);
3440    env->dcache_line_size = 32;
3441    env->icache_line_size = 32;
3442    /* Allocate hardware IRQ controller */
3443    ppc40x_irq_init(env);
3444
3445    SET_FIT_PERIOD(8, 12, 16, 20);
3446    SET_WDT_PERIOD(16, 20, 24, 28);
3447}
3448
3449POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3450{
3451    DeviceClass *dc = DEVICE_CLASS(oc);
3452    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3453
3454    dc->desc = "IOP480";
3455    pcc->init_proc = init_proc_IOP480;
3456    pcc->check_pow = check_pow_nocheck;
3457    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3458                       PPC_DCR | PPC_WRTEE |
3459                       PPC_CACHE | PPC_CACHE_ICBI |  PPC_40x_ICBT |
3460                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3461                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3462                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3463                       PPC_4xx_COMMON | PPC_40x_EXCP;
3464    pcc->msr_mask = (1ull << 20) |
3465                    (1ull << MSR_KEY) |
3466                    (1ull << MSR_POW) |
3467                    (1ull << MSR_CE) |
3468                    (1ull << MSR_ILE) |
3469                    (1ull << MSR_EE) |
3470                    (1ull << MSR_PR) |
3471                    (1ull << MSR_ME) |
3472                    (1ull << MSR_DE) |
3473                    (1ull << MSR_IR) |
3474                    (1ull << MSR_DR) |
3475                    (1ull << MSR_LE);
3476    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3477    pcc->excp_model = POWERPC_EXCP_40x;
3478    pcc->bus_model = PPC_FLAGS_INPUT_401;
3479    pcc->bfd_mach = bfd_mach_ppc_403;
3480    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3481                 POWERPC_FLAG_BUS_CLK;
3482}
3483
3484static void init_proc_403 (CPUPPCState *env)
3485{
3486    gen_spr_40x(env);
3487    gen_spr_401_403(env);
3488    gen_spr_403(env);
3489    gen_spr_403_real(env);
3490    init_excp_4xx_real(env);
3491    env->dcache_line_size = 32;
3492    env->icache_line_size = 32;
3493    /* Allocate hardware IRQ controller */
3494    ppc40x_irq_init(env);
3495
3496    SET_FIT_PERIOD(8, 12, 16, 20);
3497    SET_WDT_PERIOD(16, 20, 24, 28);
3498}
3499
3500POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3501{
3502    DeviceClass *dc = DEVICE_CLASS(oc);
3503    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3504
3505    dc->desc = "PowerPC 403";
3506    pcc->init_proc = init_proc_403;
3507    pcc->check_pow = check_pow_nocheck;
3508    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3509                       PPC_DCR | PPC_WRTEE |
3510                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3511                       PPC_CACHE_DCBZ |
3512                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3513                       PPC_4xx_COMMON | PPC_40x_EXCP;
3514    pcc->msr_mask = (1ull << MSR_POW) |
3515                    (1ull << MSR_CE) |
3516                    (1ull << MSR_ILE) |
3517                    (1ull << MSR_EE) |
3518                    (1ull << MSR_PR) |
3519                    (1ull << MSR_ME) |
3520                    (1ull << MSR_PE) |
3521                    (1ull << MSR_PX) |
3522                    (1ull << MSR_LE);
3523    pcc->mmu_model = POWERPC_MMU_REAL;
3524    pcc->excp_model = POWERPC_EXCP_40x;
3525    pcc->bus_model = PPC_FLAGS_INPUT_401;
3526    pcc->bfd_mach = bfd_mach_ppc_403;
3527    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3528                 POWERPC_FLAG_BUS_CLK;
3529}
3530
3531static void init_proc_403GCX (CPUPPCState *env)
3532{
3533    gen_spr_40x(env);
3534    gen_spr_401_403(env);
3535    gen_spr_403(env);
3536    gen_spr_403_real(env);
3537    gen_spr_403_mmu(env);
3538    /* Bus access control */
3539    /* not emulated, as QEMU never does speculative access */
3540    spr_register(env, SPR_40x_SGR, "SGR",
3541                 SPR_NOACCESS, SPR_NOACCESS,
3542                 &spr_read_generic, &spr_write_generic,
3543                 0xFFFFFFFF);
3544    /* not emulated, as QEMU do not emulate caches */
3545    spr_register(env, SPR_40x_DCWR, "DCWR",
3546                 SPR_NOACCESS, SPR_NOACCESS,
3547                 &spr_read_generic, &spr_write_generic,
3548                 0x00000000);
3549    /* Memory management */
3550#if !defined(CONFIG_USER_ONLY)
3551    env->nb_tlb = 64;
3552    env->nb_ways = 1;
3553    env->id_tlbs = 0;
3554    env->tlb_type = TLB_EMB;
3555#endif
3556    init_excp_4xx_softmmu(env);
3557    env->dcache_line_size = 32;
3558    env->icache_line_size = 32;
3559    /* Allocate hardware IRQ controller */
3560    ppc40x_irq_init(env);
3561
3562    SET_FIT_PERIOD(8, 12, 16, 20);
3563    SET_WDT_PERIOD(16, 20, 24, 28);
3564}
3565
3566POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3567{
3568    DeviceClass *dc = DEVICE_CLASS(oc);
3569    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3570
3571    dc->desc = "PowerPC 403 GCX";
3572    pcc->init_proc = init_proc_403GCX;
3573    pcc->check_pow = check_pow_nocheck;
3574    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3575                       PPC_DCR | PPC_WRTEE |
3576                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3577                       PPC_CACHE_DCBZ |
3578                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3579                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3580                       PPC_4xx_COMMON | PPC_40x_EXCP;
3581    pcc->msr_mask = (1ull << MSR_POW) |
3582                    (1ull << MSR_CE) |
3583                    (1ull << MSR_ILE) |
3584                    (1ull << MSR_EE) |
3585                    (1ull << MSR_PR) |
3586                    (1ull << MSR_ME) |
3587                    (1ull << MSR_PE) |
3588                    (1ull << MSR_PX) |
3589                    (1ull << MSR_LE);
3590    pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3591    pcc->excp_model = POWERPC_EXCP_40x;
3592    pcc->bus_model = PPC_FLAGS_INPUT_401;
3593    pcc->bfd_mach = bfd_mach_ppc_403;
3594    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3595                 POWERPC_FLAG_BUS_CLK;
3596}
3597
3598static void init_proc_405 (CPUPPCState *env)
3599{
3600    /* Time base */
3601    gen_tbl(env);
3602    gen_spr_40x(env);
3603    gen_spr_405(env);
3604    /* Bus access control */
3605    /* not emulated, as QEMU never does speculative access */
3606    spr_register(env, SPR_40x_SGR, "SGR",
3607                 SPR_NOACCESS, SPR_NOACCESS,
3608                 &spr_read_generic, &spr_write_generic,
3609                 0xFFFFFFFF);
3610    /* not emulated, as QEMU do not emulate caches */
3611    spr_register(env, SPR_40x_DCWR, "DCWR",
3612                 SPR_NOACCESS, SPR_NOACCESS,
3613                 &spr_read_generic, &spr_write_generic,
3614                 0x00000000);
3615    /* Memory management */
3616#if !defined(CONFIG_USER_ONLY)
3617    env->nb_tlb = 64;
3618    env->nb_ways = 1;
3619    env->id_tlbs = 0;
3620    env->tlb_type = TLB_EMB;
3621#endif
3622    init_excp_4xx_softmmu(env);
3623    env->dcache_line_size = 32;
3624    env->icache_line_size = 32;
3625    /* Allocate hardware IRQ controller */
3626    ppc40x_irq_init(env);
3627
3628    SET_FIT_PERIOD(8, 12, 16, 20);
3629    SET_WDT_PERIOD(16, 20, 24, 28);
3630}
3631
3632POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3633{
3634    DeviceClass *dc = DEVICE_CLASS(oc);
3635    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3636
3637    dc->desc = "PowerPC 405";
3638    pcc->init_proc = init_proc_405;
3639    pcc->check_pow = check_pow_nocheck;
3640    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3641                       PPC_DCR | PPC_WRTEE |
3642                       PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3643                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3644                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
3645                       PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3646                       PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3647    pcc->msr_mask = (1ull << MSR_POW) |
3648                    (1ull << MSR_CE) |
3649                    (1ull << MSR_EE) |
3650                    (1ull << MSR_PR) |
3651                    (1ull << MSR_FP) |
3652                    (1ull << MSR_DWE) |
3653                    (1ull << MSR_DE) |
3654                    (1ull << MSR_IR) |
3655                    (1ull << MSR_DR);
3656    pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3657    pcc->excp_model = POWERPC_EXCP_40x;
3658    pcc->bus_model = PPC_FLAGS_INPUT_405;
3659    pcc->bfd_mach = bfd_mach_ppc_403;
3660    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3661                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3662}
3663
3664static void init_proc_440EP (CPUPPCState *env)
3665{
3666    /* Time base */
3667    gen_tbl(env);
3668    gen_spr_BookE(env, 0x000000000000FFFFULL);
3669    gen_spr_440(env);
3670    gen_spr_usprgh(env);
3671    /* Processor identification */
3672    spr_register(env, SPR_BOOKE_PIR, "PIR",
3673                 SPR_NOACCESS, SPR_NOACCESS,
3674                 &spr_read_generic, &spr_write_pir,
3675                 0x00000000);
3676    /* XXX : not implemented */
3677    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3678                 SPR_NOACCESS, SPR_NOACCESS,
3679                 &spr_read_generic, &spr_write_generic,
3680                 0x00000000);
3681    /* XXX : not implemented */
3682    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3683                 SPR_NOACCESS, SPR_NOACCESS,
3684                 &spr_read_generic, &spr_write_generic,
3685                 0x00000000);
3686    /* XXX : not implemented */
3687    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3688                 SPR_NOACCESS, SPR_NOACCESS,
3689                 &spr_read_generic, &spr_write_generic,
3690                 0x00000000);
3691    /* XXX : not implemented */
3692    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3693                 SPR_NOACCESS, SPR_NOACCESS,
3694                 &spr_read_generic, &spr_write_generic,
3695                 0x00000000);
3696    /* XXX : not implemented */
3697    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3698                 SPR_NOACCESS, SPR_NOACCESS,
3699                 &spr_read_generic, &spr_write_generic,
3700                 0x00000000);
3701    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3702                 SPR_NOACCESS, SPR_NOACCESS,
3703                 &spr_read_generic, &spr_write_generic,
3704                 0x00000000);
3705    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3706                 SPR_NOACCESS, SPR_NOACCESS,
3707                 &spr_read_generic, &spr_write_generic,
3708                 0x00000000);
3709    /* XXX : not implemented */
3710    spr_register(env, SPR_440_CCR1, "CCR1",
3711                 SPR_NOACCESS, SPR_NOACCESS,
3712                 &spr_read_generic, &spr_write_generic,
3713                 0x00000000);
3714    /* Memory management */
3715#if !defined(CONFIG_USER_ONLY)
3716    env->nb_tlb = 64;
3717    env->nb_ways = 1;
3718    env->id_tlbs = 0;
3719    env->tlb_type = TLB_EMB;
3720#endif
3721    init_excp_BookE(env);
3722    env->dcache_line_size = 32;
3723    env->icache_line_size = 32;
3724    ppc40x_irq_init(env);
3725
3726    SET_FIT_PERIOD(12, 16, 20, 24);
3727    SET_WDT_PERIOD(20, 24, 28, 32);
3728}
3729
3730POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3731{
3732    DeviceClass *dc = DEVICE_CLASS(oc);
3733    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3734
3735    dc->desc = "PowerPC 440 EP";
3736    pcc->init_proc = init_proc_440EP;
3737    pcc->check_pow = check_pow_nocheck;
3738    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3739                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3740                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3741                       PPC_FLOAT_STFIWX |
3742                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3743                       PPC_CACHE | PPC_CACHE_ICBI |
3744                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3745                       PPC_MEM_TLBSYNC | PPC_MFTB |
3746                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3747                       PPC_440_SPEC;
3748    pcc->msr_mask = (1ull << MSR_POW) |
3749                    (1ull << MSR_CE) |
3750                    (1ull << MSR_EE) |
3751                    (1ull << MSR_PR) |
3752                    (1ull << MSR_FP) |
3753                    (1ull << MSR_ME) |
3754                    (1ull << MSR_FE0) |
3755                    (1ull << MSR_DWE) |
3756                    (1ull << MSR_DE) |
3757                    (1ull << MSR_FE1) |
3758                    (1ull << MSR_IR) |
3759                    (1ull << MSR_DR);
3760    pcc->mmu_model = POWERPC_MMU_BOOKE;
3761    pcc->excp_model = POWERPC_EXCP_BOOKE;
3762    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3763    pcc->bfd_mach = bfd_mach_ppc_403;
3764    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3765                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3766}
3767
3768static void init_proc_440GP (CPUPPCState *env)
3769{
3770    /* Time base */
3771    gen_tbl(env);
3772    gen_spr_BookE(env, 0x000000000000FFFFULL);
3773    gen_spr_440(env);
3774    gen_spr_usprgh(env);
3775    /* Processor identification */
3776    spr_register(env, SPR_BOOKE_PIR, "PIR",
3777                 SPR_NOACCESS, SPR_NOACCESS,
3778                 &spr_read_generic, &spr_write_pir,
3779                 0x00000000);
3780    /* XXX : not implemented */
3781    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3782                 SPR_NOACCESS, SPR_NOACCESS,
3783                 &spr_read_generic, &spr_write_generic,
3784                 0x00000000);
3785    /* XXX : not implemented */
3786    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3787                 SPR_NOACCESS, SPR_NOACCESS,
3788                 &spr_read_generic, &spr_write_generic,
3789                 0x00000000);
3790    /* XXX : not implemented */
3791    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3792                 SPR_NOACCESS, SPR_NOACCESS,
3793                 &spr_read_generic, &spr_write_generic,
3794                 0x00000000);
3795    /* XXX : not implemented */
3796    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3797                 SPR_NOACCESS, SPR_NOACCESS,
3798                 &spr_read_generic, &spr_write_generic,
3799                 0x00000000);
3800    /* Memory management */
3801#if !defined(CONFIG_USER_ONLY)
3802    env->nb_tlb = 64;
3803    env->nb_ways = 1;
3804    env->id_tlbs = 0;
3805    env->tlb_type = TLB_EMB;
3806#endif
3807    init_excp_BookE(env);
3808    env->dcache_line_size = 32;
3809    env->icache_line_size = 32;
3810    /* XXX: TODO: allocate internal IRQ controller */
3811
3812    SET_FIT_PERIOD(12, 16, 20, 24);
3813    SET_WDT_PERIOD(20, 24, 28, 32);
3814}
3815
3816POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3817{
3818    DeviceClass *dc = DEVICE_CLASS(oc);
3819    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3820
3821    dc->desc = "PowerPC 440 GP";
3822    pcc->init_proc = init_proc_440GP;
3823    pcc->check_pow = check_pow_nocheck;
3824    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3825                       PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3826                       PPC_CACHE | PPC_CACHE_ICBI |
3827                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3828                       PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3829                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3830                       PPC_440_SPEC;
3831    pcc->msr_mask = (1ull << MSR_POW) |
3832                    (1ull << MSR_CE) |
3833                    (1ull << MSR_EE) |
3834                    (1ull << MSR_PR) |
3835                    (1ull << MSR_FP) |
3836                    (1ull << MSR_ME) |
3837                    (1ull << MSR_FE0) |
3838                    (1ull << MSR_DWE) |
3839                    (1ull << MSR_DE) |
3840                    (1ull << MSR_FE1) |
3841                    (1ull << MSR_IR) |
3842                    (1ull << MSR_DR);
3843    pcc->mmu_model = POWERPC_MMU_BOOKE;
3844    pcc->excp_model = POWERPC_EXCP_BOOKE;
3845    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3846    pcc->bfd_mach = bfd_mach_ppc_403;
3847    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3848                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3849}
3850
3851static void init_proc_440x4 (CPUPPCState *env)
3852{
3853    /* Time base */
3854    gen_tbl(env);
3855    gen_spr_BookE(env, 0x000000000000FFFFULL);
3856    gen_spr_440(env);
3857    gen_spr_usprgh(env);
3858    /* Processor identification */
3859    spr_register(env, SPR_BOOKE_PIR, "PIR",
3860                 SPR_NOACCESS, SPR_NOACCESS,
3861                 &spr_read_generic, &spr_write_pir,
3862                 0x00000000);
3863    /* XXX : not implemented */
3864    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3865                 SPR_NOACCESS, SPR_NOACCESS,
3866                 &spr_read_generic, &spr_write_generic,
3867                 0x00000000);
3868    /* XXX : not implemented */
3869    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3870                 SPR_NOACCESS, SPR_NOACCESS,
3871                 &spr_read_generic, &spr_write_generic,
3872                 0x00000000);
3873    /* XXX : not implemented */
3874    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3875                 SPR_NOACCESS, SPR_NOACCESS,
3876                 &spr_read_generic, &spr_write_generic,
3877                 0x00000000);
3878    /* XXX : not implemented */
3879    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3880                 SPR_NOACCESS, SPR_NOACCESS,
3881                 &spr_read_generic, &spr_write_generic,
3882                 0x00000000);
3883    /* Memory management */
3884#if !defined(CONFIG_USER_ONLY)
3885    env->nb_tlb = 64;
3886    env->nb_ways = 1;
3887    env->id_tlbs = 0;
3888    env->tlb_type = TLB_EMB;
3889#endif
3890    init_excp_BookE(env);
3891    env->dcache_line_size = 32;
3892    env->icache_line_size = 32;
3893    /* XXX: TODO: allocate internal IRQ controller */
3894
3895    SET_FIT_PERIOD(12, 16, 20, 24);
3896    SET_WDT_PERIOD(20, 24, 28, 32);
3897}
3898
3899POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3900{
3901    DeviceClass *dc = DEVICE_CLASS(oc);
3902    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3903
3904    dc->desc = "PowerPC 440x4";
3905    pcc->init_proc = init_proc_440x4;
3906    pcc->check_pow = check_pow_nocheck;
3907    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3908                       PPC_DCR | PPC_WRTEE |
3909                       PPC_CACHE | PPC_CACHE_ICBI |
3910                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3911                       PPC_MEM_TLBSYNC | PPC_MFTB |
3912                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3913                       PPC_440_SPEC;
3914    pcc->msr_mask = (1ull << MSR_POW) |
3915                    (1ull << MSR_CE) |
3916                    (1ull << MSR_EE) |
3917                    (1ull << MSR_PR) |
3918                    (1ull << MSR_FP) |
3919                    (1ull << MSR_ME) |
3920                    (1ull << MSR_FE0) |
3921                    (1ull << MSR_DWE) |
3922                    (1ull << MSR_DE) |
3923                    (1ull << MSR_FE1) |
3924                    (1ull << MSR_IR) |
3925                    (1ull << MSR_DR);
3926    pcc->mmu_model = POWERPC_MMU_BOOKE;
3927    pcc->excp_model = POWERPC_EXCP_BOOKE;
3928    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3929    pcc->bfd_mach = bfd_mach_ppc_403;
3930    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3931                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3932}
3933
3934static void init_proc_440x5 (CPUPPCState *env)
3935{
3936    /* Time base */
3937    gen_tbl(env);
3938    gen_spr_BookE(env, 0x000000000000FFFFULL);
3939    gen_spr_440(env);
3940    gen_spr_usprgh(env);
3941    /* Processor identification */
3942    spr_register(env, SPR_BOOKE_PIR, "PIR",
3943                 SPR_NOACCESS, SPR_NOACCESS,
3944                 &spr_read_generic, &spr_write_pir,
3945                 0x00000000);
3946    /* XXX : not implemented */
3947    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3948                 SPR_NOACCESS, SPR_NOACCESS,
3949                 &spr_read_generic, &spr_write_generic,
3950                 0x00000000);
3951    /* XXX : not implemented */
3952    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3953                 SPR_NOACCESS, SPR_NOACCESS,
3954                 &spr_read_generic, &spr_write_generic,
3955                 0x00000000);
3956    /* XXX : not implemented */
3957    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3958                 SPR_NOACCESS, SPR_NOACCESS,
3959                 &spr_read_generic, &spr_write_generic,
3960                 0x00000000);
3961    /* XXX : not implemented */
3962    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3963                 SPR_NOACCESS, SPR_NOACCESS,
3964                 &spr_read_generic, &spr_write_generic,
3965                 0x00000000);
3966    /* XXX : not implemented */
3967    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3968                 SPR_NOACCESS, SPR_NOACCESS,
3969                 &spr_read_generic, &spr_write_generic,
3970                 0x00000000);
3971    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3972                 SPR_NOACCESS, SPR_NOACCESS,
3973                 &spr_read_generic, &spr_write_generic,
3974                 0x00000000);
3975    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3976                 SPR_NOACCESS, SPR_NOACCESS,
3977                 &spr_read_generic, &spr_write_generic,
3978                 0x00000000);
3979    /* XXX : not implemented */
3980    spr_register(env, SPR_440_CCR1, "CCR1",
3981                 SPR_NOACCESS, SPR_NOACCESS,
3982                 &spr_read_generic, &spr_write_generic,
3983                 0x00000000);
3984    /* Memory management */
3985#if !defined(CONFIG_USER_ONLY)
3986    env->nb_tlb = 64;
3987    env->nb_ways = 1;
3988    env->id_tlbs = 0;
3989    env->tlb_type = TLB_EMB;
3990#endif
3991    init_excp_BookE(env);
3992    env->dcache_line_size = 32;
3993    env->icache_line_size = 32;
3994    ppc40x_irq_init(env);
3995
3996    SET_FIT_PERIOD(12, 16, 20, 24);
3997    SET_WDT_PERIOD(20, 24, 28, 32);
3998}
3999
4000POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
4001{
4002    DeviceClass *dc = DEVICE_CLASS(oc);
4003    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4004
4005    dc->desc = "PowerPC 440x5";
4006    pcc->init_proc = init_proc_440x5;
4007    pcc->check_pow = check_pow_nocheck;
4008    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4009                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4010                       PPC_CACHE | PPC_CACHE_ICBI |
4011                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4012                       PPC_MEM_TLBSYNC | PPC_MFTB |
4013                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4014                       PPC_440_SPEC;
4015    pcc->msr_mask = (1ull << MSR_POW) |
4016                    (1ull << MSR_CE) |
4017                    (1ull << MSR_EE) |
4018                    (1ull << MSR_PR) |
4019                    (1ull << MSR_FP) |
4020                    (1ull << MSR_ME) |
4021                    (1ull << MSR_FE0) |
4022                    (1ull << MSR_DWE) |
4023                    (1ull << MSR_DE) |
4024                    (1ull << MSR_FE1) |
4025                    (1ull << MSR_IR) |
4026                    (1ull << MSR_DR);
4027    pcc->mmu_model = POWERPC_MMU_BOOKE;
4028    pcc->excp_model = POWERPC_EXCP_BOOKE;
4029    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4030    pcc->bfd_mach = bfd_mach_ppc_403;
4031    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4032                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4033}
4034
4035POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
4036{
4037    DeviceClass *dc = DEVICE_CLASS(oc);
4038    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4039
4040    dc->desc = "PowerPC 440x5 with double precision FPU";
4041    pcc->init_proc = init_proc_440x5;
4042    pcc->check_pow = check_pow_nocheck;
4043    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4044                       PPC_FLOAT | PPC_FLOAT_FSQRT |
4045                       PPC_FLOAT_STFIWX |
4046                       PPC_DCR | PPC_WRTEE | PPC_RFMCI |
4047                       PPC_CACHE | PPC_CACHE_ICBI |
4048                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4049                       PPC_MEM_TLBSYNC | PPC_MFTB |
4050                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4051                       PPC_440_SPEC;
4052    pcc->insns_flags2 = PPC2_FP_CVT_S64;
4053    pcc->msr_mask = (1ull << MSR_POW) |
4054                    (1ull << MSR_CE) |
4055                    (1ull << MSR_EE) |
4056                    (1ull << MSR_PR) |
4057                    (1ull << MSR_FP) |
4058                    (1ull << MSR_ME) |
4059                    (1ull << MSR_FE0) |
4060                    (1ull << MSR_DWE) |
4061                    (1ull << MSR_DE) |
4062                    (1ull << MSR_FE1) |
4063                    (1ull << MSR_IR) |
4064                    (1ull << MSR_DR);
4065    pcc->mmu_model = POWERPC_MMU_BOOKE;
4066    pcc->excp_model = POWERPC_EXCP_BOOKE;
4067    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4068    pcc->bfd_mach = bfd_mach_ppc_403;
4069    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4070                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4071}
4072
4073static void init_proc_460 (CPUPPCState *env)
4074{
4075    /* Time base */
4076    gen_tbl(env);
4077    gen_spr_BookE(env, 0x000000000000FFFFULL);
4078    gen_spr_440(env);
4079    gen_spr_usprgh(env);
4080    /* Processor identification */
4081    spr_register(env, SPR_BOOKE_PIR, "PIR",
4082                 SPR_NOACCESS, SPR_NOACCESS,
4083                 &spr_read_generic, &spr_write_pir,
4084                 0x00000000);
4085    /* XXX : not implemented */
4086    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4087                 SPR_NOACCESS, SPR_NOACCESS,
4088                 &spr_read_generic, &spr_write_generic,
4089                 0x00000000);
4090    /* XXX : not implemented */
4091    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4092                 SPR_NOACCESS, SPR_NOACCESS,
4093                 &spr_read_generic, &spr_write_generic,
4094                 0x00000000);
4095    /* XXX : not implemented */
4096    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4097                 SPR_NOACCESS, SPR_NOACCESS,
4098                 &spr_read_generic, &spr_write_generic,
4099                 0x00000000);
4100    /* XXX : not implemented */
4101    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4102                 SPR_NOACCESS, SPR_NOACCESS,
4103                 &spr_read_generic, &spr_write_generic,
4104                 0x00000000);
4105    /* XXX : not implemented */
4106    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4107                 SPR_NOACCESS, SPR_NOACCESS,
4108                 &spr_read_generic, &spr_write_generic,
4109                 0x00000000);
4110    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4111                 SPR_NOACCESS, SPR_NOACCESS,
4112                 &spr_read_generic, &spr_write_generic,
4113                 0x00000000);
4114    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4115                 SPR_NOACCESS, SPR_NOACCESS,
4116                 &spr_read_generic, &spr_write_generic,
4117                 0x00000000);
4118    /* XXX : not implemented */
4119    spr_register(env, SPR_440_CCR1, "CCR1",
4120                 SPR_NOACCESS, SPR_NOACCESS,
4121                 &spr_read_generic, &spr_write_generic,
4122                 0x00000000);
4123    /* XXX : not implemented */
4124    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4125                 &spr_read_generic, &spr_write_generic,
4126                 &spr_read_generic, &spr_write_generic,
4127                 0x00000000);
4128    /* Memory management */
4129#if !defined(CONFIG_USER_ONLY)
4130    env->nb_tlb = 64;
4131    env->nb_ways = 1;
4132    env->id_tlbs = 0;
4133    env->tlb_type = TLB_EMB;
4134#endif
4135    init_excp_BookE(env);
4136    env->dcache_line_size = 32;
4137    env->icache_line_size = 32;
4138    /* XXX: TODO: allocate internal IRQ controller */
4139
4140    SET_FIT_PERIOD(12, 16, 20, 24);
4141    SET_WDT_PERIOD(20, 24, 28, 32);
4142}
4143
4144POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
4145{
4146    DeviceClass *dc = DEVICE_CLASS(oc);
4147    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4148
4149    dc->desc = "PowerPC 460 (guessed)";
4150    pcc->init_proc = init_proc_460;
4151    pcc->check_pow = check_pow_nocheck;
4152    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4153                       PPC_DCR | PPC_DCRX  | PPC_DCRUX |
4154                       PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
4155                       PPC_CACHE | PPC_CACHE_ICBI |
4156                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4157                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
4158                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4159                       PPC_440_SPEC;
4160    pcc->msr_mask = (1ull << MSR_POW) |
4161                    (1ull << MSR_CE) |
4162                    (1ull << MSR_EE) |
4163                    (1ull << MSR_PR) |
4164                    (1ull << MSR_FP) |
4165                    (1ull << MSR_ME) |
4166                    (1ull << MSR_FE0) |
4167                    (1ull << MSR_DWE) |
4168                    (1ull << MSR_DE) |
4169                    (1ull << MSR_FE1) |
4170                    (1ull << MSR_IR) |
4171                    (1ull << MSR_DR);
4172    pcc->mmu_model = POWERPC_MMU_BOOKE;
4173    pcc->excp_model = POWERPC_EXCP_BOOKE;
4174    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4175    pcc->bfd_mach = bfd_mach_ppc_403;
4176    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4177                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4178}
4179
4180static void init_proc_460F (CPUPPCState *env)
4181{
4182    /* Time base */
4183    gen_tbl(env);
4184    gen_spr_BookE(env, 0x000000000000FFFFULL);
4185    gen_spr_440(env);
4186    gen_spr_usprgh(env);
4187    /* Processor identification */
4188    spr_register(env, SPR_BOOKE_PIR, "PIR",
4189                 SPR_NOACCESS, SPR_NOACCESS,
4190                 &spr_read_generic, &spr_write_pir,
4191                 0x00000000);
4192    /* XXX : not implemented */
4193    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4194                 SPR_NOACCESS, SPR_NOACCESS,
4195                 &spr_read_generic, &spr_write_generic,
4196                 0x00000000);
4197    /* XXX : not implemented */
4198    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4199                 SPR_NOACCESS, SPR_NOACCESS,
4200                 &spr_read_generic, &spr_write_generic,
4201                 0x00000000);
4202    /* XXX : not implemented */
4203    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4204                 SPR_NOACCESS, SPR_NOACCESS,
4205                 &spr_read_generic, &spr_write_generic,
4206                 0x00000000);
4207    /* XXX : not implemented */
4208    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4209                 SPR_NOACCESS, SPR_NOACCESS,
4210                 &spr_read_generic, &spr_write_generic,
4211                 0x00000000);
4212    /* XXX : not implemented */
4213    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4214                 SPR_NOACCESS, SPR_NOACCESS,
4215                 &spr_read_generic, &spr_write_generic,
4216                 0x00000000);
4217    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4218                 SPR_NOACCESS, SPR_NOACCESS,
4219                 &spr_read_generic, &spr_write_generic,
4220                 0x00000000);
4221    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4222                 SPR_NOACCESS, SPR_NOACCESS,
4223                 &spr_read_generic, &spr_write_generic,
4224                 0x00000000);
4225    /* XXX : not implemented */
4226    spr_register(env, SPR_440_CCR1, "CCR1",
4227                 SPR_NOACCESS, SPR_NOACCESS,
4228                 &spr_read_generic, &spr_write_generic,
4229                 0x00000000);
4230    /* XXX : not implemented */
4231    spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4232                 &spr_read_generic, &spr_write_generic,
4233                 &spr_read_generic, &spr_write_generic,
4234                 0x00000000);
4235    /* Memory management */
4236#if !defined(CONFIG_USER_ONLY)
4237    env->nb_tlb = 64;
4238    env->nb_ways = 1;
4239    env->id_tlbs = 0;
4240    env->tlb_type = TLB_EMB;
4241#endif
4242    init_excp_BookE(env);
4243    env->dcache_line_size = 32;
4244    env->icache_line_size = 32;
4245    /* XXX: TODO: allocate internal IRQ controller */
4246
4247    SET_FIT_PERIOD(12, 16, 20, 24);
4248    SET_WDT_PERIOD(20, 24, 28, 32);
4249}
4250
4251POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4252{
4253    DeviceClass *dc = DEVICE_CLASS(oc);
4254    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4255
4256    dc->desc = "PowerPC 460F (guessed)";
4257    pcc->init_proc = init_proc_460F;
4258    pcc->check_pow = check_pow_nocheck;
4259    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4260                       PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4261                       PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4262                       PPC_FLOAT_STFIWX | PPC_MFTB |
4263                       PPC_DCR | PPC_DCRX | PPC_DCRUX |
4264                       PPC_WRTEE | PPC_MFAPIDI |
4265                       PPC_CACHE | PPC_CACHE_ICBI |
4266                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4267                       PPC_MEM_TLBSYNC | PPC_TLBIVA |
4268                       PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4269                       PPC_440_SPEC;
4270    pcc->msr_mask = (1ull << MSR_POW) |
4271                    (1ull << MSR_CE) |
4272                    (1ull << MSR_EE) |
4273                    (1ull << MSR_PR) |
4274                    (1ull << MSR_FP) |
4275                    (1ull << MSR_ME) |
4276                    (1ull << MSR_FE0) |
4277                    (1ull << MSR_DWE) |
4278                    (1ull << MSR_DE) |
4279                    (1ull << MSR_FE1) |
4280                    (1ull << MSR_IR) |
4281                    (1ull << MSR_DR);
4282    pcc->mmu_model = POWERPC_MMU_BOOKE;
4283    pcc->excp_model = POWERPC_EXCP_BOOKE;
4284    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4285    pcc->bfd_mach = bfd_mach_ppc_403;
4286    pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4287                 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4288}
4289
4290static void init_proc_MPC5xx (CPUPPCState *env)
4291{
4292    /* Time base */
4293    gen_tbl(env);
4294    gen_spr_5xx_8xx(env);
4295    gen_spr_5xx(env);
4296    init_excp_MPC5xx(env);
4297    env->dcache_line_size = 32;
4298    env->icache_line_size = 32;
4299    /* XXX: TODO: allocate internal IRQ controller */
4300}
4301
4302POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4303{
4304    DeviceClass *dc = DEVICE_CLASS(oc);
4305    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4306
4307    dc->desc = "Freescale 5xx cores (aka RCPU)";
4308    pcc->init_proc = init_proc_MPC5xx;
4309    pcc->check_pow = check_pow_none;
4310    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4311                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4312                       PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4313                       PPC_MFTB;
4314    pcc->msr_mask = (1ull << MSR_ILE) |
4315                    (1ull << MSR_EE) |
4316                    (1ull << MSR_PR) |
4317                    (1ull << MSR_FP) |
4318                    (1ull << MSR_ME) |
4319                    (1ull << MSR_FE0) |
4320                    (1ull << MSR_SE) |
4321                    (1ull << MSR_DE) |
4322                    (1ull << MSR_FE1) |
4323                    (1ull << MSR_EP) |
4324                    (1ull << MSR_RI) |
4325                    (1ull << MSR_LE);
4326    pcc->mmu_model = POWERPC_MMU_REAL;
4327    pcc->excp_model = POWERPC_EXCP_603;
4328    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4329    pcc->bfd_mach = bfd_mach_ppc_505;
4330    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4331                 POWERPC_FLAG_BUS_CLK;
4332}
4333
4334static void init_proc_MPC8xx (CPUPPCState *env)
4335{
4336    /* Time base */
4337    gen_tbl(env);
4338    gen_spr_5xx_8xx(env);
4339    gen_spr_8xx(env);
4340    init_excp_MPC8xx(env);
4341    env->dcache_line_size = 32;
4342    env->icache_line_size = 32;
4343    /* XXX: TODO: allocate internal IRQ controller */
4344}
4345
4346POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4347{
4348    DeviceClass *dc = DEVICE_CLASS(oc);
4349    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4350
4351    dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4352    pcc->init_proc = init_proc_MPC8xx;
4353    pcc->check_pow = check_pow_none;
4354    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING  |
4355                       PPC_MEM_EIEIO | PPC_MEM_SYNC |
4356                       PPC_CACHE_ICBI | PPC_MFTB;
4357    pcc->msr_mask = (1ull << MSR_ILE) |
4358                    (1ull << MSR_EE) |
4359                    (1ull << MSR_PR) |
4360                    (1ull << MSR_FP) |
4361                    (1ull << MSR_ME) |
4362                    (1ull << MSR_SE) |
4363                    (1ull << MSR_DE) |
4364                    (1ull << MSR_EP) |
4365                    (1ull << MSR_IR) |
4366                    (1ull << MSR_DR) |
4367                    (1ull << MSR_RI) |
4368                    (1ull << MSR_LE);
4369    pcc->mmu_model = POWERPC_MMU_MPC8xx;
4370    pcc->excp_model = POWERPC_EXCP_603;
4371    pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4372    pcc->bfd_mach = bfd_mach_ppc_860;
4373    pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4374                 POWERPC_FLAG_BUS_CLK;
4375}
4376
4377/* Freescale 82xx cores (aka PowerQUICC-II)                                  */
4378
4379static void init_proc_G2 (CPUPPCState *env)
4380{
4381    gen_spr_ne_601(env);
4382    gen_spr_G2_755(env);
4383    gen_spr_G2(env);
4384    /* Time base */
4385    gen_tbl(env);
4386    /* External access control */
4387    /* XXX : not implemented */
4388    spr_register(env, SPR_EAR, "EAR",
4389                 SPR_NOACCESS, SPR_NOACCESS,
4390                 &spr_read_generic, &spr_write_generic,
4391                 0x00000000);
4392    /* Hardware implementation register */
4393    /* XXX : not implemented */
4394    spr_register(env, SPR_HID0, "HID0",
4395                 SPR_NOACCESS, SPR_NOACCESS,
4396                 &spr_read_generic, &spr_write_generic,
4397                 0x00000000);
4398    /* XXX : not implemented */
4399    spr_register(env, SPR_HID1, "HID1",
4400                 SPR_NOACCESS, SPR_NOACCESS,
4401                 &spr_read_generic, &spr_write_generic,
4402                 0x00000000);
4403    /* XXX : not implemented */
4404    spr_register(env, SPR_HID2, "HID2",
4405                 SPR_NOACCESS, SPR_NOACCESS,
4406                 &spr_read_generic, &spr_write_generic,
4407                 0x00000000);
4408    /* Memory management */
4409    gen_low_BATs(env);
4410    gen_high_BATs(env);
4411    gen_6xx_7xx_soft_tlb(env, 64, 2);
4412    init_excp_G2(env);
4413    env->dcache_line_size = 32;
4414    env->icache_line_size = 32;
4415    /* Allocate hardware IRQ controller */
4416    ppc6xx_irq_init(env);
4417}
4418
4419POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4420{
4421    DeviceClass *dc = DEVICE_CLASS(oc);
4422    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4423
4424    dc->desc = "PowerPC G2";
4425    pcc->init_proc = init_proc_G2;
4426    pcc->check_pow = check_pow_hid0;
4427    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4428                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4429                       PPC_FLOAT_STFIWX |
4430                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4431                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4432                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4433                       PPC_SEGMENT | PPC_EXTERN;
4434    pcc->msr_mask = (1ull << MSR_POW) |
4435                    (1ull << MSR_TGPR) |
4436                    (1ull << MSR_EE) |
4437                    (1ull << MSR_PR) |
4438                    (1ull << MSR_FP) |
4439                    (1ull << MSR_ME) |
4440                    (1ull << MSR_FE0) |
4441                    (1ull << MSR_SE) |
4442                    (1ull << MSR_DE) |
4443                    (1ull << MSR_FE1) |
4444                    (1ull << MSR_AL) |
4445                    (1ull << MSR_EP) |
4446                    (1ull << MSR_IR) |
4447                    (1ull << MSR_DR) |
4448                    (1ull << MSR_RI);
4449    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4450    pcc->excp_model = POWERPC_EXCP_G2;
4451    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4452    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4453    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4454                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4455}
4456
4457static void init_proc_G2LE (CPUPPCState *env)
4458{
4459    gen_spr_ne_601(env);
4460    gen_spr_G2_755(env);
4461    gen_spr_G2(env);
4462    /* Time base */
4463    gen_tbl(env);
4464    /* External access control */
4465    /* XXX : not implemented */
4466    spr_register(env, SPR_EAR, "EAR",
4467                 SPR_NOACCESS, SPR_NOACCESS,
4468                 &spr_read_generic, &spr_write_generic,
4469                 0x00000000);
4470    /* Hardware implementation register */
4471    /* XXX : not implemented */
4472    spr_register(env, SPR_HID0, "HID0",
4473                 SPR_NOACCESS, SPR_NOACCESS,
4474                 &spr_read_generic, &spr_write_generic,
4475                 0x00000000);
4476    /* XXX : not implemented */
4477    spr_register(env, SPR_HID1, "HID1",
4478                 SPR_NOACCESS, SPR_NOACCESS,
4479                 &spr_read_generic, &spr_write_generic,
4480                 0x00000000);
4481    /* XXX : not implemented */
4482    spr_register(env, SPR_HID2, "HID2",
4483                 SPR_NOACCESS, SPR_NOACCESS,
4484                 &spr_read_generic, &spr_write_generic,
4485                 0x00000000);
4486
4487    /* Memory management */
4488    gen_low_BATs(env);
4489    gen_high_BATs(env);
4490    gen_6xx_7xx_soft_tlb(env, 64, 2);
4491    init_excp_G2(env);
4492    env->dcache_line_size = 32;
4493    env->icache_line_size = 32;
4494    /* Allocate hardware IRQ controller */
4495    ppc6xx_irq_init(env);
4496}
4497
4498POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4499{
4500    DeviceClass *dc = DEVICE_CLASS(oc);
4501    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4502
4503    dc->desc = "PowerPC G2LE";
4504    pcc->init_proc = init_proc_G2LE;
4505    pcc->check_pow = check_pow_hid0;
4506    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4507                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4508                       PPC_FLOAT_STFIWX |
4509                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4510                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4511                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4512                       PPC_SEGMENT | PPC_EXTERN;
4513    pcc->msr_mask = (1ull << MSR_POW) |
4514                    (1ull << MSR_TGPR) |
4515                    (1ull << MSR_ILE) |
4516                    (1ull << MSR_EE) |
4517                    (1ull << MSR_PR) |
4518                    (1ull << MSR_FP) |
4519                    (1ull << MSR_ME) |
4520                    (1ull << MSR_FE0) |
4521                    (1ull << MSR_SE) |
4522                    (1ull << MSR_DE) |
4523                    (1ull << MSR_FE1) |
4524                    (1ull << MSR_AL) |
4525                    (1ull << MSR_EP) |
4526                    (1ull << MSR_IR) |
4527                    (1ull << MSR_DR) |
4528                    (1ull << MSR_RI) |
4529                    (1ull << MSR_LE);
4530    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4531    pcc->excp_model = POWERPC_EXCP_G2;
4532    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4533    pcc->bfd_mach = bfd_mach_ppc_ec603e;
4534    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4535                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4536}
4537
4538static void init_proc_e200 (CPUPPCState *env)
4539{
4540    /* Time base */
4541    gen_tbl(env);
4542    gen_spr_BookE(env, 0x000000070000FFFFULL);
4543    /* XXX : not implemented */
4544    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4545                 &spr_read_spefscr, &spr_write_spefscr,
4546                 &spr_read_spefscr, &spr_write_spefscr,
4547                 0x00000000);
4548    /* Memory management */
4549    gen_spr_BookE206(env, 0x0000005D, NULL);
4550    /* XXX : not implemented */
4551    spr_register(env, SPR_HID0, "HID0",
4552                 SPR_NOACCESS, SPR_NOACCESS,
4553                 &spr_read_generic, &spr_write_generic,
4554                 0x00000000);
4555    /* XXX : not implemented */
4556    spr_register(env, SPR_HID1, "HID1",
4557                 SPR_NOACCESS, SPR_NOACCESS,
4558                 &spr_read_generic, &spr_write_generic,
4559                 0x00000000);
4560    /* XXX : not implemented */
4561    spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4562                 SPR_NOACCESS, SPR_NOACCESS,
4563                 &spr_read_generic, &spr_write_generic,
4564                 0x00000000);
4565    /* XXX : not implemented */
4566    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4567                 SPR_NOACCESS, SPR_NOACCESS,
4568                 &spr_read_generic, &spr_write_generic,
4569                 0x00000000);
4570    /* XXX : not implemented */
4571    spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4572                 SPR_NOACCESS, SPR_NOACCESS,
4573                 &spr_read_generic, &spr_write_generic,
4574                 0x00000000);
4575    /* XXX : not implemented */
4576    spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4577                 SPR_NOACCESS, SPR_NOACCESS,
4578                 &spr_read_generic, &spr_write_generic,
4579                 0x00000000);
4580    /* XXX : not implemented */
4581    spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4582                 SPR_NOACCESS, SPR_NOACCESS,
4583                 &spr_read_generic, &spr_write_generic,
4584                 0x00000000);
4585    /* XXX : not implemented */
4586    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4587                 &spr_read_generic, SPR_NOACCESS,
4588                 &spr_read_generic, SPR_NOACCESS,
4589                 0x00000000);
4590    /* XXX : not implemented */
4591    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4592                 SPR_NOACCESS, SPR_NOACCESS,
4593                 &spr_read_generic, &spr_write_generic,
4594                 0x00000000);
4595    /* XXX : not implemented */
4596    spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4597                 SPR_NOACCESS, SPR_NOACCESS,
4598                 &spr_read_generic, &spr_write_generic,
4599                 0x00000000);
4600    /* XXX : not implemented */
4601    spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4602                 SPR_NOACCESS, SPR_NOACCESS,
4603                 &spr_read_generic, &spr_write_generic,
4604                 0x00000000);
4605    /* XXX : not implemented */
4606    spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4607                 SPR_NOACCESS, SPR_NOACCESS,
4608                 &spr_read_generic, &spr_write_generic,
4609                 0x00000000);
4610    /* XXX : not implemented */
4611    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4612                 SPR_NOACCESS, SPR_NOACCESS,
4613                 &spr_read_generic, &spr_write_generic,
4614                 0x00000000);
4615    /* XXX : not implemented */
4616    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4617                 SPR_NOACCESS, SPR_NOACCESS,
4618                 &spr_read_generic, &spr_write_generic,
4619                 0x00000000);
4620    /* XXX : not implemented */
4621    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4622                 SPR_NOACCESS, SPR_NOACCESS,
4623                 &spr_read_generic, &spr_write_generic,
4624                 0x00000000); /* TOFIX */
4625    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4626                 SPR_NOACCESS, SPR_NOACCESS,
4627                 &spr_read_generic, &spr_write_generic,
4628                 0x00000000);
4629    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4630                 SPR_NOACCESS, SPR_NOACCESS,
4631                 &spr_read_generic, &spr_write_generic,
4632                 0x00000000);
4633#if !defined(CONFIG_USER_ONLY)
4634    env->nb_tlb = 64;
4635    env->nb_ways = 1;
4636    env->id_tlbs = 0;
4637    env->tlb_type = TLB_EMB;
4638#endif
4639    init_excp_e200(env, 0xFFFF0000UL);
4640    env->dcache_line_size = 32;
4641    env->icache_line_size = 32;
4642    /* XXX: TODO: allocate internal IRQ controller */
4643}
4644
4645POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4646{
4647    DeviceClass *dc = DEVICE_CLASS(oc);
4648    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4649
4650    dc->desc = "e200 core";
4651    pcc->init_proc = init_proc_e200;
4652    pcc->check_pow = check_pow_hid0;
4653    /* XXX: unimplemented instructions:
4654     * dcblc
4655     * dcbtlst
4656     * dcbtstls
4657     * icblc
4658     * icbtls
4659     * tlbivax
4660     * all SPE multiply-accumulate instructions
4661     */
4662    pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4663                       PPC_SPE | PPC_SPE_SINGLE |
4664                       PPC_WRTEE | PPC_RFDI |
4665                       PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4666                       PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4667                       PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4668                       PPC_BOOKE;
4669    pcc->msr_mask = (1ull << MSR_UCLE) |
4670                    (1ull << MSR_SPE) |
4671                    (1ull << MSR_POW) |
4672                    (1ull << MSR_CE) |
4673                    (1ull << MSR_EE) |
4674                    (1ull << MSR_PR) |
4675                    (1ull << MSR_FP) |
4676                    (1ull << MSR_ME) |
4677                    (1ull << MSR_FE0) |
4678                    (1ull << MSR_DWE) |
4679                    (1ull << MSR_DE) |
4680                    (1ull << MSR_FE1) |
4681                    (1ull << MSR_IR) |
4682                    (1ull << MSR_DR);
4683    pcc->mmu_model = POWERPC_MMU_BOOKE206;
4684    pcc->excp_model = POWERPC_EXCP_BOOKE;
4685    pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4686    pcc->bfd_mach = bfd_mach_ppc_860;
4687    pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4688                 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4689                 POWERPC_FLAG_BUS_CLK;
4690}
4691
4692static void init_proc_e300 (CPUPPCState *env)
4693{
4694    gen_spr_ne_601(env);
4695    gen_spr_603(env);
4696    /* Time base */
4697    gen_tbl(env);
4698    /* hardware implementation registers */
4699    /* XXX : not implemented */
4700    spr_register(env, SPR_HID0, "HID0",
4701                 SPR_NOACCESS, SPR_NOACCESS,
4702                 &spr_read_generic, &spr_write_generic,
4703                 0x00000000);
4704    /* XXX : not implemented */
4705    spr_register(env, SPR_HID1, "HID1",
4706                 SPR_NOACCESS, SPR_NOACCESS,
4707                 &spr_read_generic, &spr_write_generic,
4708                 0x00000000);
4709    /* XXX : not implemented */
4710    spr_register(env, SPR_HID2, "HID2",
4711                 SPR_NOACCESS, SPR_NOACCESS,
4712                 &spr_read_generic, &spr_write_generic,
4713                 0x00000000);
4714    /* Breakpoints */
4715    /* XXX : not implemented */
4716    spr_register(env, SPR_DABR, "DABR",
4717                 SPR_NOACCESS, SPR_NOACCESS,
4718                 &spr_read_generic, &spr_write_generic,
4719                 0x00000000);
4720    /* XXX : not implemented */
4721    spr_register(env, SPR_DABR2, "DABR2",
4722                 SPR_NOACCESS, SPR_NOACCESS,
4723                 &spr_read_generic, &spr_write_generic,
4724                 0x00000000);
4725    /* XXX : not implemented */
4726    spr_register(env, SPR_IABR2, "IABR2",
4727                 SPR_NOACCESS, SPR_NOACCESS,
4728                 &spr_read_generic, &spr_write_generic,
4729                 0x00000000);
4730    /* XXX : not implemented */
4731    spr_register(env, SPR_IBCR, "IBCR",
4732                 SPR_NOACCESS, SPR_NOACCESS,
4733                 &spr_read_generic, &spr_write_generic,
4734                 0x00000000);
4735    /* XXX : not implemented */
4736    spr_register(env, SPR_DBCR, "DBCR",
4737                 SPR_NOACCESS, SPR_NOACCESS,
4738                 &spr_read_generic, &spr_write_generic,
4739                 0x00000000);
4740    /* Memory management */
4741    gen_low_BATs(env);
4742    gen_high_BATs(env);
4743    gen_6xx_7xx_soft_tlb(env, 64, 2);
4744    init_excp_603(env);
4745    env->dcache_line_size = 32;
4746    env->icache_line_size = 32;
4747    /* Allocate hardware IRQ controller */
4748    ppc6xx_irq_init(env);
4749}
4750
4751POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4752{
4753    DeviceClass *dc = DEVICE_CLASS(oc);
4754    PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4755
4756    dc->desc = "e300 core";
4757    pcc->init_proc = init_proc_e300;
4758    pcc->check_pow = check_pow_hid0;
4759    pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4760                       PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4761                       PPC_FLOAT_STFIWX |
4762                       PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4763                       PPC_MEM_SYNC | PPC_MEM_EIEIO |
4764                       PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4765                       PPC_SEGMENT | PPC_EXTERN;
4766    pcc->msr_mask = (1ull << MSR_POW) |
4767                    (1ull << MSR_TGPR) |
4768                    (1ull << MSR_ILE) |
4769                    (1ull << MSR_EE) |
4770                    (1ull << MSR_PR) |
4771                    (1ull << MSR_FP) |
4772                    (1ull << MSR_ME) |
4773                    (1ull << MSR_FE0) |
4774                    (1ull << MSR_SE) |
4775                    (1ull << MSR_DE) |
4776                    (1ull << MSR_FE1) |
4777                    (1ull << MSR_AL) |
4778                    (1ull << MSR_EP) |
4779                    (1ull << MSR_IR) |
4780                    (1ull << MSR_DR) |
4781                    (1ull << MSR_RI) |
4782                    (1ull << MSR_LE);
4783    pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4784    pcc->excp_model = POWERPC_EXCP_603;
4785    pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4786    pcc->bfd_mach = bfd_mach_ppc_603;
4787    pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4788                 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4789}
4790
4791#if !defined(CONFIG_USER_ONLY)
4792static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn)
4793{
4794    TCGv val = tcg_temp_new();
4795    tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4796    gen_store_spr(SPR_BOOKE_MAS3, val);
4797    tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4798    gen_store_spr(SPR_BOOKE_MAS7, val);
4799    tcg_temp_free(val);
4800}
4801
4802static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn)
4803{
4804    TCGv mas7 = tcg_temp_new();
4805    TCGv mas3 = tcg_temp_new();
4806    gen_load_spr(mas7, SPR_BOOKE_MAS7);
4807    tcg_gen_shli_tl(mas7, mas7, 32);
4808    gen_load_spr(mas3, SPR_BOOKE_MAS3);
4809    tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4810    tcg_temp_free(mas3);
4811    tcg_temp_free(mas7);
4812}
4813
4814#endif
4815
4816enum fsl_e500_version {
4817    fsl_e500v1,
4818    fsl_e500v2,
4819    fsl_e500mc,
4820    fsl_e5500,
4821};
4822
4823static void init_proc_e500 (CPUPPCState *env, int version)
4824{
4825    PowerPCCPU *cpu = ppc_env_get_cpu(env);
4826    uint32_t tlbncfg[2];
4827    uint64_t ivor_mask;
4828    uint64_t ivpr_mask = 0xFFFF0000ULL;
4829    uint32_t l1cfg0 = 0x3800  /* 8 ways */
4830                    | 0x0020; /* 32 kb */
4831    uint32_t l1cfg1 = 0x3800  /* 8 ways */
4832                    | 0x0020; /* 32 kb */
4833#if !defined(CONFIG_USER_ONLY)
4834    int i;
4835#endif
4836
4837    /* Time base */
4838    gen_tbl(env);
4839    /*
4840     * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4841     *     complain when accessing them.
4842     * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4843     */
4844    switch (version) {
4845        case fsl_e500v1:
4846        case fsl_e500v2:
4847        default:
4848            ivor_mask = 0x0000000F0000FFFFULL;
4849            break;
4850        case fsl_e500mc:
4851        case fsl_e5500:
4852            ivor_mask = 0x000003FE0000FFFFULL;
4853            break;
4854    }
4855    gen_spr_BookE(env, ivor_mask);
4856    /* Processor identification */
4857    spr_register(env, SPR_BOOKE_PIR, "PIR",
4858                 SPR_NOACCESS, SPR_NOACCESS,
4859                 &spr_read_generic, &spr_write_pir,
4860                 0x00000000);
4861    /* XXX : not implemented */
4862    spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4863                 &spr_read_spefscr, &spr_write_spefscr,
4864                 &spr_read_spefscr, &spr_write_spefscr,
4865                 0x00000000);
4866#if !defined(CONFIG_USER_ONLY)
4867    /* Memory management */
4868    env->nb_pids = 3;
4869    env->nb_ways = 2;
4870    env->id_tlbs = 0;
4871    switch (version) {
4872    case fsl_e500v1:
4873        tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4874        tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4875        break;
4876    case fsl_e500v2:
4877        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4878        tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4879        break;
4880    case fsl_e500mc:
4881    case fsl_e5500:
4882        tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4883        tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4884        break;
4885    default:
4886        cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4887    }
4888#endif
4889    /* Cache sizes */
4890    switch (version) {
4891    case fsl_e500v1:
4892    case fsl_e500v2:
4893        env->dcache_line_size = 32;
4894        env->icache_line_size = 32;
4895        break;
4896    case fsl_e500mc:
4897    case fsl_e5500:
4898        env->dcache_line_size = 64;
4899        env->icache_line_size = 64;
4900        l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4901        l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4902        break;
4903    default:
4904        cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4905    }
4906    gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4907    /* XXX : not implemented */
4908    spr_register(env, SPR_HID0, "HID0",
4909                 SPR_NOACCESS, SPR_NOACCESS,
4910                 &spr_read_generic, &spr_write_generic,
4911                 0x00000000);
4912    /* XXX : not implemented */
4913    spr_register(env, SPR_HID1, "HID1",
4914                 SPR_NOACCESS, SPR_NOACCESS,
4915                 &spr_read_generic, &spr_write_generic,
4916                 0x00000000);
4917    /* XXX : not implemented */
4918    spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4919                 SPR_NOACCESS, SPR_NOACCESS,
4920                 &spr_read_generic, &spr_write_generic,
4921                 0x00000000);
4922    /* XXX : not implemented */
4923    spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4924                 SPR_NOACCESS, SPR_NOACCESS,
4925                 &spr_read_generic, &spr_write_generic,
4926                 0x00000000);
4927    /* XXX : not implemented */
4928    spr_register(env, SPR_Exxx_MCAR, "MCAR",
4929                 SPR_NOACCESS, SPR_NOACCESS,
4930                 &spr_read_generic, &spr_write_generic,
4931                 0x00000000);
4932    /* XXX : not implemented */
4933    spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4934                 SPR_NOACCESS, SPR_NOACCESS,
4935                 &spr_read_generic, &spr_write_generic,
4936                 0x00000000);
4937    /* XXX : not implemented */
4938    spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4939                 SPR_NOACCESS, SPR_NOACCESS,
4940                 &spr_read_generic, &spr_write_generic,
4941                 0x00000000);
4942    /* XXX : not implemented */
4943    spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4944                 SPR_NOACCESS, SPR_NOACCESS,
4945                 &spr_read_generic, &spr_write_generic,
4946                 0x00000000);
4947    /* XXX : not implemented */
4948    spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4949                 &spr_read_generic, SPR_NOACCESS,
4950                 &spr_read_generic, SPR_NOACCESS,
4951                 l1cfg0);
4952    spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4953                 &spr_read_generic, SPR_NOACCESS,
4954                 &spr_read_generic, SPR_NOACCESS,
4955                 l1cfg1);
4956    spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4957                 SPR_NOACCESS, SPR_NOACCESS,
4958                 &spr_read_generic, &spr_write_e500_l1csr0,
4959                 0x00000000);
4960    spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4961                 SPR_NOACCESS, SPR_NOACCESS,
4962                 &spr_read_generic, &spr_write_e500_l1csr1,
4963                 0x00000000);
4964    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4965                 SPR_NOACCESS, SPR_NOACCESS,
4966                 &spr_read_generic, &spr_write_generic,
4967                 0x00000000);
4968    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4969                 SPR_NOACCESS, SPR_NOACCESS,
4970                 &spr_read_generic, &spr_write_generic,
4971                 0x00000000);
4972    spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4973                 SPR_NOACCESS, SPR_NOACCESS,
4974                 &spr_read_generic, &spr_write_booke206_mmucsr0,
4975                 0x00000000);
4976    spr_register(env, SPR_BOOKE_EPR, "EPR",
4977                 SPR_NOACCESS, SPR_NOACCESS,
4978                 &spr_read_generic, SPR_NOACCESS,
4979                 0x00000000);
4980    /* XXX better abstract into Emb.xxx features */
4981    if (version == fsl_e5500) {
4982        spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4983                     SPR_NOACCESS, SPR_NOACCESS,
4984                     &spr_read_generic, &spr_write_generic,
4985                     0x00000000);
4986        spr_register(env, SPR_BOOKE_MAS