qemu/target-tricore/translate.c
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   1/*
   2 *  TriCore emulation for qemu: main translation routines.
   3 *
   4 *  Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20
  21#include "qemu/osdep.h"
  22#include "cpu.h"
  23#include "disas/disas.h"
  24#include "tcg-op.h"
  25#include "exec/cpu_ldst.h"
  26
  27#include "exec/helper-proto.h"
  28#include "exec/helper-gen.h"
  29
  30#include "tricore-opcodes.h"
  31#include "exec/log.h"
  32
  33/*
  34 * TCG registers
  35 */
  36static TCGv cpu_PC;
  37static TCGv cpu_PCXI;
  38static TCGv cpu_PSW;
  39static TCGv cpu_ICR;
  40/* GPR registers */
  41static TCGv cpu_gpr_a[16];
  42static TCGv cpu_gpr_d[16];
  43/* PSW Flag cache */
  44static TCGv cpu_PSW_C;
  45static TCGv cpu_PSW_V;
  46static TCGv cpu_PSW_SV;
  47static TCGv cpu_PSW_AV;
  48static TCGv cpu_PSW_SAV;
  49/* CPU env */
  50static TCGv_env cpu_env;
  51
  52#include "exec/gen-icount.h"
  53
  54static const char *regnames_a[] = {
  55      "a0"  , "a1"  , "a2"  , "a3" , "a4"  , "a5" ,
  56      "a6"  , "a7"  , "a8"  , "a9" , "sp" , "a11" ,
  57      "a12" , "a13" , "a14" , "a15",
  58    };
  59
  60static const char *regnames_d[] = {
  61      "d0"  , "d1"  , "d2"  , "d3" , "d4"  , "d5"  ,
  62      "d6"  , "d7"  , "d8"  , "d9" , "d10" , "d11" ,
  63      "d12" , "d13" , "d14" , "d15",
  64    };
  65
  66typedef struct DisasContext {
  67    struct TranslationBlock *tb;
  68    target_ulong pc, saved_pc, next_pc;
  69    uint32_t opcode;
  70    int singlestep_enabled;
  71    /* Routine used to access memory */
  72    int mem_idx;
  73    uint32_t hflags, saved_hflags;
  74    int bstate;
  75} DisasContext;
  76
  77enum {
  78
  79    BS_NONE   = 0,
  80    BS_STOP   = 1,
  81    BS_BRANCH = 2,
  82    BS_EXCP   = 3,
  83};
  84
  85enum {
  86    MODE_LL = 0,
  87    MODE_LU = 1,
  88    MODE_UL = 2,
  89    MODE_UU = 3,
  90};
  91
  92void tricore_cpu_dump_state(CPUState *cs, FILE *f,
  93                            fprintf_function cpu_fprintf, int flags)
  94{
  95    TriCoreCPU *cpu = TRICORE_CPU(cs);
  96    CPUTriCoreState *env = &cpu->env;
  97    uint32_t psw;
  98    int i;
  99
 100    psw = psw_read(env);
 101
 102    cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
 103    cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
 104    cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
 105    cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
 106    cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
 107    cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
 108
 109    for (i = 0; i < 16; ++i) {
 110        if ((i & 3) == 0) {
 111            cpu_fprintf(f, "\nGPR A%02d:", i);
 112        }
 113        cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
 114    }
 115    for (i = 0; i < 16; ++i) {
 116        if ((i & 3) == 0) {
 117            cpu_fprintf(f, "\nGPR D%02d:", i);
 118        }
 119        cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
 120    }
 121    cpu_fprintf(f, "\n");
 122}
 123
 124/*
 125 * Functions to generate micro-ops
 126 */
 127
 128/* Makros for generating helpers */
 129
 130#define gen_helper_1arg(name, arg) do {                           \
 131    TCGv_i32 helper_tmp = tcg_const_i32(arg);                     \
 132    gen_helper_##name(cpu_env, helper_tmp);                       \
 133    tcg_temp_free_i32(helper_tmp);                                \
 134    } while (0)
 135
 136#define GEN_HELPER_LL(name, ret, arg0, arg1, n) do {         \
 137    TCGv arg00 = tcg_temp_new();                             \
 138    TCGv arg01 = tcg_temp_new();                             \
 139    TCGv arg11 = tcg_temp_new();                             \
 140    tcg_gen_sari_tl(arg00, arg0, 16);                        \
 141    tcg_gen_ext16s_tl(arg01, arg0);                          \
 142    tcg_gen_ext16s_tl(arg11, arg1);                          \
 143    gen_helper_##name(ret, arg00, arg01, arg11, arg11, n);   \
 144    tcg_temp_free(arg00);                                    \
 145    tcg_temp_free(arg01);                                    \
 146    tcg_temp_free(arg11);                                    \
 147} while (0)
 148
 149#define GEN_HELPER_LU(name, ret, arg0, arg1, n) do {         \
 150    TCGv arg00 = tcg_temp_new();                             \
 151    TCGv arg01 = tcg_temp_new();                             \
 152    TCGv arg10 = tcg_temp_new();                             \
 153    TCGv arg11 = tcg_temp_new();                             \
 154    tcg_gen_sari_tl(arg00, arg0, 16);                        \
 155    tcg_gen_ext16s_tl(arg01, arg0);                          \
 156    tcg_gen_sari_tl(arg11, arg1, 16);                        \
 157    tcg_gen_ext16s_tl(arg10, arg1);                          \
 158    gen_helper_##name(ret, arg00, arg01, arg10, arg11, n);   \
 159    tcg_temp_free(arg00);                                    \
 160    tcg_temp_free(arg01);                                    \
 161    tcg_temp_free(arg10);                                    \
 162    tcg_temp_free(arg11);                                    \
 163} while (0)
 164
 165#define GEN_HELPER_UL(name, ret, arg0, arg1, n) do {         \
 166    TCGv arg00 = tcg_temp_new();                             \
 167    TCGv arg01 = tcg_temp_new();                             \
 168    TCGv arg10 = tcg_temp_new();                             \
 169    TCGv arg11 = tcg_temp_new();                             \
 170    tcg_gen_sari_tl(arg00, arg0, 16);                        \
 171    tcg_gen_ext16s_tl(arg01, arg0);                          \
 172    tcg_gen_sari_tl(arg10, arg1, 16);                        \
 173    tcg_gen_ext16s_tl(arg11, arg1);                          \
 174    gen_helper_##name(ret, arg00, arg01, arg10, arg11, n);   \
 175    tcg_temp_free(arg00);                                    \
 176    tcg_temp_free(arg01);                                    \
 177    tcg_temp_free(arg10);                                    \
 178    tcg_temp_free(arg11);                                    \
 179} while (0)
 180
 181#define GEN_HELPER_UU(name, ret, arg0, arg1, n) do {         \
 182    TCGv arg00 = tcg_temp_new();                             \
 183    TCGv arg01 = tcg_temp_new();                             \
 184    TCGv arg11 = tcg_temp_new();                             \
 185    tcg_gen_sari_tl(arg01, arg0, 16);                        \
 186    tcg_gen_ext16s_tl(arg00, arg0);                          \
 187    tcg_gen_sari_tl(arg11, arg1, 16);                        \
 188    gen_helper_##name(ret, arg00, arg01, arg11, arg11, n);   \
 189    tcg_temp_free(arg00);                                    \
 190    tcg_temp_free(arg01);                                    \
 191    tcg_temp_free(arg11);                                    \
 192} while (0)
 193
 194#define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do {    \
 195    TCGv_i64 ret = tcg_temp_new_i64();                       \
 196    TCGv_i64 arg1 = tcg_temp_new_i64();                      \
 197                                                             \
 198    tcg_gen_concat_i32_i64(arg1, al1, ah1);                  \
 199    gen_helper_##name(ret, arg1, arg2);                      \
 200    tcg_gen_extr_i64_i32(rl, rh, ret);                       \
 201                                                             \
 202    tcg_temp_free_i64(ret);                                  \
 203    tcg_temp_free_i64(arg1);                                 \
 204} while (0)
 205
 206#define GEN_HELPER_RR(name, rl, rh, arg1, arg2) do {        \
 207    TCGv_i64 ret = tcg_temp_new_i64();                      \
 208                                                            \
 209    gen_helper_##name(ret, cpu_env, arg1, arg2);            \
 210    tcg_gen_extr_i64_i32(rl, rh, ret);                      \
 211                                                            \
 212    tcg_temp_free_i64(ret);                                 \
 213} while (0)
 214
 215#define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
 216#define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
 217                           ((offset & 0x0fffff) << 1))
 218
 219/* For two 32-bit registers used a 64-bit register, the first
 220   registernumber needs to be even. Otherwise we trap. */
 221static inline void generate_trap(DisasContext *ctx, int class, int tin);
 222#define CHECK_REG_PAIR(reg) do {                      \
 223    if (reg & 0x1) {                                  \
 224        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_OPD); \
 225    }                                                 \
 226} while (0)
 227
 228/* Functions for load/save to/from memory */
 229
 230static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
 231                                 int16_t con, TCGMemOp mop)
 232{
 233    TCGv temp = tcg_temp_new();
 234    tcg_gen_addi_tl(temp, r2, con);
 235    tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
 236    tcg_temp_free(temp);
 237}
 238
 239static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
 240                                 int16_t con, TCGMemOp mop)
 241{
 242    TCGv temp = tcg_temp_new();
 243    tcg_gen_addi_tl(temp, r2, con);
 244    tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
 245    tcg_temp_free(temp);
 246}
 247
 248static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
 249{
 250    TCGv_i64 temp = tcg_temp_new_i64();
 251
 252    tcg_gen_concat_i32_i64(temp, rl, rh);
 253    tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
 254
 255    tcg_temp_free_i64(temp);
 256}
 257
 258static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
 259                                DisasContext *ctx)
 260{
 261    TCGv temp = tcg_temp_new();
 262    tcg_gen_addi_tl(temp, base, con);
 263    gen_st_2regs_64(rh, rl, temp, ctx);
 264    tcg_temp_free(temp);
 265}
 266
 267static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
 268{
 269    TCGv_i64 temp = tcg_temp_new_i64();
 270
 271    tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
 272    /* write back to two 32 bit regs */
 273    tcg_gen_extr_i64_i32(rl, rh, temp);
 274
 275    tcg_temp_free_i64(temp);
 276}
 277
 278static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
 279                                DisasContext *ctx)
 280{
 281    TCGv temp = tcg_temp_new();
 282    tcg_gen_addi_tl(temp, base, con);
 283    gen_ld_2regs_64(rh, rl, temp, ctx);
 284    tcg_temp_free(temp);
 285}
 286
 287static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
 288                           TCGMemOp mop)
 289{
 290    TCGv temp = tcg_temp_new();
 291    tcg_gen_addi_tl(temp, r2, off);
 292    tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
 293    tcg_gen_mov_tl(r2, temp);
 294    tcg_temp_free(temp);
 295}
 296
 297static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
 298                           TCGMemOp mop)
 299{
 300    TCGv temp = tcg_temp_new();
 301    tcg_gen_addi_tl(temp, r2, off);
 302    tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
 303    tcg_gen_mov_tl(r2, temp);
 304    tcg_temp_free(temp);
 305}
 306
 307/* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
 308static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
 309{
 310    TCGv temp = tcg_temp_new();
 311    TCGv temp2 = tcg_temp_new();
 312
 313    CHECK_REG_PAIR(ereg);
 314    /* temp = (M(EA, word) */
 315    tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
 316    /* temp = temp & ~E[a][63:32]) */
 317    tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
 318    /* temp2 = (E[a][31:0] & E[a][63:32]); */
 319    tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
 320    /* temp = temp | temp2; */
 321    tcg_gen_or_tl(temp, temp, temp2);
 322    /* M(EA, word) = temp; */
 323    tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
 324
 325    tcg_temp_free(temp);
 326    tcg_temp_free(temp2);
 327}
 328
 329/* tmp = M(EA, word);
 330   M(EA, word) = D[a];
 331   D[a] = tmp[31:0];*/
 332static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
 333{
 334    TCGv temp = tcg_temp_new();
 335
 336    tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
 337    tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
 338    tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
 339
 340    tcg_temp_free(temp);
 341}
 342
 343static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
 344{
 345    TCGv temp = tcg_temp_new();
 346    TCGv temp2 = tcg_temp_new();
 347    tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
 348    tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
 349                       cpu_gpr_d[reg], temp);
 350    tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
 351    tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
 352
 353    tcg_temp_free(temp);
 354    tcg_temp_free(temp2);
 355}
 356
 357static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
 358{
 359    TCGv temp = tcg_temp_new();
 360    TCGv temp2 = tcg_temp_new();
 361    TCGv temp3 = tcg_temp_new();
 362
 363    tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
 364    tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
 365    tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
 366    tcg_gen_or_tl(temp2, temp2, temp3);
 367    tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
 368    tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
 369
 370    tcg_temp_free(temp);
 371    tcg_temp_free(temp2);
 372    tcg_temp_free(temp3);
 373}
 374
 375
 376/* We generate loads and store to core special function register (csfr) through
 377   the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
 378   makros R, A and E, which allow read-only, all and endinit protected access.
 379   These makros also specify in which ISA version the csfr was introduced. */
 380#define R(ADDRESS, REG, FEATURE)                                         \
 381    case ADDRESS:                                                        \
 382        if (tricore_feature(env, FEATURE)) {                             \
 383            tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
 384        }                                                                \
 385        break;
 386#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
 387#define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
 388static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
 389{
 390    /* since we're caching PSW make this a special case */
 391    if (offset == 0xfe04) {
 392        gen_helper_psw_read(ret, cpu_env);
 393    } else {
 394        switch (offset) {
 395#include "csfr.def"
 396        }
 397    }
 398}
 399#undef R
 400#undef A
 401#undef E
 402
 403#define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
 404                                    since no execption occurs */
 405#define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)                \
 406    case ADDRESS:                                                        \
 407        if (tricore_feature(env, FEATURE)) {                             \
 408            tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG));  \
 409        }                                                                \
 410        break;
 411/* Endinit protected registers
 412   TODO: Since the endinit bit is in a register of a not yet implemented
 413         watchdog device, we handle endinit protected registers like
 414         all-access registers for now. */
 415#define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
 416static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
 417                            int32_t offset)
 418{
 419    if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
 420        /* since we're caching PSW make this a special case */
 421        if (offset == 0xfe04) {
 422            gen_helper_psw_write(cpu_env, r1);
 423        } else {
 424            switch (offset) {
 425#include "csfr.def"
 426            }
 427        }
 428    } else {
 429        /* generate privilege trap */
 430    }
 431}
 432
 433/* Functions for arithmetic instructions  */
 434
 435static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
 436{
 437    TCGv t0 = tcg_temp_new_i32();
 438    TCGv result = tcg_temp_new_i32();
 439    /* Addition and set V/SV bits */
 440    tcg_gen_add_tl(result, r1, r2);
 441    /* calc V bit */
 442    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
 443    tcg_gen_xor_tl(t0, r1, r2);
 444    tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
 445    /* Calc SV bit */
 446    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 447    /* Calc AV/SAV bits */
 448    tcg_gen_add_tl(cpu_PSW_AV, result, result);
 449    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
 450    /* calc SAV */
 451    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 452    /* write back result */
 453    tcg_gen_mov_tl(ret, result);
 454
 455    tcg_temp_free(result);
 456    tcg_temp_free(t0);
 457}
 458
 459static inline void
 460gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
 461{
 462    TCGv temp = tcg_temp_new();
 463    TCGv_i64 t0 = tcg_temp_new_i64();
 464    TCGv_i64 t1 = tcg_temp_new_i64();
 465    TCGv_i64 result = tcg_temp_new_i64();
 466
 467    tcg_gen_add_i64(result, r1, r2);
 468    /* calc v bit */
 469    tcg_gen_xor_i64(t1, result, r1);
 470    tcg_gen_xor_i64(t0, r1, r2);
 471    tcg_gen_andc_i64(t1, t1, t0);
 472    tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
 473    /* calc SV bit */
 474    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 475    /* calc AV/SAV bits */
 476    tcg_gen_extrh_i64_i32(temp, result);
 477    tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
 478    tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
 479    /* calc SAV */
 480    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 481    /* write back result */
 482    tcg_gen_mov_i64(ret, result);
 483
 484    tcg_temp_free(temp);
 485    tcg_temp_free_i64(result);
 486    tcg_temp_free_i64(t0);
 487    tcg_temp_free_i64(t1);
 488}
 489
 490static inline void
 491gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 492               TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
 493               void(*op2)(TCGv, TCGv, TCGv))
 494{
 495    TCGv temp = tcg_temp_new();
 496    TCGv temp2 = tcg_temp_new();
 497    TCGv temp3 = tcg_temp_new();
 498    TCGv temp4 = tcg_temp_new();
 499
 500    (*op1)(temp, r1_low, r2);
 501    /* calc V0 bit */
 502    tcg_gen_xor_tl(temp2, temp, r1_low);
 503    tcg_gen_xor_tl(temp3, r1_low, r2);
 504    if (op1 == tcg_gen_add_tl) {
 505        tcg_gen_andc_tl(temp2, temp2, temp3);
 506    } else {
 507        tcg_gen_and_tl(temp2, temp2, temp3);
 508    }
 509
 510    (*op2)(temp3, r1_high, r3);
 511    /* calc V1 bit */
 512    tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
 513    tcg_gen_xor_tl(temp4, r1_high, r3);
 514    if (op2 == tcg_gen_add_tl) {
 515        tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
 516    } else {
 517        tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
 518    }
 519    /* combine V0/V1 bits */
 520    tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
 521    /* calc sv bit */
 522    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 523    /* write result */
 524    tcg_gen_mov_tl(ret_low, temp);
 525    tcg_gen_mov_tl(ret_high, temp3);
 526    /* calc AV bit */
 527    tcg_gen_add_tl(temp, ret_low, ret_low);
 528    tcg_gen_xor_tl(temp, temp, ret_low);
 529    tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
 530    tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
 531    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
 532    /* calc SAV bit */
 533    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 534
 535    tcg_temp_free(temp);
 536    tcg_temp_free(temp2);
 537    tcg_temp_free(temp3);
 538    tcg_temp_free(temp4);
 539}
 540
 541/* ret = r2 + (r1 * r3); */
 542static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
 543{
 544    TCGv_i64 t1 = tcg_temp_new_i64();
 545    TCGv_i64 t2 = tcg_temp_new_i64();
 546    TCGv_i64 t3 = tcg_temp_new_i64();
 547
 548    tcg_gen_ext_i32_i64(t1, r1);
 549    tcg_gen_ext_i32_i64(t2, r2);
 550    tcg_gen_ext_i32_i64(t3, r3);
 551
 552    tcg_gen_mul_i64(t1, t1, t3);
 553    tcg_gen_add_i64(t1, t2, t1);
 554
 555    tcg_gen_extrl_i64_i32(ret, t1);
 556    /* calc V
 557       t1 > 0x7fffffff */
 558    tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
 559    /* t1 < -0x80000000 */
 560    tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
 561    tcg_gen_or_i64(t2, t2, t3);
 562    tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
 563    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
 564    /* Calc SV bit */
 565    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 566    /* Calc AV/SAV bits */
 567    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
 568    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
 569    /* calc SAV */
 570    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 571
 572    tcg_temp_free_i64(t1);
 573    tcg_temp_free_i64(t2);
 574    tcg_temp_free_i64(t3);
 575}
 576
 577static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
 578{
 579    TCGv temp = tcg_const_i32(con);
 580    gen_madd32_d(ret, r1, r2, temp);
 581    tcg_temp_free(temp);
 582}
 583
 584static inline void
 585gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
 586             TCGv r3)
 587{
 588    TCGv t1 = tcg_temp_new();
 589    TCGv t2 = tcg_temp_new();
 590    TCGv t3 = tcg_temp_new();
 591    TCGv t4 = tcg_temp_new();
 592
 593    tcg_gen_muls2_tl(t1, t2, r1, r3);
 594    /* only the add can overflow */
 595    tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
 596    /* calc V bit */
 597    tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
 598    tcg_gen_xor_tl(t1, r2_high, t2);
 599    tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
 600    /* Calc SV bit */
 601    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 602    /* Calc AV/SAV bits */
 603    tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
 604    tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
 605    /* calc SAV */
 606    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 607    /* write back the result */
 608    tcg_gen_mov_tl(ret_low, t3);
 609    tcg_gen_mov_tl(ret_high, t4);
 610
 611    tcg_temp_free(t1);
 612    tcg_temp_free(t2);
 613    tcg_temp_free(t3);
 614    tcg_temp_free(t4);
 615}
 616
 617static inline void
 618gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
 619              TCGv r3)
 620{
 621    TCGv_i64 t1 = tcg_temp_new_i64();
 622    TCGv_i64 t2 = tcg_temp_new_i64();
 623    TCGv_i64 t3 = tcg_temp_new_i64();
 624
 625    tcg_gen_extu_i32_i64(t1, r1);
 626    tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
 627    tcg_gen_extu_i32_i64(t3, r3);
 628
 629    tcg_gen_mul_i64(t1, t1, t3);
 630    tcg_gen_add_i64(t2, t2, t1);
 631    /* write back result */
 632    tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
 633    /* only the add overflows, if t2 < t1
 634       calc V bit */
 635    tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
 636    tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
 637    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
 638    /* Calc SV bit */
 639    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
 640    /* Calc AV/SAV bits */
 641    tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
 642    tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
 643    /* calc SAV */
 644    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
 645
 646    tcg_temp_free_i64(t1);
 647    tcg_temp_free_i64(t2);
 648    tcg_temp_free_i64(t3);
 649}
 650
 651static inline void
 652gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
 653              int32_t con)
 654{
 655    TCGv temp = tcg_const_i32(con);
 656    gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
 657    tcg_temp_free(temp);
 658}
 659
 660static inline void
 661gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
 662               int32_t con)
 663{
 664    TCGv temp = tcg_const_i32(con);
 665    gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
 666    tcg_temp_free(temp);
 667}
 668
 669static inline void
 670gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 671           TCGv r3, uint32_t n, uint32_t mode)
 672{
 673    TCGv temp = tcg_const_i32(n);
 674    TCGv temp2 = tcg_temp_new();
 675    TCGv_i64 temp64 = tcg_temp_new_i64();
 676    switch (mode) {
 677    case MODE_LL:
 678        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 679        break;
 680    case MODE_LU:
 681        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 682        break;
 683    case MODE_UL:
 684        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 685        break;
 686    case MODE_UU:
 687        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 688        break;
 689    }
 690    tcg_gen_extr_i64_i32(temp, temp2, temp64);
 691    gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
 692                   tcg_gen_add_tl, tcg_gen_add_tl);
 693    tcg_temp_free(temp);
 694    tcg_temp_free(temp2);
 695    tcg_temp_free_i64(temp64);
 696}
 697
 698static inline void
 699gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 700             TCGv r3, uint32_t n, uint32_t mode)
 701{
 702    TCGv temp = tcg_const_i32(n);
 703    TCGv temp2 = tcg_temp_new();
 704    TCGv_i64 temp64 = tcg_temp_new_i64();
 705    switch (mode) {
 706    case MODE_LL:
 707        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 708        break;
 709    case MODE_LU:
 710        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 711        break;
 712    case MODE_UL:
 713        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 714        break;
 715    case MODE_UU:
 716        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 717        break;
 718    }
 719    tcg_gen_extr_i64_i32(temp, temp2, temp64);
 720    gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
 721                   tcg_gen_sub_tl, tcg_gen_add_tl);
 722    tcg_temp_free(temp);
 723    tcg_temp_free(temp2);
 724    tcg_temp_free_i64(temp64);
 725}
 726
 727static inline void
 728gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 729              TCGv r3, uint32_t n, uint32_t mode)
 730{
 731    TCGv temp = tcg_const_i32(n);
 732    TCGv_i64 temp64 = tcg_temp_new_i64();
 733    TCGv_i64 temp64_2 = tcg_temp_new_i64();
 734    TCGv_i64 temp64_3 = tcg_temp_new_i64();
 735    switch (mode) {
 736    case MODE_LL:
 737        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 738        break;
 739    case MODE_LU:
 740        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 741        break;
 742    case MODE_UL:
 743        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 744        break;
 745    case MODE_UU:
 746        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 747        break;
 748    }
 749    tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
 750    tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
 751    tcg_gen_ext32s_i64(temp64, temp64); /* low */
 752    tcg_gen_sub_i64(temp64, temp64_2, temp64);
 753    tcg_gen_shli_i64(temp64, temp64, 16);
 754
 755    gen_add64_d(temp64_2, temp64_3, temp64);
 756    /* write back result */
 757    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
 758
 759    tcg_temp_free(temp);
 760    tcg_temp_free_i64(temp64);
 761    tcg_temp_free_i64(temp64_2);
 762    tcg_temp_free_i64(temp64_3);
 763}
 764
 765static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
 766
 767static inline void
 768gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 769           TCGv r3, uint32_t n, uint32_t mode)
 770{
 771    TCGv temp = tcg_const_i32(n);
 772    TCGv temp2 = tcg_temp_new();
 773    TCGv temp3 = tcg_temp_new();
 774    TCGv_i64 temp64 = tcg_temp_new_i64();
 775
 776    switch (mode) {
 777    case MODE_LL:
 778        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 779        break;
 780    case MODE_LU:
 781        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 782        break;
 783    case MODE_UL:
 784        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 785        break;
 786    case MODE_UU:
 787        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 788        break;
 789    }
 790    tcg_gen_extr_i64_i32(temp, temp2, temp64);
 791    gen_adds(ret_low, r1_low, temp);
 792    tcg_gen_mov_tl(temp, cpu_PSW_V);
 793    tcg_gen_mov_tl(temp3, cpu_PSW_AV);
 794    gen_adds(ret_high, r1_high, temp2);
 795    /* combine v bits */
 796    tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
 797    /* combine av bits */
 798    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
 799
 800    tcg_temp_free(temp);
 801    tcg_temp_free(temp2);
 802    tcg_temp_free(temp3);
 803    tcg_temp_free_i64(temp64);
 804
 805}
 806
 807static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
 808
 809static inline void
 810gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 811              TCGv r3, uint32_t n, uint32_t mode)
 812{
 813    TCGv temp = tcg_const_i32(n);
 814    TCGv temp2 = tcg_temp_new();
 815    TCGv temp3 = tcg_temp_new();
 816    TCGv_i64 temp64 = tcg_temp_new_i64();
 817
 818    switch (mode) {
 819    case MODE_LL:
 820        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 821        break;
 822    case MODE_LU:
 823        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 824        break;
 825    case MODE_UL:
 826        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 827        break;
 828    case MODE_UU:
 829        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 830        break;
 831    }
 832    tcg_gen_extr_i64_i32(temp, temp2, temp64);
 833    gen_subs(ret_low, r1_low, temp);
 834    tcg_gen_mov_tl(temp, cpu_PSW_V);
 835    tcg_gen_mov_tl(temp3, cpu_PSW_AV);
 836    gen_adds(ret_high, r1_high, temp2);
 837    /* combine v bits */
 838    tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
 839    /* combine av bits */
 840    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
 841
 842    tcg_temp_free(temp);
 843    tcg_temp_free(temp2);
 844    tcg_temp_free(temp3);
 845    tcg_temp_free_i64(temp64);
 846
 847}
 848
 849static inline void
 850gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 851               TCGv r3, uint32_t n, uint32_t mode)
 852{
 853    TCGv temp = tcg_const_i32(n);
 854    TCGv_i64 temp64 = tcg_temp_new_i64();
 855    TCGv_i64 temp64_2 = tcg_temp_new_i64();
 856
 857    switch (mode) {
 858    case MODE_LL:
 859        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 860        break;
 861    case MODE_LU:
 862        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 863        break;
 864    case MODE_UL:
 865        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 866        break;
 867    case MODE_UU:
 868        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 869        break;
 870    }
 871    tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
 872    tcg_gen_ext32s_i64(temp64, temp64); /* low */
 873    tcg_gen_sub_i64(temp64, temp64_2, temp64);
 874    tcg_gen_shli_i64(temp64, temp64, 16);
 875    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
 876
 877    gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
 878    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
 879
 880    tcg_temp_free(temp);
 881    tcg_temp_free_i64(temp64);
 882    tcg_temp_free_i64(temp64_2);
 883}
 884
 885
 886static inline void
 887gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 888           TCGv r3, uint32_t n, uint32_t mode)
 889{
 890    TCGv temp = tcg_const_i32(n);
 891    TCGv_i64 temp64 = tcg_temp_new_i64();
 892    TCGv_i64 temp64_2 = tcg_temp_new_i64();
 893    TCGv_i64 temp64_3 = tcg_temp_new_i64();
 894    switch (mode) {
 895    case MODE_LL:
 896        GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
 897        break;
 898    case MODE_LU:
 899        GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
 900        break;
 901    case MODE_UL:
 902        GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
 903        break;
 904    case MODE_UU:
 905        GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
 906        break;
 907    }
 908    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
 909    gen_add64_d(temp64_3, temp64_2, temp64);
 910    /* write back result */
 911    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
 912
 913    tcg_temp_free(temp);
 914    tcg_temp_free_i64(temp64);
 915    tcg_temp_free_i64(temp64_2);
 916    tcg_temp_free_i64(temp64_3);
 917}
 918
 919static inline void
 920gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
 921           TCGv r3, uint32_t n, uint32_t mode)
 922{
 923    TCGv temp = tcg_const_i32(n);
 924    TCGv_i64 temp64 = tcg_temp_new_i64();
 925    TCGv_i64 temp64_2 = tcg_temp_new_i64();
 926    switch (mode) {
 927    case MODE_LL:
 928        GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
 929        break;
 930    case MODE_LU:
 931        GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
 932        break;
 933    case MODE_UL:
 934        GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
 935        break;
 936    case MODE_UU:
 937        GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
 938        break;
 939    }
 940    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
 941    gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
 942    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
 943
 944    tcg_temp_free(temp);
 945    tcg_temp_free_i64(temp64);
 946    tcg_temp_free_i64(temp64_2);
 947}
 948
 949static inline void
 950gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
 951              uint32_t mode)
 952{
 953    TCGv temp = tcg_const_i32(n);
 954    TCGv_i64 temp64 = tcg_temp_new_i64();
 955    switch (mode) {
 956    case MODE_LL:
 957        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 958        break;
 959    case MODE_LU:
 960        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
 961        break;
 962    case MODE_UL:
 963        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
 964        break;
 965    case MODE_UU:
 966        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
 967        break;
 968    }
 969    gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
 970
 971    tcg_temp_free(temp);
 972    tcg_temp_free_i64(temp64);
 973}
 974
 975static inline void
 976gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
 977{
 978    TCGv temp = tcg_temp_new();
 979    TCGv temp2 = tcg_temp_new();
 980
 981    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
 982    tcg_gen_shli_tl(temp, r1, 16);
 983    gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
 984
 985    tcg_temp_free(temp);
 986    tcg_temp_free(temp2);
 987}
 988
 989static inline void
 990gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
 991{
 992    TCGv temp = tcg_const_i32(n);
 993    TCGv temp2 = tcg_temp_new();
 994    TCGv_i64 temp64 = tcg_temp_new_i64();
 995    switch (mode) {
 996    case MODE_LL:
 997        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
 998        break;
 999    case MODE_LU:
1000        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1001        break;
1002    case MODE_UL:
1003        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1004        break;
1005    case MODE_UU:
1006        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1007        break;
1008    }
1009    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1010    tcg_gen_shli_tl(temp, r1, 16);
1011    gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
1012
1013    tcg_temp_free(temp);
1014    tcg_temp_free(temp2);
1015    tcg_temp_free_i64(temp64);
1016}
1017
1018
1019static inline void
1020gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1021               uint32_t n, uint32_t mode)
1022{
1023    TCGv temp = tcg_const_i32(n);
1024    TCGv_i64 temp64 = tcg_temp_new_i64();
1025    switch (mode) {
1026    case MODE_LL:
1027        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1028        break;
1029    case MODE_LU:
1030        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1031        break;
1032    case MODE_UL:
1033        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1034        break;
1035    case MODE_UU:
1036        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1037        break;
1038    }
1039    gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1040
1041    tcg_temp_free(temp);
1042    tcg_temp_free_i64(temp64);
1043}
1044
1045static inline void
1046gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1047{
1048    TCGv temp = tcg_temp_new();
1049    TCGv temp2 = tcg_temp_new();
1050
1051    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1052    tcg_gen_shli_tl(temp, r1, 16);
1053    gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1054
1055    tcg_temp_free(temp);
1056    tcg_temp_free(temp2);
1057}
1058
1059static inline void
1060gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1061{
1062    TCGv temp = tcg_const_i32(n);
1063    TCGv temp2 = tcg_temp_new();
1064    TCGv_i64 temp64 = tcg_temp_new_i64();
1065    switch (mode) {
1066    case MODE_LL:
1067        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1068        break;
1069    case MODE_LU:
1070        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1071        break;
1072    case MODE_UL:
1073        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1074        break;
1075    case MODE_UU:
1076        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1077        break;
1078    }
1079    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1080    tcg_gen_shli_tl(temp, r1, 16);
1081    gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1082
1083    tcg_temp_free(temp);
1084    tcg_temp_free(temp2);
1085    tcg_temp_free_i64(temp64);
1086}
1087
1088static inline void
1089gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1090{
1091    TCGv temp = tcg_const_i32(n);
1092    gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1093    tcg_temp_free(temp);
1094}
1095
1096static inline void
1097gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1098{
1099    TCGv temp = tcg_const_i32(n);
1100    gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1101    tcg_temp_free(temp);
1102}
1103
1104static inline void
1105gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1106             uint32_t up_shift, CPUTriCoreState *env)
1107{
1108    TCGv temp = tcg_temp_new();
1109    TCGv temp2 = tcg_temp_new();
1110    TCGv temp3 = tcg_temp_new();
1111    TCGv_i64 t1 = tcg_temp_new_i64();
1112    TCGv_i64 t2 = tcg_temp_new_i64();
1113    TCGv_i64 t3 = tcg_temp_new_i64();
1114
1115    tcg_gen_ext_i32_i64(t2, arg2);
1116    tcg_gen_ext_i32_i64(t3, arg3);
1117
1118    tcg_gen_mul_i64(t2, t2, t3);
1119    tcg_gen_shli_i64(t2, t2, n);
1120
1121    tcg_gen_ext_i32_i64(t1, arg1);
1122    tcg_gen_sari_i64(t2, t2, up_shift);
1123
1124    tcg_gen_add_i64(t3, t1, t2);
1125    tcg_gen_extrl_i64_i32(temp3, t3);
1126    /* calc v bit */
1127    tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1128    tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1129    tcg_gen_or_i64(t1, t1, t2);
1130    tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1131    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1132    /* We produce an overflow on the host if the mul before was
1133       (0x80000000 * 0x80000000) << 1). If this is the
1134       case, we negate the ovf. */
1135    if (n == 1) {
1136        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1137        tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1138        tcg_gen_and_tl(temp, temp, temp2);
1139        tcg_gen_shli_tl(temp, temp, 31);
1140        /* negate v bit, if special condition */
1141        tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1142    }
1143    /* Calc SV bit */
1144    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1145    /* Calc AV/SAV bits */
1146    tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1147    tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1148    /* calc SAV */
1149    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1150    /* write back result */
1151    tcg_gen_mov_tl(ret, temp3);
1152
1153    tcg_temp_free(temp);
1154    tcg_temp_free(temp2);
1155    tcg_temp_free(temp3);
1156    tcg_temp_free_i64(t1);
1157    tcg_temp_free_i64(t2);
1158    tcg_temp_free_i64(t3);
1159}
1160
1161static inline void
1162gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1163{
1164    TCGv temp = tcg_temp_new();
1165    TCGv temp2 = tcg_temp_new();
1166    if (n == 0) {
1167        tcg_gen_mul_tl(temp, arg2, arg3);
1168    } else { /* n is expected to be 1 */
1169        tcg_gen_mul_tl(temp, arg2, arg3);
1170        tcg_gen_shli_tl(temp, temp, 1);
1171        /* catch special case r1 = r2 = 0x8000 */
1172        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1173        tcg_gen_sub_tl(temp, temp, temp2);
1174    }
1175    gen_add_d(ret, arg1, temp);
1176
1177    tcg_temp_free(temp);
1178    tcg_temp_free(temp2);
1179}
1180
1181static inline void
1182gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1183{
1184    TCGv temp = tcg_temp_new();
1185    TCGv temp2 = tcg_temp_new();
1186    if (n == 0) {
1187        tcg_gen_mul_tl(temp, arg2, arg3);
1188    } else { /* n is expected to be 1 */
1189        tcg_gen_mul_tl(temp, arg2, arg3);
1190        tcg_gen_shli_tl(temp, temp, 1);
1191        /* catch special case r1 = r2 = 0x8000 */
1192        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1193        tcg_gen_sub_tl(temp, temp, temp2);
1194    }
1195    gen_adds(ret, arg1, temp);
1196
1197    tcg_temp_free(temp);
1198    tcg_temp_free(temp2);
1199}
1200
1201static inline void
1202gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1203               TCGv arg3, uint32_t n)
1204{
1205    TCGv temp = tcg_temp_new();
1206    TCGv temp2 = tcg_temp_new();
1207    TCGv_i64 t1 = tcg_temp_new_i64();
1208    TCGv_i64 t2 = tcg_temp_new_i64();
1209    TCGv_i64 t3 = tcg_temp_new_i64();
1210
1211    if (n == 0) {
1212        tcg_gen_mul_tl(temp, arg2, arg3);
1213    } else { /* n is expected to be 1 */
1214        tcg_gen_mul_tl(temp, arg2, arg3);
1215        tcg_gen_shli_tl(temp, temp, 1);
1216        /* catch special case r1 = r2 = 0x8000 */
1217        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1218        tcg_gen_sub_tl(temp, temp, temp2);
1219    }
1220    tcg_gen_ext_i32_i64(t2, temp);
1221    tcg_gen_shli_i64(t2, t2, 16);
1222    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1223    gen_add64_d(t3, t1, t2);
1224    /* write back result */
1225    tcg_gen_extr_i64_i32(rl, rh, t3);
1226
1227    tcg_temp_free_i64(t1);
1228    tcg_temp_free_i64(t2);
1229    tcg_temp_free_i64(t3);
1230    tcg_temp_free(temp);
1231    tcg_temp_free(temp2);
1232}
1233
1234static inline void
1235gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1236               TCGv arg3, uint32_t n)
1237{
1238    TCGv temp = tcg_temp_new();
1239    TCGv temp2 = tcg_temp_new();
1240    TCGv_i64 t1 = tcg_temp_new_i64();
1241    TCGv_i64 t2 = tcg_temp_new_i64();
1242
1243    if (n == 0) {
1244        tcg_gen_mul_tl(temp, arg2, arg3);
1245    } else { /* n is expected to be 1 */
1246        tcg_gen_mul_tl(temp, arg2, arg3);
1247        tcg_gen_shli_tl(temp, temp, 1);
1248        /* catch special case r1 = r2 = 0x8000 */
1249        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1250        tcg_gen_sub_tl(temp, temp, temp2);
1251    }
1252    tcg_gen_ext_i32_i64(t2, temp);
1253    tcg_gen_shli_i64(t2, t2, 16);
1254    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1255
1256    gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1257    tcg_gen_extr_i64_i32(rl, rh, t1);
1258
1259    tcg_temp_free(temp);
1260    tcg_temp_free(temp2);
1261    tcg_temp_free_i64(t1);
1262    tcg_temp_free_i64(t2);
1263}
1264
1265static inline void
1266gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1267             TCGv arg3, uint32_t n, CPUTriCoreState *env)
1268{
1269    TCGv_i64 t1 = tcg_temp_new_i64();
1270    TCGv_i64 t2 = tcg_temp_new_i64();
1271    TCGv_i64 t3 = tcg_temp_new_i64();
1272    TCGv_i64 t4 = tcg_temp_new_i64();
1273    TCGv temp, temp2;
1274
1275    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1276    tcg_gen_ext_i32_i64(t2, arg2);
1277    tcg_gen_ext_i32_i64(t3, arg3);
1278
1279    tcg_gen_mul_i64(t2, t2, t3);
1280    if (n != 0) {
1281        tcg_gen_shli_i64(t2, t2, 1);
1282    }
1283    tcg_gen_add_i64(t4, t1, t2);
1284    /* calc v bit */
1285    tcg_gen_xor_i64(t3, t4, t1);
1286    tcg_gen_xor_i64(t2, t1, t2);
1287    tcg_gen_andc_i64(t3, t3, t2);
1288    tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
1289    /* We produce an overflow on the host if the mul before was
1290       (0x80000000 * 0x80000000) << 1). If this is the
1291       case, we negate the ovf. */
1292    if (n == 1) {
1293        temp = tcg_temp_new();
1294        temp2 = tcg_temp_new();
1295        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1296        tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1297        tcg_gen_and_tl(temp, temp, temp2);
1298        tcg_gen_shli_tl(temp, temp, 31);
1299        /* negate v bit, if special condition */
1300        tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1301
1302        tcg_temp_free(temp);
1303        tcg_temp_free(temp2);
1304    }
1305    /* write back result */
1306    tcg_gen_extr_i64_i32(rl, rh, t4);
1307    /* Calc SV bit */
1308    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1309    /* Calc AV/SAV bits */
1310    tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1311    tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1312    /* calc SAV */
1313    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1314
1315    tcg_temp_free_i64(t1);
1316    tcg_temp_free_i64(t2);
1317    tcg_temp_free_i64(t3);
1318    tcg_temp_free_i64(t4);
1319}
1320
1321static inline void
1322gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1323              uint32_t up_shift)
1324{
1325    TCGv_i64 t1 = tcg_temp_new_i64();
1326    TCGv_i64 t2 = tcg_temp_new_i64();
1327    TCGv_i64 t3 = tcg_temp_new_i64();
1328
1329    tcg_gen_ext_i32_i64(t1, arg1);
1330    tcg_gen_ext_i32_i64(t2, arg2);
1331    tcg_gen_ext_i32_i64(t3, arg3);
1332
1333    tcg_gen_mul_i64(t2, t2, t3);
1334    tcg_gen_sari_i64(t2, t2, up_shift - n);
1335
1336    gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1337
1338    tcg_temp_free_i64(t1);
1339    tcg_temp_free_i64(t2);
1340    tcg_temp_free_i64(t3);
1341}
1342
1343static inline void
1344gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1345             TCGv arg3, uint32_t n)
1346{
1347    TCGv_i64 r1 = tcg_temp_new_i64();
1348    TCGv temp = tcg_const_i32(n);
1349
1350    tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1351    gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1352    tcg_gen_extr_i64_i32(rl, rh, r1);
1353
1354    tcg_temp_free_i64(r1);
1355    tcg_temp_free(temp);
1356}
1357/* ret = r2 - (r1 * r3); */
1358static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1359{
1360    TCGv_i64 t1 = tcg_temp_new_i64();
1361    TCGv_i64 t2 = tcg_temp_new_i64();
1362    TCGv_i64 t3 = tcg_temp_new_i64();
1363
1364    tcg_gen_ext_i32_i64(t1, r1);
1365    tcg_gen_ext_i32_i64(t2, r2);
1366    tcg_gen_ext_i32_i64(t3, r3);
1367
1368    tcg_gen_mul_i64(t1, t1, t3);
1369    tcg_gen_sub_i64(t1, t2, t1);
1370
1371    tcg_gen_extrl_i64_i32(ret, t1);
1372    /* calc V
1373       t2 > 0x7fffffff */
1374    tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1375    /* result < -0x80000000 */
1376    tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1377    tcg_gen_or_i64(t2, t2, t3);
1378    tcg_gen_extrl_i64_i32(cpu_PSW_V, t2);
1379    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1380
1381    /* Calc SV bit */
1382    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1383    /* Calc AV/SAV bits */
1384    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1385    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1386    /* calc SAV */
1387    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1388
1389    tcg_temp_free_i64(t1);
1390    tcg_temp_free_i64(t2);
1391    tcg_temp_free_i64(t3);
1392}
1393
1394static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1395{
1396    TCGv temp = tcg_const_i32(con);
1397    gen_msub32_d(ret, r1, r2, temp);
1398    tcg_temp_free(temp);
1399}
1400
1401static inline void
1402gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1403             TCGv r3)
1404{
1405    TCGv t1 = tcg_temp_new();
1406    TCGv t2 = tcg_temp_new();
1407    TCGv t3 = tcg_temp_new();
1408    TCGv t4 = tcg_temp_new();
1409
1410    tcg_gen_muls2_tl(t1, t2, r1, r3);
1411    /* only the sub can overflow */
1412    tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1413    /* calc V bit */
1414    tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1415    tcg_gen_xor_tl(t1, r2_high, t2);
1416    tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1417    /* Calc SV bit */
1418    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1419    /* Calc AV/SAV bits */
1420    tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1421    tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1422    /* calc SAV */
1423    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1424    /* write back the result */
1425    tcg_gen_mov_tl(ret_low, t3);
1426    tcg_gen_mov_tl(ret_high, t4);
1427
1428    tcg_temp_free(t1);
1429    tcg_temp_free(t2);
1430    tcg_temp_free(t3);
1431    tcg_temp_free(t4);
1432}
1433
1434static inline void
1435gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1436              int32_t con)
1437{
1438    TCGv temp = tcg_const_i32(con);
1439    gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1440    tcg_temp_free(temp);
1441}
1442
1443static inline void
1444gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1445              TCGv r3)
1446{
1447    TCGv_i64 t1 = tcg_temp_new_i64();
1448    TCGv_i64 t2 = tcg_temp_new_i64();
1449    TCGv_i64 t3 = tcg_temp_new_i64();
1450
1451    tcg_gen_extu_i32_i64(t1, r1);
1452    tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1453    tcg_gen_extu_i32_i64(t3, r3);
1454
1455    tcg_gen_mul_i64(t1, t1, t3);
1456    tcg_gen_sub_i64(t3, t2, t1);
1457    tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1458    /* calc V bit, only the sub can overflow, if t1 > t2 */
1459    tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1460    tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1461    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1462    /* Calc SV bit */
1463    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1464    /* Calc AV/SAV bits */
1465    tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1466    tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1467    /* calc SAV */
1468    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1469
1470    tcg_temp_free_i64(t1);
1471    tcg_temp_free_i64(t2);
1472    tcg_temp_free_i64(t3);
1473}
1474
1475static inline void
1476gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1477               int32_t con)
1478{
1479    TCGv temp = tcg_const_i32(con);
1480    gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1481    tcg_temp_free(temp);
1482}
1483
1484static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1485{
1486    TCGv temp = tcg_const_i32(r2);
1487    gen_add_d(ret, r1, temp);
1488    tcg_temp_free(temp);
1489}
1490/* calculate the carry bit too */
1491static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1492{
1493    TCGv t0    = tcg_temp_new_i32();
1494    TCGv result = tcg_temp_new_i32();
1495
1496    tcg_gen_movi_tl(t0, 0);
1497    /* Addition and set C/V/SV bits */
1498    tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1499    /* calc V bit */
1500    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1501    tcg_gen_xor_tl(t0, r1, r2);
1502    tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1503    /* Calc SV bit */
1504    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1505    /* Calc AV/SAV bits */
1506    tcg_gen_add_tl(cpu_PSW_AV, result, result);
1507    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1508    /* calc SAV */
1509    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1510    /* write back result */
1511    tcg_gen_mov_tl(ret, result);
1512
1513    tcg_temp_free(result);
1514    tcg_temp_free(t0);
1515}
1516
1517static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1518{
1519    TCGv temp = tcg_const_i32(con);
1520    gen_add_CC(ret, r1, temp);
1521    tcg_temp_free(temp);
1522}
1523
1524static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1525{
1526    TCGv carry = tcg_temp_new_i32();
1527    TCGv t0    = tcg_temp_new_i32();
1528    TCGv result = tcg_temp_new_i32();
1529
1530    tcg_gen_movi_tl(t0, 0);
1531    tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1532    /* Addition, carry and set C/V/SV bits */
1533    tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1534    tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1535    /* calc V bit */
1536    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1537    tcg_gen_xor_tl(t0, r1, r2);
1538    tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1539    /* Calc SV bit */
1540    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1541    /* Calc AV/SAV bits */
1542    tcg_gen_add_tl(cpu_PSW_AV, result, result);
1543    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1544    /* calc SAV */
1545    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1546    /* write back result */
1547    tcg_gen_mov_tl(ret, result);
1548
1549    tcg_temp_free(result);
1550    tcg_temp_free(t0);
1551    tcg_temp_free(carry);
1552}
1553
1554static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1555{
1556    TCGv temp = tcg_const_i32(con);
1557    gen_addc_CC(ret, r1, temp);
1558    tcg_temp_free(temp);
1559}
1560
1561static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1562                                TCGv r4)
1563{
1564    TCGv temp = tcg_temp_new();
1565    TCGv temp2 = tcg_temp_new();
1566    TCGv result = tcg_temp_new();
1567    TCGv mask = tcg_temp_new();
1568    TCGv t0 = tcg_const_i32(0);
1569
1570    /* create mask for sticky bits */
1571    tcg_gen_setcond_tl(cond, mask, r4, t0);
1572    tcg_gen_shli_tl(mask, mask, 31);
1573
1574    tcg_gen_add_tl(result, r1, r2);
1575    /* Calc PSW_V */
1576    tcg_gen_xor_tl(temp, result, r1);
1577    tcg_gen_xor_tl(temp2, r1, r2);
1578    tcg_gen_andc_tl(temp, temp, temp2);
1579    tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1580    /* Set PSW_SV */
1581    tcg_gen_and_tl(temp, temp, mask);
1582    tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1583    /* calc AV bit */
1584    tcg_gen_add_tl(temp, result, result);
1585    tcg_gen_xor_tl(temp, temp, result);
1586    tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1587    /* calc SAV bit */
1588    tcg_gen_and_tl(temp, temp, mask);
1589    tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1590    /* write back result */
1591    tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1592
1593    tcg_temp_free(t0);
1594    tcg_temp_free(temp);
1595    tcg_temp_free(temp2);
1596    tcg_temp_free(result);
1597    tcg_temp_free(mask);
1598}
1599
1600static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1601                                 TCGv r3, TCGv r4)
1602{
1603    TCGv temp = tcg_const_i32(r2);
1604    gen_cond_add(cond, r1, temp, r3, r4);
1605    tcg_temp_free(temp);
1606}
1607
1608static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1609{
1610    TCGv temp = tcg_temp_new_i32();
1611    TCGv result = tcg_temp_new_i32();
1612
1613    tcg_gen_sub_tl(result, r1, r2);
1614    /* calc V bit */
1615    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1616    tcg_gen_xor_tl(temp, r1, r2);
1617    tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1618    /* calc SV bit */
1619    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1620    /* Calc AV bit */
1621    tcg_gen_add_tl(cpu_PSW_AV, result, result);
1622    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1623    /* calc SAV bit */
1624    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1625    /* write back result */
1626    tcg_gen_mov_tl(ret, result);
1627
1628    tcg_temp_free(temp);
1629    tcg_temp_free(result);
1630}
1631
1632static inline void
1633gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1634{
1635    TCGv temp = tcg_temp_new();
1636    TCGv_i64 t0 = tcg_temp_new_i64();
1637    TCGv_i64 t1 = tcg_temp_new_i64();
1638    TCGv_i64 result = tcg_temp_new_i64();
1639
1640    tcg_gen_sub_i64(result, r1, r2);
1641    /* calc v bit */
1642    tcg_gen_xor_i64(t1, result, r1);
1643    tcg_gen_xor_i64(t0, r1, r2);
1644    tcg_gen_and_i64(t1, t1, t0);
1645    tcg_gen_extrh_i64_i32(cpu_PSW_V, t1);
1646    /* calc SV bit */
1647    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1648    /* calc AV/SAV bits */
1649    tcg_gen_extrh_i64_i32(temp, result);
1650    tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1651    tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1652    /* calc SAV */
1653    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1654    /* write back result */
1655    tcg_gen_mov_i64(ret, result);
1656
1657    tcg_temp_free(temp);
1658    tcg_temp_free_i64(result);
1659    tcg_temp_free_i64(t0);
1660    tcg_temp_free_i64(t1);
1661}
1662
1663static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1664{
1665    TCGv result = tcg_temp_new();
1666    TCGv temp = tcg_temp_new();
1667
1668    tcg_gen_sub_tl(result, r1, r2);
1669    /* calc C bit */
1670    tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1671    /* calc V bit */
1672    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1673    tcg_gen_xor_tl(temp, r1, r2);
1674    tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1675    /* calc SV bit */
1676    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1677    /* Calc AV bit */
1678    tcg_gen_add_tl(cpu_PSW_AV, result, result);
1679    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1680    /* calc SAV bit */
1681    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1682    /* write back result */
1683    tcg_gen_mov_tl(ret, result);
1684
1685    tcg_temp_free(result);
1686    tcg_temp_free(temp);
1687}
1688
1689static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1690{
1691    TCGv temp = tcg_temp_new();
1692    tcg_gen_not_tl(temp, r2);
1693    gen_addc_CC(ret, r1, temp);
1694    tcg_temp_free(temp);
1695}
1696
1697static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1698                                TCGv r4)
1699{
1700    TCGv temp = tcg_temp_new();
1701    TCGv temp2 = tcg_temp_new();
1702    TCGv result = tcg_temp_new();
1703    TCGv mask = tcg_temp_new();
1704    TCGv t0 = tcg_const_i32(0);
1705
1706    /* create mask for sticky bits */
1707    tcg_gen_setcond_tl(cond, mask, r4, t0);
1708    tcg_gen_shli_tl(mask, mask, 31);
1709
1710    tcg_gen_sub_tl(result, r1, r2);
1711    /* Calc PSW_V */
1712    tcg_gen_xor_tl(temp, result, r1);
1713    tcg_gen_xor_tl(temp2, r1, r2);
1714    tcg_gen_and_tl(temp, temp, temp2);
1715    tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1716    /* Set PSW_SV */
1717    tcg_gen_and_tl(temp, temp, mask);
1718    tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1719    /* calc AV bit */
1720    tcg_gen_add_tl(temp, result, result);
1721    tcg_gen_xor_tl(temp, temp, result);
1722    tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1723    /* calc SAV bit */
1724    tcg_gen_and_tl(temp, temp, mask);
1725    tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1726    /* write back result */
1727    tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1728
1729    tcg_temp_free(t0);
1730    tcg_temp_free(temp);
1731    tcg_temp_free(temp2);
1732    tcg_temp_free(result);
1733    tcg_temp_free(mask);
1734}
1735
1736static inline void
1737gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1738           TCGv r3, uint32_t n, uint32_t mode)
1739{
1740    TCGv temp = tcg_const_i32(n);
1741    TCGv temp2 = tcg_temp_new();
1742    TCGv_i64 temp64 = tcg_temp_new_i64();
1743    switch (mode) {
1744    case MODE_LL:
1745        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1746        break;
1747    case MODE_LU:
1748        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1749        break;
1750    case MODE_UL:
1751        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1752        break;
1753    case MODE_UU:
1754        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1755        break;
1756    }
1757    tcg_gen_extr_i64_i32(temp, temp2, temp64);
1758    gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1759                   tcg_gen_sub_tl, tcg_gen_sub_tl);
1760    tcg_temp_free(temp);
1761    tcg_temp_free(temp2);
1762    tcg_temp_free_i64(temp64);
1763}
1764
1765static inline void
1766gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1767            TCGv r3, uint32_t n, uint32_t mode)
1768{
1769    TCGv temp = tcg_const_i32(n);
1770    TCGv temp2 = tcg_temp_new();
1771    TCGv temp3 = tcg_temp_new();
1772    TCGv_i64 temp64 = tcg_temp_new_i64();
1773
1774    switch (mode) {
1775    case MODE_LL:
1776        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1777        break;
1778    case MODE_LU:
1779        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1780        break;
1781    case MODE_UL:
1782        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1783        break;
1784    case MODE_UU:
1785        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1786        break;
1787    }
1788    tcg_gen_extr_i64_i32(temp, temp2, temp64);
1789    gen_subs(ret_low, r1_low, temp);
1790    tcg_gen_mov_tl(temp, cpu_PSW_V);
1791    tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1792    gen_subs(ret_high, r1_high, temp2);
1793    /* combine v bits */
1794    tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1795    /* combine av bits */
1796    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1797
1798    tcg_temp_free(temp);
1799    tcg_temp_free(temp2);
1800    tcg_temp_free(temp3);
1801    tcg_temp_free_i64(temp64);
1802}
1803
1804static inline void
1805gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1806            TCGv r3, uint32_t n, uint32_t mode)
1807{
1808    TCGv temp = tcg_const_i32(n);
1809    TCGv_i64 temp64 = tcg_temp_new_i64();
1810    TCGv_i64 temp64_2 = tcg_temp_new_i64();
1811    TCGv_i64 temp64_3 = tcg_temp_new_i64();
1812    switch (mode) {
1813    case MODE_LL:
1814        GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1815        break;
1816    case MODE_LU:
1817        GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1818        break;
1819    case MODE_UL:
1820        GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1821        break;
1822    case MODE_UU:
1823        GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1824        break;
1825    }
1826    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1827    gen_sub64_d(temp64_3, temp64_2, temp64);
1828    /* write back result */
1829    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1830
1831    tcg_temp_free(temp);
1832    tcg_temp_free_i64(temp64);
1833    tcg_temp_free_i64(temp64_2);
1834    tcg_temp_free_i64(temp64_3);
1835}
1836
1837static inline void
1838gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1839             TCGv r3, uint32_t n, uint32_t mode)
1840{
1841    TCGv temp = tcg_const_i32(n);
1842    TCGv_i64 temp64 = tcg_temp_new_i64();
1843    TCGv_i64 temp64_2 = tcg_temp_new_i64();
1844    switch (mode) {
1845    case MODE_LL:
1846        GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1847        break;
1848    case MODE_LU:
1849        GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1850        break;
1851    case MODE_UL:
1852        GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1853        break;
1854    case MODE_UU:
1855        GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1856        break;
1857    }
1858    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1859    gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1860    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1861
1862    tcg_temp_free(temp);
1863    tcg_temp_free_i64(temp64);
1864    tcg_temp_free_i64(temp64_2);
1865}
1866
1867static inline void
1868gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1869              uint32_t mode)
1870{
1871    TCGv temp = tcg_const_i32(n);
1872    TCGv_i64 temp64 = tcg_temp_new_i64();
1873    switch (mode) {
1874    case MODE_LL:
1875        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1876        break;
1877    case MODE_LU:
1878        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1879        break;
1880    case MODE_UL:
1881        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1882        break;
1883    case MODE_UU:
1884        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1885        break;
1886    }
1887    gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1888
1889    tcg_temp_free(temp);
1890    tcg_temp_free_i64(temp64);
1891}
1892
1893static inline void
1894gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1895{
1896    TCGv temp = tcg_temp_new();
1897    TCGv temp2 = tcg_temp_new();
1898
1899    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1900    tcg_gen_shli_tl(temp, r1, 16);
1901    gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1902
1903    tcg_temp_free(temp);
1904    tcg_temp_free(temp2);
1905}
1906
1907static inline void
1908gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1909               uint32_t n, uint32_t mode)
1910{
1911    TCGv temp = tcg_const_i32(n);
1912    TCGv_i64 temp64 = tcg_temp_new_i64();
1913    switch (mode) {
1914    case MODE_LL:
1915        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1916        break;
1917    case MODE_LU:
1918        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1919        break;
1920    case MODE_UL:
1921        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1922        break;
1923    case MODE_UU:
1924        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1925        break;
1926    }
1927    gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1928
1929    tcg_temp_free(temp);
1930    tcg_temp_free_i64(temp64);
1931}
1932
1933static inline void
1934gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1935{
1936    TCGv temp = tcg_temp_new();
1937    TCGv temp2 = tcg_temp_new();
1938
1939    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1940    tcg_gen_shli_tl(temp, r1, 16);
1941    gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1942
1943    tcg_temp_free(temp);
1944    tcg_temp_free(temp2);
1945}
1946
1947static inline void
1948gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1949{
1950    TCGv temp = tcg_const_i32(n);
1951    gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1952    tcg_temp_free(temp);
1953}
1954
1955static inline void
1956gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1957{
1958    TCGv temp = tcg_const_i32(n);
1959    gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1960    tcg_temp_free(temp);
1961}
1962
1963static inline void
1964gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1965             uint32_t up_shift, CPUTriCoreState *env)
1966{
1967    TCGv temp = tcg_temp_new();
1968    TCGv temp2 = tcg_temp_new();
1969    TCGv temp3 = tcg_temp_new();
1970    TCGv_i64 t1 = tcg_temp_new_i64();
1971    TCGv_i64 t2 = tcg_temp_new_i64();
1972    TCGv_i64 t3 = tcg_temp_new_i64();
1973    TCGv_i64 t4 = tcg_temp_new_i64();
1974
1975    tcg_gen_ext_i32_i64(t2, arg2);
1976    tcg_gen_ext_i32_i64(t3, arg3);
1977
1978    tcg_gen_mul_i64(t2, t2, t3);
1979
1980    tcg_gen_ext_i32_i64(t1, arg1);
1981    /* if we shift part of the fraction out, we need to round up */
1982    tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1983    tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1984    tcg_gen_sari_i64(t2, t2, up_shift - n);
1985    tcg_gen_add_i64(t2, t2, t4);
1986
1987    tcg_gen_sub_i64(t3, t1, t2);
1988    tcg_gen_extrl_i64_i32(temp3, t3);
1989    /* calc v bit */
1990    tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1991    tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1992    tcg_gen_or_i64(t1, t1, t2);
1993    tcg_gen_extrl_i64_i32(cpu_PSW_V, t1);
1994    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1995    /* Calc SV bit */
1996    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1997    /* Calc AV/SAV bits */
1998    tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1999    tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
2000    /* calc SAV */
2001    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2002    /* write back result */
2003    tcg_gen_mov_tl(ret, temp3);
2004
2005    tcg_temp_free(temp);
2006    tcg_temp_free(temp2);
2007    tcg_temp_free(temp3);
2008    tcg_temp_free_i64(t1);
2009    tcg_temp_free_i64(t2);
2010    tcg_temp_free_i64(t3);
2011    tcg_temp_free_i64(t4);
2012}
2013
2014static inline void
2015gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2016{
2017    TCGv temp = tcg_temp_new();
2018    TCGv temp2 = tcg_temp_new();
2019    if (n == 0) {
2020        tcg_gen_mul_tl(temp, arg2, arg3);
2021    } else { /* n is expected to be 1 */
2022        tcg_gen_mul_tl(temp, arg2, arg3);
2023        tcg_gen_shli_tl(temp, temp, 1);
2024        /* catch special case r1 = r2 = 0x8000 */
2025        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2026        tcg_gen_sub_tl(temp, temp, temp2);
2027    }
2028    gen_sub_d(ret, arg1, temp);
2029
2030    tcg_temp_free(temp);
2031    tcg_temp_free(temp2);
2032}
2033
2034static inline void
2035gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2036{
2037    TCGv temp = tcg_temp_new();
2038    TCGv temp2 = tcg_temp_new();
2039    if (n == 0) {
2040        tcg_gen_mul_tl(temp, arg2, arg3);
2041    } else { /* n is expected to be 1 */
2042        tcg_gen_mul_tl(temp, arg2, arg3);
2043        tcg_gen_shli_tl(temp, temp, 1);
2044        /* catch special case r1 = r2 = 0x8000 */
2045        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2046        tcg_gen_sub_tl(temp, temp, temp2);
2047    }
2048    gen_subs(ret, arg1, temp);
2049
2050    tcg_temp_free(temp);
2051    tcg_temp_free(temp2);
2052}
2053
2054static inline void
2055gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2056               TCGv arg3, uint32_t n)
2057{
2058    TCGv temp = tcg_temp_new();
2059    TCGv temp2 = tcg_temp_new();
2060    TCGv_i64 t1 = tcg_temp_new_i64();
2061    TCGv_i64 t2 = tcg_temp_new_i64();
2062    TCGv_i64 t3 = tcg_temp_new_i64();
2063
2064    if (n == 0) {
2065        tcg_gen_mul_tl(temp, arg2, arg3);
2066    } else { /* n is expected to be 1 */
2067        tcg_gen_mul_tl(temp, arg2, arg3);
2068        tcg_gen_shli_tl(temp, temp, 1);
2069        /* catch special case r1 = r2 = 0x8000 */
2070        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2071        tcg_gen_sub_tl(temp, temp, temp2);
2072    }
2073    tcg_gen_ext_i32_i64(t2, temp);
2074    tcg_gen_shli_i64(t2, t2, 16);
2075    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2076    gen_sub64_d(t3, t1, t2);
2077    /* write back result */
2078    tcg_gen_extr_i64_i32(rl, rh, t3);
2079
2080    tcg_temp_free_i64(t1);
2081    tcg_temp_free_i64(t2);
2082    tcg_temp_free_i64(t3);
2083    tcg_temp_free(temp);
2084    tcg_temp_free(temp2);
2085}
2086
2087static inline void
2088gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2089               TCGv arg3, uint32_t n)
2090{
2091    TCGv temp = tcg_temp_new();
2092    TCGv temp2 = tcg_temp_new();
2093    TCGv_i64 t1 = tcg_temp_new_i64();
2094    TCGv_i64 t2 = tcg_temp_new_i64();
2095
2096    if (n == 0) {
2097        tcg_gen_mul_tl(temp, arg2, arg3);
2098    } else { /* n is expected to be 1 */
2099        tcg_gen_mul_tl(temp, arg2, arg3);
2100        tcg_gen_shli_tl(temp, temp, 1);
2101        /* catch special case r1 = r2 = 0x8000 */
2102        tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2103        tcg_gen_sub_tl(temp, temp, temp2);
2104    }
2105    tcg_gen_ext_i32_i64(t2, temp);
2106    tcg_gen_shli_i64(t2, t2, 16);
2107    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2108
2109    gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2110    tcg_gen_extr_i64_i32(rl, rh, t1);
2111
2112    tcg_temp_free(temp);
2113    tcg_temp_free(temp2);
2114    tcg_temp_free_i64(t1);
2115    tcg_temp_free_i64(t2);
2116}
2117
2118static inline void
2119gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2120             TCGv arg3, uint32_t n, CPUTriCoreState *env)
2121{
2122    TCGv_i64 t1 = tcg_temp_new_i64();
2123    TCGv_i64 t2 = tcg_temp_new_i64();
2124    TCGv_i64 t3 = tcg_temp_new_i64();
2125    TCGv_i64 t4 = tcg_temp_new_i64();
2126    TCGv temp, temp2;
2127
2128    tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2129    tcg_gen_ext_i32_i64(t2, arg2);
2130    tcg_gen_ext_i32_i64(t3, arg3);
2131
2132    tcg_gen_mul_i64(t2, t2, t3);
2133    if (n != 0) {
2134        tcg_gen_shli_i64(t2, t2, 1);
2135    }
2136    tcg_gen_sub_i64(t4, t1, t2);
2137    /* calc v bit */
2138    tcg_gen_xor_i64(t3, t4, t1);
2139    tcg_gen_xor_i64(t2, t1, t2);
2140    tcg_gen_and_i64(t3, t3, t2);
2141    tcg_gen_extrh_i64_i32(cpu_PSW_V, t3);
2142    /* We produce an overflow on the host if the mul before was
2143       (0x80000000 * 0x80000000) << 1). If this is the
2144       case, we negate the ovf. */
2145    if (n == 1) {
2146        temp = tcg_temp_new();
2147        temp2 = tcg_temp_new();
2148        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2149        tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2150        tcg_gen_and_tl(temp, temp, temp2);
2151        tcg_gen_shli_tl(temp, temp, 31);
2152        /* negate v bit, if special condition */
2153        tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2154
2155        tcg_temp_free(temp);
2156        tcg_temp_free(temp2);
2157    }
2158    /* write back result */
2159    tcg_gen_extr_i64_i32(rl, rh, t4);
2160    /* Calc SV bit */
2161    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2162    /* Calc AV/SAV bits */
2163    tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2164    tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2165    /* calc SAV */
2166    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2167
2168    tcg_temp_free_i64(t1);
2169    tcg_temp_free_i64(t2);
2170    tcg_temp_free_i64(t3);
2171    tcg_temp_free_i64(t4);
2172}
2173
2174static inline void
2175gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2176              uint32_t up_shift)
2177{
2178    TCGv_i64 t1 = tcg_temp_new_i64();
2179    TCGv_i64 t2 = tcg_temp_new_i64();
2180    TCGv_i64 t3 = tcg_temp_new_i64();
2181    TCGv_i64 t4 = tcg_temp_new_i64();
2182
2183    tcg_gen_ext_i32_i64(t1, arg1);
2184    tcg_gen_ext_i32_i64(t2, arg2);
2185    tcg_gen_ext_i32_i64(t3, arg3);
2186
2187    tcg_gen_mul_i64(t2, t2, t3);
2188    /* if we shift part of the fraction out, we need to round up */
2189    tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2190    tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2191    tcg_gen_sari_i64(t3, t2, up_shift - n);
2192    tcg_gen_add_i64(t3, t3, t4);
2193
2194    gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2195
2196    tcg_temp_free_i64(t1);
2197    tcg_temp_free_i64(t2);
2198    tcg_temp_free_i64(t3);
2199    tcg_temp_free_i64(t4);
2200}
2201
2202static inline void
2203gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2204             TCGv arg3, uint32_t n)
2205{
2206    TCGv_i64 r1 = tcg_temp_new_i64();
2207    TCGv temp = tcg_const_i32(n);
2208
2209    tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2210    gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2211    tcg_gen_extr_i64_i32(rl, rh, r1);
2212
2213    tcg_temp_free_i64(r1);
2214    tcg_temp_free(temp);
2215}
2216
2217static inline void
2218gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2219             TCGv r3, uint32_t n, uint32_t mode)
2220{
2221    TCGv temp = tcg_const_i32(n);
2222    TCGv temp2 = tcg_temp_new();
2223    TCGv_i64 temp64 = tcg_temp_new_i64();
2224    switch (mode) {
2225    case MODE_LL:
2226        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2227        break;
2228    case MODE_LU:
2229        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2230        break;
2231    case MODE_UL:
2232        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2233        break;
2234    case MODE_UU:
2235        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2236        break;
2237    }
2238    tcg_gen_extr_i64_i32(temp, temp2, temp64);
2239    gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2240                   tcg_gen_add_tl, tcg_gen_sub_tl);
2241    tcg_temp_free(temp);
2242    tcg_temp_free(temp2);
2243    tcg_temp_free_i64(temp64);
2244}
2245
2246static inline void
2247gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2248              TCGv r3, uint32_t n, uint32_t mode)
2249{
2250    TCGv temp = tcg_const_i32(n);
2251    TCGv_i64 temp64 = tcg_temp_new_i64();
2252    TCGv_i64 temp64_2 = tcg_temp_new_i64();
2253    TCGv_i64 temp64_3 = tcg_temp_new_i64();
2254    switch (mode) {
2255    case MODE_LL:
2256        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2257        break;
2258    case MODE_LU:
2259        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2260        break;
2261    case MODE_UL:
2262        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2263        break;
2264    case MODE_UU:
2265        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2266        break;
2267    }
2268    tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2269    tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2270    tcg_gen_ext32s_i64(temp64, temp64); /* low */
2271    tcg_gen_sub_i64(temp64, temp64_2, temp64);
2272    tcg_gen_shli_i64(temp64, temp64, 16);
2273
2274    gen_sub64_d(temp64_2, temp64_3, temp64);
2275    /* write back result */
2276    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2277
2278    tcg_temp_free(temp);
2279    tcg_temp_free_i64(temp64);
2280    tcg_temp_free_i64(temp64_2);
2281    tcg_temp_free_i64(temp64_3);
2282}
2283
2284static inline void
2285gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2286{
2287    TCGv temp = tcg_const_i32(n);
2288    TCGv temp2 = tcg_temp_new();
2289    TCGv_i64 temp64 = tcg_temp_new_i64();
2290    switch (mode) {
2291    case MODE_LL:
2292        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2293        break;
2294    case MODE_LU:
2295        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2296        break;
2297    case MODE_UL:
2298        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2299        break;
2300    case MODE_UU:
2301        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2302        break;
2303    }
2304    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2305    tcg_gen_shli_tl(temp, r1, 16);
2306    gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2307
2308    tcg_temp_free(temp);
2309    tcg_temp_free(temp2);
2310    tcg_temp_free_i64(temp64);
2311}
2312
2313static inline void
2314gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2315              TCGv r3, uint32_t n, uint32_t mode)
2316{
2317    TCGv temp = tcg_const_i32(n);
2318    TCGv temp2 = tcg_temp_new();
2319    TCGv temp3 = tcg_temp_new();
2320    TCGv_i64 temp64 = tcg_temp_new_i64();
2321
2322    switch (mode) {
2323    case MODE_LL:
2324        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2325        break;
2326    case MODE_LU:
2327        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2328        break;
2329    case MODE_UL:
2330        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2331        break;
2332    case MODE_UU:
2333        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2334        break;
2335    }
2336    tcg_gen_extr_i64_i32(temp, temp2, temp64);
2337    gen_adds(ret_low, r1_low, temp);
2338    tcg_gen_mov_tl(temp, cpu_PSW_V);
2339    tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2340    gen_subs(ret_high, r1_high, temp2);
2341    /* combine v bits */
2342    tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2343    /* combine av bits */
2344    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2345
2346    tcg_temp_free(temp);
2347    tcg_temp_free(temp2);
2348    tcg_temp_free(temp3);
2349    tcg_temp_free_i64(temp64);
2350}
2351
2352static inline void
2353gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2354               TCGv r3, uint32_t n, uint32_t mode)
2355{
2356    TCGv temp = tcg_const_i32(n);
2357    TCGv_i64 temp64 = tcg_temp_new_i64();
2358    TCGv_i64 temp64_2 = tcg_temp_new_i64();
2359
2360    switch (mode) {
2361    case MODE_LL:
2362        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2363        break;
2364    case MODE_LU:
2365        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2366        break;
2367    case MODE_UL:
2368        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2369        break;
2370    case MODE_UU:
2371        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2372        break;
2373    }
2374    tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2375    tcg_gen_ext32s_i64(temp64, temp64); /* low */
2376    tcg_gen_sub_i64(temp64, temp64_2, temp64);
2377    tcg_gen_shli_i64(temp64, temp64, 16);
2378    tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2379
2380    gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2381    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2382
2383    tcg_temp_free(temp);
2384    tcg_temp_free_i64(temp64);
2385    tcg_temp_free_i64(temp64_2);
2386}
2387
2388static inline void
2389gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2390{
2391    TCGv temp = tcg_const_i32(n);
2392    TCGv temp2 = tcg_temp_new();
2393    TCGv_i64 temp64 = tcg_temp_new_i64();
2394    switch (mode) {
2395    case MODE_LL:
2396        GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2397        break;
2398    case MODE_LU:
2399        GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2400        break;
2401    case MODE_UL:
2402        GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2403        break;
2404    case MODE_UU:
2405        GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2406        break;
2407    }
2408    tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2409    tcg_gen_shli_tl(temp, r1, 16);
2410    gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2411
2412    tcg_temp_free(temp);
2413    tcg_temp_free(temp2);
2414    tcg_temp_free_i64(temp64);
2415}
2416
2417static inline void gen_abs(TCGv ret, TCGv r1)
2418{
2419    TCGv temp = tcg_temp_new();
2420    TCGv t0 = tcg_const_i32(0);
2421
2422    tcg_gen_neg_tl(temp, r1);
2423    tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2424    /* overflow can only happen, if r1 = 0x80000000 */
2425    tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2426    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2427    /* calc SV bit */
2428    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2429    /* Calc AV bit */
2430    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2431    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2432    /* calc SAV bit */
2433    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2434
2435    tcg_temp_free(temp);
2436    tcg_temp_free(t0);
2437}
2438
2439static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2440{
2441    TCGv temp = tcg_temp_new_i32();
2442    TCGv result = tcg_temp_new_i32();
2443
2444    tcg_gen_sub_tl(result, r1, r2);
2445    tcg_gen_sub_tl(temp, r2, r1);
2446    tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2447
2448    /* calc V bit */
2449    tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2450    tcg_gen_xor_tl(temp, result, r2);
2451    tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2452    tcg_gen_xor_tl(temp, r1, r2);
2453    tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2454    /* calc SV bit */
2455    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2456    /* Calc AV bit */
2457    tcg_gen_add_tl(cpu_PSW_AV, result, result);
2458    tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2459    /* calc SAV bit */
2460    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2461    /* write back result */
2462    tcg_gen_mov_tl(ret, result);
2463
2464    tcg_temp_free(temp);
2465    tcg_temp_free(result);
2466}
2467
2468static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2469{
2470    TCGv temp = tcg_const_i32(con);
2471    gen_absdif(ret, r1, temp);
2472    tcg_temp_free(temp);
2473}
2474
2475static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2476{
2477    TCGv temp = tcg_const_i32(con);
2478    gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2479    tcg_temp_free(temp);
2480}
2481
2482static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2483{
2484    TCGv high = tcg_temp_new();
2485    TCGv low = tcg_temp_new();
2486
2487    tcg_gen_muls2_tl(low, high, r1, r2);
2488    tcg_gen_mov_tl(ret, low);
2489    /* calc V bit */
2490    tcg_gen_sari_tl(low, low, 31);
2491    tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2492    tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2493    /* calc SV bit */
2494    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2495    /* Calc AV bit */
2496    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2497    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2498    /* calc SAV bit */
2499    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2500
2501    tcg_temp_free(high);
2502    tcg_temp_free(low);
2503}
2504
2505static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2506{
2507    TCGv temp = tcg_const_i32(con);
2508    gen_mul_i32s(ret, r1, temp);
2509    tcg_temp_free(temp);
2510}
2511
2512static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2513{
2514    tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2515    /* clear V bit */
2516    tcg_gen_movi_tl(cpu_PSW_V, 0);
2517    /* calc SV bit */
2518    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2519    /* Calc AV bit */
2520    tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2521    tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2522    /* calc SAV bit */
2523    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2524}
2525
2526static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2527                                int32_t con)
2528{
2529    TCGv temp = tcg_const_i32(con);
2530    gen_mul_i64s(ret_low, ret_high, r1, temp);
2531    tcg_temp_free(temp);
2532}
2533
2534static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2535{
2536    tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2537    /* clear V bit */
2538    tcg_gen_movi_tl(cpu_PSW_V, 0);
2539    /* calc SV bit */
2540    tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2541    /* Calc AV bit */
2542    tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2543    tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2544    /* calc SAV bit */
2545    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2546}
2547
2548static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2549                                int32_t con)
2550{
2551    TCGv temp = tcg_const_i32(con);
2552    gen_mul_i64u(ret_low, ret_high, r1, temp);
2553    tcg_temp_free(temp);
2554}
2555
2556static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2557{
2558    TCGv temp = tcg_const_i32(con);
2559    gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2560    tcg_temp_free(temp);
2561}
2562
2563static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2564{
2565    TCGv temp = tcg_const_i32(con);
2566    gen_helper_mul_suov(ret, cpu_env, r1, temp);
2567    tcg_temp_free(temp);
2568}
2569/* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2570static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2571{
2572    TCGv temp = tcg_const_i32(con);
2573    gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2574    tcg_temp_free(temp);
2575}
2576
2577static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2578{
2579    TCGv temp = tcg_const_i32(con);
2580    gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2581    tcg_temp_free(temp);
2582}
2583
2584static void
2585gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2586{
2587    TCGv temp = tcg_temp_new();
2588    TCGv_i64 temp_64 = tcg_temp_new_i64();
2589    TCGv_i64 temp2_64 = tcg_temp_new_i64();
2590
2591    if (n == 0) {
2592        if (up_shift == 32) {
2593            tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2594        } else if (up_shift == 16) {
2595            tcg_gen_ext_i32_i64(temp_64, arg1);
2596            tcg_gen_ext_i32_i64(temp2_64, arg2);
2597
2598            tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2599            tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2600            tcg_gen_extr_i64_i32(rl, rh, temp_64);
2601        } else {
2602            tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2603        }
2604        /* reset v bit */
2605        tcg_gen_movi_tl(cpu_PSW_V, 0);
2606    } else { /* n is expected to be 1 */
2607        tcg_gen_ext_i32_i64(temp_64, arg1);
2608        tcg_gen_ext_i32_i64(temp2_64, arg2);
2609
2610        tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2611
2612        if (up_shift == 0) {
2613            tcg_gen_shli_i64(temp_64, temp_64, 1);
2614        } else {
2615            tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2616        }
2617        tcg_gen_extr_i64_i32(rl, rh, temp_64);
2618        /* overflow only occurs if r1 = r2 = 0x8000 */
2619        if (up_shift == 0) {/* result is 64 bit */
2620            tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2621                                0x80000000);
2622        } else { /* result is 32 bit */
2623            tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2624                                0x80000000);
2625        }
2626        tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2627        /* calc sv overflow bit */
2628        tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2629    }
2630    /* calc av overflow bit */
2631    if (up_shift == 0) {
2632        tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2633        tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2634    } else {
2635        tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2636        tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2637    }
2638    /* calc sav overflow bit */
2639    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2640    tcg_temp_free(temp);
2641    tcg_temp_free_i64(temp_64);
2642    tcg_temp_free_i64(temp2_64);
2643}
2644
2645static void
2646gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2647{
2648    TCGv temp = tcg_temp_new();
2649    if (n == 0) {
2650        tcg_gen_mul_tl(ret, arg1, arg2);
2651    } else { /* n is expected to be 1 */
2652        tcg_gen_mul_tl(ret, arg1, arg2);
2653        tcg_gen_shli_tl(ret, ret, 1);
2654        /* catch special case r1 = r2 = 0x8000 */
2655        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2656        tcg_gen_sub_tl(ret, ret, temp);
2657    }
2658    /* reset v bit */
2659    tcg_gen_movi_tl(cpu_PSW_V, 0);
2660    /* calc av overflow bit */
2661    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2662    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2663    /* calc sav overflow bit */
2664    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2665
2666    tcg_temp_free(temp);
2667}
2668
2669static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2670{
2671    TCGv temp = tcg_temp_new();
2672    if (n == 0) {
2673        tcg_gen_mul_tl(ret, arg1, arg2);
2674        tcg_gen_addi_tl(ret, ret, 0x8000);
2675    } else {
2676        tcg_gen_mul_tl(ret, arg1, arg2);
2677        tcg_gen_shli_tl(ret, ret, 1);
2678        tcg_gen_addi_tl(ret, ret, 0x8000);
2679        /* catch special case r1 = r2 = 0x8000 */
2680        tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2681        tcg_gen_muli_tl(temp, temp, 0x8001);
2682        tcg_gen_sub_tl(ret, ret, temp);
2683    }
2684    /* reset v bit */
2685    tcg_gen_movi_tl(cpu_PSW_V, 0);
2686    /* calc av overflow bit */
2687    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2688    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2689    /* calc sav overflow bit */
2690    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2691    /* cut halfword off */
2692    tcg_gen_andi_tl(ret, ret, 0xffff0000);
2693
2694    tcg_temp_free(temp);
2695}
2696
2697static inline void
2698gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2699             TCGv r3)
2700{
2701    TCGv_i64 temp64 = tcg_temp_new_i64();
2702    tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2703    gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2704    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2705    tcg_temp_free_i64(temp64);
2706}
2707
2708static inline void
2709gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2710              int32_t con)
2711{
2712    TCGv temp = tcg_const_i32(con);
2713    gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2714    tcg_temp_free(temp);
2715}
2716
2717static inline void
2718gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2719             TCGv r3)
2720{
2721    TCGv_i64 temp64 = tcg_temp_new_i64();
2722    tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2723    gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2724    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2725    tcg_temp_free_i64(temp64);
2726}
2727
2728static inline void
2729gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2730               int32_t con)
2731{
2732    TCGv temp = tcg_const_i32(con);
2733    gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2734    tcg_temp_free(temp);
2735}
2736
2737static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2738{
2739    TCGv temp = tcg_const_i32(con);
2740    gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2741    tcg_temp_free(temp);
2742}
2743
2744static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2745{
2746    TCGv temp = tcg_const_i32(con);
2747    gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2748    tcg_temp_free(temp);
2749}
2750
2751static inline void
2752gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2753             TCGv r3)
2754{
2755    TCGv_i64 temp64 = tcg_temp_new_i64();
2756    tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2757    gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2758    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2759    tcg_temp_free_i64(temp64);
2760}
2761
2762static inline void
2763gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2764              int32_t con)
2765{
2766    TCGv temp = tcg_const_i32(con);
2767    gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2768    tcg_temp_free(temp);
2769}
2770
2771static inline void
2772gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2773             TCGv r3)
2774{
2775    TCGv_i64 temp64 = tcg_temp_new_i64();
2776    tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2777    gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2778    tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2779    tcg_temp_free_i64(temp64);
2780}
2781
2782static inline void
2783gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2784               int32_t con)
2785{
2786    TCGv temp = tcg_const_i32(con);
2787    gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2788    tcg_temp_free(temp);
2789}
2790
2791static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2792{
2793    TCGv sat_neg = tcg_const_i32(low);
2794    TCGv temp = tcg_const_i32(up);
2795
2796    /* sat_neg = (arg < low ) ? low : arg; */
2797    tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2798
2799    /* ret = (sat_neg > up ) ? up  : sat_neg; */
2800    tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2801
2802    tcg_temp_free(sat_neg);
2803    tcg_temp_free(temp);
2804}
2805
2806static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2807{
2808    TCGv temp = tcg_const_i32(up);
2809    /* sat_neg = (arg > up ) ? up : arg; */
2810    tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2811    tcg_temp_free(temp);
2812}
2813
2814static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2815{
2816    if (shift_count == -32) {
2817        tcg_gen_movi_tl(ret, 0);
2818    } else if (shift_count >= 0) {
2819        tcg_gen_shli_tl(ret, r1, shift_count);
2820    } else {
2821        tcg_gen_shri_tl(ret, r1, -shift_count);
2822    }
2823}
2824
2825static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2826{
2827    TCGv temp_low, temp_high;
2828
2829    if (shiftcount == -16) {
2830        tcg_gen_movi_tl(ret, 0);
2831    } else {
2832        temp_high = tcg_temp_new();
2833        temp_low = tcg_temp_new();
2834
2835        tcg_gen_andi_tl(temp_low, r1, 0xffff);
2836        tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2837        gen_shi(temp_low, temp_low, shiftcount);
2838        gen_shi(ret, temp_high, shiftcount);
2839        tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2840
2841        tcg_temp_free(temp_low);
2842        tcg_temp_free(temp_high);
2843    }
2844}
2845
2846static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2847{
2848    uint32_t msk, msk_start;
2849    TCGv temp = tcg_temp_new();
2850    TCGv temp2 = tcg_temp_new();
2851    TCGv t_0 = tcg_const_i32(0);
2852
2853    if (shift_count == 0) {
2854        /* Clear PSW.C and PSW.V */
2855        tcg_gen_movi_tl(cpu_PSW_C, 0);
2856        tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2857        tcg_gen_mov_tl(ret, r1);
2858    } else if (shift_count == -32) {
2859        /* set PSW.C */
2860        tcg_gen_mov_tl(cpu_PSW_C, r1);
2861        /* fill ret completly with sign bit */
2862        tcg_gen_sari_tl(ret, r1, 31);
2863        /* clear PSW.V */
2864        tcg_gen_movi_tl(cpu_PSW_V, 0);
2865    } else if (shift_count > 0) {
2866        TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2867        TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2868
2869        /* calc carry */
2870        msk_start = 32 - shift_count;
2871        msk = ((1 << shift_count) - 1) << msk_start;
2872        tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2873        /* calc v/sv bits */
2874        tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2875        tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2876        tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2877        tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2878        /* calc sv */
2879        tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2880        /* do shift */
2881        tcg_gen_shli_tl(ret, r1, shift_count);
2882
2883        tcg_temp_free(t_max);
2884        tcg_temp_free(t_min);
2885    } else {
2886        /* clear PSW.V */
2887        tcg_gen_movi_tl(cpu_PSW_V, 0);
2888        /* calc carry */
2889        msk = (1 << -shift_count) - 1;
2890        tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2891        /* do shift */
2892        tcg_gen_sari_tl(ret, r1, -shift_count);
2893    }
2894    /* calc av overflow bit */
2895    tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2896    tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2897    /* calc sav overflow bit */
2898    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2899
2900    tcg_temp_free(temp);
2901    tcg_temp_free(temp2);
2902    tcg_temp_free(t_0);
2903}
2904
2905static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2906{
2907    gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2908}
2909
2910static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2911{
2912    TCGv temp = tcg_const_i32(con);
2913    gen_shas(ret, r1, temp);
2914    tcg_temp_free(temp);
2915}
2916
2917static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2918{
2919    TCGv low, high;
2920
2921    if (shift_count == 0) {
2922        tcg_gen_mov_tl(ret, r1);
2923    } else if (shift_count > 0) {
2924        low = tcg_temp_new();
2925        high = tcg_temp_new();
2926
2927        tcg_gen_andi_tl(high, r1, 0xffff0000);
2928        tcg_gen_shli_tl(low, r1, shift_count);
2929        tcg_gen_shli_tl(ret, high, shift_count);
2930        tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2931
2932        tcg_temp_free(low);
2933        tcg_temp_free(high);
2934    } else {
2935        low = tcg_temp_new();
2936        high = tcg_temp_new();
2937
2938        tcg_gen_ext16s_tl(low, r1);
2939        tcg_gen_sari_tl(low, low, -shift_count);
2940        tcg_gen_sari_tl(ret, r1, -shift_count);
2941        tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2942
2943        tcg_temp_free(low);
2944        tcg_temp_free(high);
2945    }
2946
2947}
2948
2949/* ret = {ret[30:0], (r1 cond r2)}; */
2950static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2951{
2952    TCGv temp = tcg_temp_new();
2953    TCGv temp2 = tcg_temp_new();
2954
2955    tcg_gen_shli_tl(temp, ret, 1);
2956    tcg_gen_setcond_tl(cond, temp2, r1, r2);
2957    tcg_gen_or_tl(ret, temp, temp2);
2958
2959    tcg_temp_free(temp);
2960    tcg_temp_free(temp2);
2961}
2962
2963static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2964{
2965    TCGv temp = tcg_const_i32(con);
2966    gen_sh_cond(cond, ret, r1, temp);
2967    tcg_temp_free(temp);
2968}
2969
2970static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2971{
2972    gen_helper_add_ssov(ret, cpu_env, r1, r2);
2973}
2974
2975static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2976{
2977    TCGv temp = tcg_const_i32(con);
2978    gen_helper_add_ssov(ret, cpu_env, r1, temp);
2979    tcg_temp_free(temp);
2980}
2981
2982static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2983{
2984    TCGv temp = tcg_const_i32(con);
2985    gen_helper_add_suov(ret, cpu_env, r1, temp);
2986    tcg_temp_free(temp);
2987}
2988
2989static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2990{
2991    gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2992}
2993
2994static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2995{
2996    gen_helper_sub_suov(ret, cpu_env, r1, r2);
2997}
2998
2999static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
3000                               int pos1, int pos2,
3001                               void(*op1)(TCGv, TCGv, TCGv),
3002                               void(*op2)(TCGv, TCGv, TCGv))
3003{
3004    TCGv temp1, temp2;
3005
3006    temp1 = tcg_temp_new();
3007    temp2 = tcg_temp_new();
3008
3009    tcg_gen_shri_tl(temp2, r2, pos2);
3010    tcg_gen_shri_tl(temp1, r1, pos1);
3011
3012    (*op1)(temp1, temp1, temp2);
3013    (*op2)(temp1 , ret, temp1);
3014
3015    tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3016
3017    tcg_temp_free(temp1);
3018    tcg_temp_free(temp2);
3019}
3020
3021/* ret = r1[pos1] op1 r2[pos2]; */
3022static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3023                               int pos1, int pos2,
3024                               void(*op1)(TCGv, TCGv, TCGv))
3025{
3026    TCGv temp1, temp2;
3027
3028    temp1 = tcg_temp_new();
3029    temp2 = tcg_temp_new();
3030
3031    tcg_gen_shri_tl(temp2, r2, pos2);
3032    tcg_gen_shri_tl(temp1, r1, pos1);
3033
3034    (*op1)(ret, temp1, temp2);
3035
3036    tcg_gen_andi_tl(ret, ret, 0x1);
3037
3038    tcg_temp_free(temp1);
3039    tcg_temp_free(temp2);
3040}
3041
3042static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3043                                         void(*op)(TCGv, TCGv, TCGv))
3044{
3045    TCGv temp = tcg_temp_new();
3046    TCGv temp2 = tcg_temp_new();
3047    /* temp = (arg1 cond arg2 )*/
3048    tcg_gen_setcond_tl(cond, temp, r1, r2);
3049    /* temp2 = ret[0]*/
3050    tcg_gen_andi_tl(temp2, ret, 0x1);
3051    /* temp = temp insn temp2 */
3052    (*op)(temp, temp, temp2);
3053    /* ret = {ret[31:1], temp} */
3054    tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3055
3056    tcg_temp_free(temp);
3057    tcg_temp_free(temp2);
3058}
3059
3060static inline void
3061gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3062                       void(*op)(TCGv, TCGv, TCGv))
3063{
3064    TCGv temp = tcg_const_i32(con);
3065    gen_accumulating_cond(cond, ret, r1, temp, op);
3066    tcg_temp_free(temp);
3067}
3068
3069/* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3070static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3071{
3072    tcg_gen_setcond_tl(cond, ret, r1, r2);
3073    tcg_gen_neg_tl(ret, ret);
3074}
3075
3076static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3077{
3078    TCGv b0 = tcg_temp_new();
3079    TCGv b1 = tcg_temp_new();
3080    TCGv b2 = tcg_temp_new();
3081    TCGv b3 = tcg_temp_new();
3082
3083    /* byte 0 */
3084    tcg_gen_andi_tl(b0, r1, 0xff);
3085    tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3086
3087    /* byte 1 */
3088    tcg_gen_andi_tl(b1, r1, 0xff00);
3089    tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3090
3091    /* byte 2 */
3092    tcg_gen_andi_tl(b2, r1, 0xff0000);
3093    tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3094
3095    /* byte 3 */
3096    tcg_gen_andi_tl(b3, r1, 0xff000000);
3097    tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3098
3099    /* combine them */
3100    tcg_gen_or_tl(ret, b0, b1);
3101    tcg_gen_or_tl(ret, ret, b2);
3102    tcg_gen_or_tl(ret, ret, b3);
3103
3104    tcg_temp_free(b0);
3105    tcg_temp_free(b1);
3106    tcg_temp_free(b2);
3107    tcg_temp_free(b3);
3108}
3109
3110static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3111{
3112    TCGv h0 = tcg_temp_new();
3113    TCGv h1 = tcg_temp_new();
3114
3115    /* halfword 0 */
3116    tcg_gen_andi_tl(h0, r1, 0xffff);
3117    tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3118
3119    /* halfword 1 */
3120    tcg_gen_andi_tl(h1, r1, 0xffff0000);
3121    tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3122
3123    /* combine them */
3124    tcg_gen_or_tl(ret, h0, h1);
3125
3126    tcg_temp_free(h0);
3127    tcg_temp_free(h1);
3128}
3129/* mask = ((1 << width) -1) << pos;
3130   ret = (r1 & ~mask) | (r2 << pos) & mask); */
3131static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3132{
3133    TCGv mask = tcg_temp_new();
3134    TCGv temp = tcg_temp_new();
3135    TCGv temp2 = tcg_temp_new();
3136
3137    tcg_gen_movi_tl(mask, 1);
3138    tcg_gen_shl_tl(mask, mask, width);
3139    tcg_gen_subi_tl(mask, mask, 1);
3140    tcg_gen_shl_tl(mask, mask, pos);
3141
3142    tcg_gen_shl_tl(temp, r2, pos);
3143    tcg_gen_and_tl(temp, temp, mask);
3144    tcg_gen_andc_tl(temp2, r1, mask);
3145    tcg_gen_or_tl(ret, temp, temp2);
3146
3147    tcg_temp_free(mask);
3148    tcg_temp_free(temp);
3149    tcg_temp_free(temp2);
3150}
3151
3152static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3153{
3154    TCGv_i64 temp = tcg_temp_new_i64();
3155
3156    gen_helper_bsplit(temp, r1);
3157    tcg_gen_extr_i64_i32(rl, rh, temp);
3158
3159    tcg_temp_free_i64(temp);
3160}
3161
3162static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3163{
3164    TCGv_i64 temp = tcg_temp_new_i64();
3165
3166    gen_helper_unpack(temp, r1);
3167    tcg_gen_extr_i64_i32(rl, rh, temp);
3168
3169    tcg_temp_free_i64(temp);
3170}
3171
3172static inline void
3173gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3174{
3175    TCGv_i64 ret = tcg_temp_new_i64();
3176
3177    if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3178        gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3179    } else {
3180        gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3181    }
3182    tcg_gen_extr_i64_i32(rl, rh, ret);
3183
3184    tcg_temp_free_i64(ret);
3185}
3186
3187static inline void
3188gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3189{
3190    TCGv_i64 ret = tcg_temp_new_i64();
3191
3192    if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3193        gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3194    } else {
3195        gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3196    }
3197    tcg_gen_extr_i64_i32(rl, rh, ret);
3198
3199    tcg_temp_free_i64(ret);
3200}
3201
3202static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3203{
3204    TCGv temp = tcg_temp_new();
3205    /* calc AV bit */
3206    tcg_gen_add_tl(temp, arg_low, arg_low);
3207    tcg_gen_xor_tl(temp, temp, arg_low);
3208    tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3209    tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3210    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3211    /* calc SAV bit */
3212    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3213    tcg_gen_movi_tl(cpu_PSW_V, 0);
3214    tcg_temp_free(temp);
3215}
3216
3217static void gen_calc_usb_mulr_h(TCGv arg)
3218{
3219    TCGv temp = tcg_temp_new();
3220    /* calc AV bit */
3221    tcg_gen_add_tl(temp, arg, arg);
3222    tcg_gen_xor_tl(temp, temp, arg);
3223    tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3224    tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3225    /* calc SAV bit */
3226    tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3227    /* clear V bit */
3228    tcg_gen_movi_tl(cpu_PSW_V, 0);
3229    tcg_temp_free(temp);
3230}
3231
3232/* helpers for generating program flow micro-ops */
3233
3234static inline void gen_save_pc(target_ulong pc)
3235{
3236    tcg_gen_movi_tl(cpu_PC, pc);
3237}
3238
3239static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3240{
3241    TranslationBlock *tb;
3242    tb = ctx->tb;
3243    if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3244        likely(!ctx->singlestep_enabled)) {
3245        tcg_gen_goto_tb(n);
3246        gen_save_pc(dest);
3247        tcg_gen_exit_tb((uintptr_t)tb + n);
3248    } else {
3249        gen_save_pc(dest);
3250        if (ctx->singlestep_enabled) {
3251            /* raise exception debug */
3252        }
3253        tcg_gen_exit_tb(0);
3254    }
3255}
3256
3257static void generate_trap(DisasContext *ctx, int class, int tin)
3258{
3259    TCGv_i32 classtemp = tcg_const_i32(class);
3260    TCGv_i32 tintemp = tcg_const_i32(tin);
3261
3262    gen_save_pc(ctx->pc);
3263    gen_helper_raise_exception_sync(cpu_env, classtemp, tintemp);
3264    ctx->bstate = BS_EXCP;
3265
3266    tcg_temp_free(classtemp);
3267    tcg_temp_free(tintemp);
3268}
3269
3270static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3271                                   TCGv r2, int16_t address)
3272{
3273    TCGLabel *jumpLabel = gen_new_label();
3274    tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3275
3276    gen_goto_tb(ctx, 1, ctx->next_pc);
3277
3278    gen_set_label(jumpLabel);
3279    gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3280}
3281
3282static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3283                                    int r2, int16_t address)
3284{
3285    TCGv temp = tcg_const_i32(r2);
3286    gen_branch_cond(ctx, cond, r1, temp, address);
3287    tcg_temp_free(temp);
3288}
3289
3290static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3291{
3292    TCGLabel *l1 = gen_new_label();
3293
3294    tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3295    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3296    gen_goto_tb(ctx, 1, ctx->pc + offset);
3297    gen_set_label(l1);
3298    gen_goto_tb(ctx, 0, ctx->next_pc);
3299}
3300
3301static void gen_fcall_save_ctx(DisasContext *ctx)
3302{
3303    TCGv temp = tcg_temp_new();
3304
3305    tcg_gen_addi_tl(temp, cpu_gpr_a[10], -4);
3306    tcg_gen_qemu_st_tl(cpu_gpr_a[11], temp, ctx->mem_idx, MO_LESL);
3307    tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3308    tcg_gen_mov_tl(cpu_gpr_a[10], temp);
3309
3310    tcg_temp_free(temp);
3311}
3312
3313static void gen_fret(DisasContext *ctx)
3314{
3315    TCGv temp = tcg_temp_new();
3316
3317    tcg_gen_andi_tl(temp, cpu_gpr_a[11], ~0x1);
3318    tcg_gen_qemu_ld_tl(cpu_gpr_a[11], cpu_gpr_a[10], ctx->mem_idx, MO_LESL);
3319    tcg_gen_addi_tl(cpu_gpr_a[10], cpu_gpr_a[10], 4);
3320    tcg_gen_mov_tl(cpu_PC, temp);
3321    tcg_gen_exit_tb(0);
3322    ctx->bstate = BS_BRANCH;
3323
3324    tcg_temp_free(temp);
3325}
3326
3327static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3328                               int r2 , int32_t constant , int32_t offset)
3329{
3330    TCGv temp, temp2;
3331    int n;
3332
3333    switch (opc) {
3334/* SB-format jumps */
3335    case OPC1_16_SB_J:
3336    case OPC1_32_B_J:
3337        gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3338        break;
3339    case OPC1_32_B_CALL:
3340    case OPC1_16_SB_CALL:
3341        gen_helper_1arg(call, ctx->next_pc);
3342        gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3343        break;
3344    case OPC1_16_SB_JZ:
3345        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3346        break;
3347    case OPC1_16_SB_JNZ:
3348        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3349        break;
3350/* SBC-format jumps */
3351    case OPC1_16_SBC_JEQ:
3352        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3353        break;
3354    case OPC1_16_SBC_JNE:
3355        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3356        break;
3357/* SBRN-format jumps */
3358    case OPC1_16_SBRN_JZ_T:
3359        temp = tcg_temp_new();
3360        tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3361        gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3362        tcg_temp_free(temp);
3363        break;
3364    case OPC1_16_SBRN_JNZ_T:
3365        temp = tcg_temp_new();
3366        tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3367        gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3368        tcg_temp_free(temp);
3369        break;
3370/* SBR-format jumps */
3371    case OPC1_16_SBR_JEQ:
3372        gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3373                        offset);
3374        break;
3375    case OPC1_16_SBR_JNE:
3376        gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3377                        offset);
3378        break;
3379    case OPC1_16_SBR_JNZ:
3380        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3381        break;
3382    case OPC1_16_SBR_JNZ_A:
3383        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3384        break;
3385    case OPC1_16_SBR_JGEZ:
3386        gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3387        break;
3388    case OPC1_16_SBR_JGTZ:
3389        gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3390        break;
3391    case OPC1_16_SBR_JLEZ:
3392        gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3393        break;
3394    case OPC1_16_SBR_JLTZ:
3395        gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3396        break;
3397    case OPC1_16_SBR_JZ:
3398        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3399        break;
3400    case OPC1_16_SBR_JZ_A:
3401        gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3402        break;
3403    case OPC1_16_SBR_LOOP:
3404        gen_loop(ctx, r1, offset * 2 - 32);
3405        break;
3406/* SR-format jumps */
3407    case OPC1_16_SR_JI:
3408        tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3409        tcg_gen_exit_tb(0);
3410        break;
3411    case OPC2_32_SYS_RET:
3412    case OPC2_16_SR_RET:
3413        gen_helper_ret(cpu_env);
3414        tcg_gen_exit_tb(0);
3415        break;
3416/* B-format */
3417    case OPC1_32_B_CALLA:
3418        gen_helper_1arg(call, ctx->next_pc);
3419        gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3420        break;
3421    case OPC1_32_B_FCALL:
3422        gen_fcall_save_ctx(ctx);
3423        gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3424        break;
3425    case OPC1_32_B_FCALLA:
3426        gen_fcall_save_ctx(ctx);
3427        gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3428        break;
3429    case OPC1_32_B_JLA:
3430        tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3431        /* fall through */
3432    case OPC1_32_B_JA:
3433        gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3434        break;
3435    case OPC1_32_B_JL:
3436        tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3437        gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3438        break;
3439/* BOL format */
3440    case OPCM_32_BRC_EQ_NEQ:
3441         if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3442            gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3443         } else {
3444            gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3445         }
3446         break;
3447    case OPCM_32_BRC_GE:
3448         if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3449            gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3450         } else {
3451            constant = MASK_OP_BRC_CONST4(ctx->opcode);
3452            gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3453                             offset);
3454         }
3455         break;
3456    case OPCM_32_BRC_JLT:
3457         if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3458            gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3459         } else {
3460            constant = MASK_OP_BRC_CONST4(ctx->opcode);
3461            gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3462                             offset);
3463         }
3464         break;
3465    case OPCM_32_BRC_JNE:
3466        temp = tcg_temp_new();
3467        if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3468            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3469            /* subi is unconditional */
3470            tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3471            gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3472        } else {
3473            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3474            /* addi is unconditional */
3475            tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3476            gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3477        }
3478        tcg_temp_free(temp);
3479        break;
3480/* BRN format */
3481    case OPCM_32_BRN_JTT:
3482        n = MASK_OP_BRN_N(ctx->opcode);
3483
3484        temp = tcg_temp_new();
3485        tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3486
3487        if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3488            gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3489        } else {
3490            gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3491        }
3492        tcg_temp_free(temp);
3493        break;
3494/* BRR Format */
3495    case OPCM_32_BRR_EQ_NEQ:
3496        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3497            gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3498                            offset);
3499        } else {
3500            gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3501                            offset);
3502        }
3503        break;
3504    case OPCM_32_BRR_ADDR_EQ_NEQ:
3505        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3506            gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3507                            offset);
3508        } else {
3509            gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3510                            offset);
3511        }
3512        break;
3513    case OPCM_32_BRR_GE:
3514        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3515            gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3516                            offset);
3517        } else {
3518            gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3519                            offset);
3520        }
3521        break;
3522    case OPCM_32_BRR_JLT:
3523        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3524            gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3525                            offset);
3526        } else {
3527            gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3528                            offset);
3529        }
3530        break;
3531    case OPCM_32_BRR_LOOP:
3532        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3533            gen_loop(ctx, r2, offset * 2);
3534        } else {
3535            /* OPC2_32_BRR_LOOPU */
3536            gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3537        }
3538        break;
3539    case OPCM_32_BRR_JNE:
3540        temp = tcg_temp_new();
3541        temp2 = tcg_temp_new();
3542        if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3543            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3544            /* also save r2, in case of r1 == r2, so r2 is not decremented */
3545            tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3546            /* subi is unconditional */
3547            tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3548            gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3549        } else {
3550            tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3551            /* also save r2, in case of r1 == r2, so r2 is not decremented */
3552            tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3553            /* addi is unconditional */
3554            tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3555            gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3556        }
3557        tcg_temp_free(temp);
3558        tcg_temp_free(temp2);
3559        break;
3560    case OPCM_32_BRR_JNZ:
3561        if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3562            gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3563        } else {
3564            gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3565        }
3566        break;
3567    default:
3568        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3569    }
3570    ctx->bstate = BS_BRANCH;
3571}
3572
3573
3574/*
3575 * Functions for decoding instructions
3576 */
3577
3578static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3579{
3580    int r1;
3581    int32_t const4;
3582    TCGv temp, temp2;
3583
3584    r1 = MASK_OP_SRC_S1D(ctx->opcode);
3585    const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3586
3587    switch (op1) {
3588    case OPC1_16_SRC_ADD:
3589        gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3590        break;
3591    case OPC1_16_SRC_ADD_A15:
3592        gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3593        break;
3594    case OPC1_16_SRC_ADD_15A:
3595        gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3596        break;
3597    case OPC1_16_SRC_ADD_A:
3598        tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3599        break;
3600    case OPC1_16_SRC_CADD:
3601        gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3602                      cpu_gpr_d[15]);
3603        break;
3604    case OPC1_16_SRC_CADDN:
3605        gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3606                      cpu_gpr_d[15]);
3607        break;
3608    case OPC1_16_SRC_CMOV:
3609        temp = tcg_const_tl(0);
3610        temp2 = tcg_const_tl(const4);
3611        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3612                           temp2, cpu_gpr_d[r1]);
3613        tcg_temp_free(temp);
3614        tcg_temp_free(temp2);
3615        break;
3616    case OPC1_16_SRC_CMOVN:
3617        temp = tcg_const_tl(0);
3618        temp2 = tcg_const_tl(const4);
3619        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3620                           temp2, cpu_gpr_d[r1]);
3621        tcg_temp_free(temp);
3622        tcg_temp_free(temp2);
3623        break;
3624    case OPC1_16_SRC_EQ:
3625        tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3626                            const4);
3627        break;
3628    case OPC1_16_SRC_LT:
3629        tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3630                            const4);
3631        break;
3632    case OPC1_16_SRC_MOV:
3633        tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3634        break;
3635    case OPC1_16_SRC_MOV_A:
3636        const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3637        tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3638        break;
3639    case OPC1_16_SRC_MOV_E:
3640        if (tricore_feature(env, TRICORE_FEATURE_16)) {
3641            tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3642            tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3643        } else {
3644            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3645        }
3646        break;
3647    case OPC1_16_SRC_SH:
3648        gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3649        break;
3650    case OPC1_16_SRC_SHA:
3651        gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3652        break;
3653    default:
3654        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3655    }
3656}
3657
3658static void decode_srr_opc(DisasContext *ctx, int op1)
3659{
3660    int r1, r2;
3661    TCGv temp;
3662
3663    r1 = MASK_OP_SRR_S1D(ctx->opcode);
3664    r2 = MASK_OP_SRR_S2(ctx->opcode);
3665
3666    switch (op1) {
3667    case OPC1_16_SRR_ADD:
3668        gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3669        break;
3670    case OPC1_16_SRR_ADD_A15:
3671        gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3672        break;
3673    case OPC1_16_SRR_ADD_15A:
3674        gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3675        break;
3676    case OPC1_16_SRR_ADD_A:
3677        tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3678        break;
3679    case OPC1_16_SRR_ADDS:
3680        gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3681        break;
3682    case OPC1_16_SRR_AND:
3683        tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3684        break;
3685    case OPC1_16_SRR_CMOV:
3686        temp = tcg_const_tl(0);
3687        tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3688                           cpu_gpr_d[r2], cpu_gpr_d[r1]);
3689        tcg_temp_free(temp);
3690        break;
3691    case OPC1_16_SRR_CMOVN:
3692        temp = tcg_const_tl(0);
3693        tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3694                           cpu_gpr_d[r2], cpu_gpr_d[r1]);
3695        tcg_temp_free(temp);
3696        break;
3697    case OPC1_16_SRR_EQ:
3698        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3699                           cpu_gpr_d[r2]);
3700        break;
3701    case OPC1_16_SRR_LT:
3702        tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3703                           cpu_gpr_d[r2]);
3704        break;
3705    case OPC1_16_SRR_MOV:
3706        tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3707        break;
3708    case OPC1_16_SRR_MOV_A:
3709        tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3710        break;
3711    case OPC1_16_SRR_MOV_AA:
3712        tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3713        break;
3714    case OPC1_16_SRR_MOV_D:
3715        tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3716        break;
3717    case OPC1_16_SRR_MUL:
3718        gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3719        break;
3720    case OPC1_16_SRR_OR:
3721        tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3722        break;
3723    case OPC1_16_SRR_SUB:
3724        gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3725        break;
3726    case OPC1_16_SRR_SUB_A15B:
3727        gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3728        break;
3729    case OPC1_16_SRR_SUB_15AB:
3730        gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3731        break;
3732    case OPC1_16_SRR_SUBS:
3733        gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3734        break;
3735    case OPC1_16_SRR_XOR:
3736        tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3737        break;
3738    default:
3739        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3740    }
3741}
3742
3743static void decode_ssr_opc(DisasContext *ctx, int op1)
3744{
3745    int r1, r2;
3746
3747    r1 = MASK_OP_SSR_S1(ctx->opcode);
3748    r2 = MASK_OP_SSR_S2(ctx->opcode);
3749
3750    switch (op1) {
3751    case OPC1_16_SSR_ST_A:
3752        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3753        break;
3754    case OPC1_16_SSR_ST_A_POSTINC:
3755        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3756        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3757        break;
3758    case OPC1_16_SSR_ST_B:
3759        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3760        break;
3761    case OPC1_16_SSR_ST_B_POSTINC:
3762        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3763        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3764        break;
3765    case OPC1_16_SSR_ST_H:
3766        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3767        break;
3768    case OPC1_16_SSR_ST_H_POSTINC:
3769        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3770        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3771        break;
3772    case OPC1_16_SSR_ST_W:
3773        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3774        break;
3775    case OPC1_16_SSR_ST_W_POSTINC:
3776        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3777        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3778        break;
3779    default:
3780        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3781    }
3782}
3783
3784static void decode_sc_opc(DisasContext *ctx, int op1)
3785{
3786    int32_t const16;
3787
3788    const16 = MASK_OP_SC_CONST8(ctx->opcode);
3789
3790    switch (op1) {
3791    case OPC1_16_SC_AND:
3792        tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3793        break;
3794    case OPC1_16_SC_BISR:
3795        gen_helper_1arg(bisr, const16 & 0xff);
3796        break;
3797    case OPC1_16_SC_LD_A:
3798        gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3799        break;
3800    case OPC1_16_SC_LD_W:
3801        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3802        break;
3803    case OPC1_16_SC_MOV:
3804        tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3805        break;
3806    case OPC1_16_SC_OR:
3807        tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3808        break;
3809    case OPC1_16_SC_ST_A:
3810        gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3811        break;
3812    case OPC1_16_SC_ST_W:
3813        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3814        break;
3815    case OPC1_16_SC_SUB_A:
3816        tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3817        break;
3818    default:
3819        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3820    }
3821}
3822
3823static void decode_slr_opc(DisasContext *ctx, int op1)
3824{
3825    int r1, r2;
3826
3827    r1 = MASK_OP_SLR_D(ctx->opcode);
3828    r2 = MASK_OP_SLR_S2(ctx->opcode);
3829
3830    switch (op1) {
3831/* SLR-format */
3832    case OPC1_16_SLR_LD_A:
3833        tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3834        break;
3835    case OPC1_16_SLR_LD_A_POSTINC:
3836        tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3837        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3838        break;
3839    case OPC1_16_SLR_LD_BU:
3840        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3841        break;
3842    case OPC1_16_SLR_LD_BU_POSTINC:
3843        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3844        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3845        break;
3846    case OPC1_16_SLR_LD_H:
3847        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3848        break;
3849    case OPC1_16_SLR_LD_H_POSTINC:
3850        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3851        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3852        break;
3853    case OPC1_16_SLR_LD_W:
3854        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3855        break;
3856    case OPC1_16_SLR_LD_W_POSTINC:
3857        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3858        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3859        break;
3860    default:
3861        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3862    }
3863}
3864
3865static void decode_sro_opc(DisasContext *ctx, int op1)
3866{
3867    int r2;
3868    int32_t address;
3869
3870    r2 = MASK_OP_SRO_S2(ctx->opcode);
3871    address = MASK_OP_SRO_OFF4(ctx->opcode);
3872
3873/* SRO-format */
3874    switch (op1) {
3875    case OPC1_16_SRO_LD_A:
3876        gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3877        break;
3878    case OPC1_16_SRO_LD_BU:
3879        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3880        break;
3881    case OPC1_16_SRO_LD_H:
3882        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3883        break;
3884    case OPC1_16_SRO_LD_W:
3885        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3886        break;
3887    case OPC1_16_SRO_ST_A:
3888        gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3889        break;
3890    case OPC1_16_SRO_ST_B:
3891        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3892        break;
3893    case OPC1_16_SRO_ST_H:
3894        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3895        break;
3896    case OPC1_16_SRO_ST_W:
3897        gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3898        break;
3899    default:
3900        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3901    }
3902}
3903
3904static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3905{
3906    uint32_t op2;
3907    op2 = MASK_OP_SR_OP2(ctx->opcode);
3908
3909    switch (op2) {
3910    case OPC2_16_SR_NOP:
3911        break;
3912    case OPC2_16_SR_RET:
3913        gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3914        break;
3915    case OPC2_16_SR_RFE:
3916        gen_helper_rfe(cpu_env);
3917        tcg_gen_exit_tb(0);
3918        ctx->bstate = BS_BRANCH;
3919        break;
3920    case OPC2_16_SR_DEBUG:
3921        /* raise EXCP_DEBUG */
3922        break;
3923    case OPC2_16_SR_FRET:
3924        gen_fret(ctx);
3925        break;
3926    default:
3927        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3928    }
3929}
3930
3931static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3932{
3933    uint32_t op2;
3934    uint32_t r1;
3935    TCGv temp;
3936
3937    r1 = MASK_OP_SR_S1D(ctx->opcode);
3938    op2 = MASK_OP_SR_OP2(ctx->opcode);
3939
3940    switch (op2) {
3941    case OPC2_16_SR_RSUB:
3942        /* overflow only if r1 = -0x80000000 */
3943        temp = tcg_const_i32(-0x80000000);
3944        /* calc V bit */
3945        tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3946        tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3947        /* calc SV bit */
3948        tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3949        /* sub */
3950        tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3951        /* calc av */
3952        tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3953        tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3954        /* calc sav */
3955        tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3956        tcg_temp_free(temp);
3957        break;
3958    case OPC2_16_SR_SAT_B:
3959        gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3960        break;
3961    case OPC2_16_SR_SAT_BU:
3962        gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3963        break;
3964    case OPC2_16_SR_SAT_H:
3965        gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3966        break;
3967    case OPC2_16_SR_SAT_HU:
3968        gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3969        break;
3970    default:
3971        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
3972    }
3973}
3974
3975static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3976{
3977    int op1;
3978    int r1, r2;
3979    int32_t const16;
3980    int32_t address;
3981    TCGv temp;
3982
3983    op1 = MASK_OP_MAJOR(ctx->opcode);
3984
3985    /* handle ADDSC.A opcode only being 6 bit long */
3986    if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3987        op1 = OPC1_16_SRRS_ADDSC_A;
3988    }
3989
3990    switch (op1) {
3991    case OPC1_16_SRC_ADD:
3992    case OPC1_16_SRC_ADD_A15:
3993    case OPC1_16_SRC_ADD_15A:
3994    case OPC1_16_SRC_ADD_A:
3995    case OPC1_16_SRC_CADD:
3996    case OPC1_16_SRC_CADDN:
3997    case OPC1_16_SRC_CMOV:
3998    case OPC1_16_SRC_CMOVN:
3999    case OPC1_16_SRC_EQ:
4000    case OPC1_16_SRC_LT:
4001    case OPC1_16_SRC_MOV:
4002    case OPC1_16_SRC_MOV_A:
4003    case OPC1_16_SRC_MOV_E:
4004    case OPC1_16_SRC_SH:
4005    case OPC1_16_SRC_SHA:
4006        decode_src_opc(env, ctx, op1);
4007        break;
4008/* SRR-format */
4009    case OPC1_16_SRR_ADD:
4010    case OPC1_16_SRR_ADD_A15:
4011    case OPC1_16_SRR_ADD_15A:
4012    case OPC1_16_SRR_ADD_A:
4013    case OPC1_16_SRR_ADDS:
4014    case OPC1_16_SRR_AND:
4015    case OPC1_16_SRR_CMOV:
4016    case OPC1_16_SRR_CMOVN:
4017    case OPC1_16_SRR_EQ:
4018    case OPC1_16_SRR_LT:
4019    case OPC1_16_SRR_MOV:
4020    case OPC1_16_SRR_MOV_A:
4021    case OPC1_16_SRR_MOV_AA:
4022    case OPC1_16_SRR_MOV_D:
4023    case OPC1_16_SRR_MUL:
4024    case OPC1_16_SRR_OR:
4025    case OPC1_16_SRR_SUB:
4026    case OPC1_16_SRR_SUB_A15B:
4027    case OPC1_16_SRR_SUB_15AB:
4028    case OPC1_16_SRR_SUBS:
4029    case OPC1_16_SRR_XOR:
4030        decode_srr_opc(ctx, op1);
4031        break;
4032/* SSR-format */
4033    case OPC1_16_SSR_ST_A:
4034    case OPC1_16_SSR_ST_A_POSTINC:
4035    case OPC1_16_SSR_ST_B:
4036    case OPC1_16_SSR_ST_B_POSTINC:
4037    case OPC1_16_SSR_ST_H:
4038    case OPC1_16_SSR_ST_H_POSTINC:
4039    case OPC1_16_SSR_ST_W:
4040    case OPC1_16_SSR_ST_W_POSTINC:
4041        decode_ssr_opc(ctx, op1);
4042        break;
4043/* SRRS-format */
4044    case OPC1_16_SRRS_ADDSC_A:
4045        r2 = MASK_OP_SRRS_S2(ctx->opcode);
4046        r1 = MASK_OP_SRRS_S1D(ctx->opcode);
4047        const16 = MASK_OP_SRRS_N(ctx->opcode);
4048        temp = tcg_temp_new();
4049        tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
4050        tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
4051        tcg_temp_free(temp);
4052        break;
4053/* SLRO-format */
4054    case OPC1_16_SLRO_LD_A:
4055        r1 = MASK_OP_SLRO_D(ctx->opcode);
4056        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4057        gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4058        break;
4059    case OPC1_16_SLRO_LD_BU:
4060        r1 = MASK_OP_SLRO_D(ctx->opcode);
4061        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4062        gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4063        break;
4064    case OPC1_16_SLRO_LD_H:
4065        r1 = MASK_OP_SLRO_D(ctx->opcode);
4066        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4067        gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4068        break;
4069    case OPC1_16_SLRO_LD_W:
4070        r1 = MASK_OP_SLRO_D(ctx->opcode);
4071        const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
4072        gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4073        break;
4074/* SB-format */
4075    case OPC1_16_SB_CALL:
4076    case OPC1_16_SB_J:
4077    case OPC1_16_SB_JNZ:
4078    case OPC1_16_SB_JZ:
4079        address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4080        gen_compute_branch(ctx, op1, 0, 0, 0, address);
4081        break;
4082/* SBC-format */
4083    case OPC1_16_SBC_JEQ:
4084    case OPC1_16_SBC_JNE:
4085        address = MASK_OP_SBC_DISP4(ctx->opcode);
4086        const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4087        gen_compute_branch(ctx, op1, 0, 0, const16, address);
4088        break;
4089/* SBRN-format */
4090    case OPC1_16_SBRN_JNZ_T:
4091    case OPC1_16_SBRN_JZ_T:
4092        address = MASK_OP_SBRN_DISP4(ctx->opcode);
4093        const16 = MASK_OP_SBRN_N(ctx->opcode);
4094        gen_compute_branch(ctx, op1, 0, 0, const16, address);
4095        break;
4096/* SBR-format */
4097    case OPC1_16_SBR_JEQ:
4098    case OPC1_16_SBR_JGEZ:
4099    case OPC1_16_SBR_JGTZ:
4100    case OPC1_16_SBR_JLEZ:
4101    case OPC1_16_SBR_JLTZ:
4102    case OPC1_16_SBR_JNE:
4103    case OPC1_16_SBR_JNZ:
4104    case OPC1_16_SBR_JNZ_A:
4105    case OPC1_16_SBR_JZ:
4106    case OPC1_16_SBR_JZ_A:
4107    case OPC1_16_SBR_LOOP:
4108        r1 = MASK_OP_SBR_S2(ctx->opcode);
4109        address = MASK_OP_SBR_DISP4(ctx->opcode);
4110        gen_compute_branch(ctx, op1, r1, 0, 0, address);
4111        break;
4112/* SC-format */
4113    case OPC1_16_SC_AND:
4114    case OPC1_16_SC_BISR:
4115    case OPC1_16_SC_LD_A:
4116    case OPC1_16_SC_LD_W:
4117    case OPC1_16_SC_MOV:
4118    case OPC1_16_SC_OR:
4119    case OPC1_16_SC_ST_A:
4120    case OPC1_16_SC_ST_W:
4121    case OPC1_16_SC_SUB_A:
4122        decode_sc_opc(ctx, op1);
4123        break;
4124/* SLR-format */
4125    case OPC1_16_SLR_LD_A:
4126    case OPC1_16_SLR_LD_A_POSTINC:
4127    case OPC1_16_SLR_LD_BU:
4128    case OPC1_16_SLR_LD_BU_POSTINC:
4129    case OPC1_16_SLR_LD_H:
4130    case OPC1_16_SLR_LD_H_POSTINC:
4131    case OPC1_16_SLR_LD_W:
4132    case OPC1_16_SLR_LD_W_POSTINC:
4133        decode_slr_opc(ctx, op1);
4134        break;
4135/* SRO-format */
4136    case OPC1_16_SRO_LD_A:
4137    case OPC1_16_SRO_LD_BU:
4138    case OPC1_16_SRO_LD_H:
4139    case OPC1_16_SRO_LD_W:
4140    case OPC1_16_SRO_ST_A:
4141    case OPC1_16_SRO_ST_B:
4142    case OPC1_16_SRO_ST_H:
4143    case OPC1_16_SRO_ST_W:
4144        decode_sro_opc(ctx, op1);
4145        break;
4146/* SSRO-format */
4147    case OPC1_16_SSRO_ST_A:
4148        r1 = MASK_OP_SSRO_S1(ctx->opcode);
4149        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4150        gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4151        break;
4152    case OPC1_16_SSRO_ST_B:
4153        r1 = MASK_OP_SSRO_S1(ctx->opcode);
4154        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4155        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4156        break;
4157    case OPC1_16_SSRO_ST_H:
4158        r1 = MASK_OP_SSRO_S1(ctx->opcode);
4159        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4160        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4161        break;
4162    case OPC1_16_SSRO_ST_W:
4163        r1 = MASK_OP_SSRO_S1(ctx->opcode);
4164        const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4165        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4166        break;
4167/* SR-format */
4168    case OPCM_16_SR_SYSTEM:
4169        decode_sr_system(env, ctx);
4170        break;
4171    case OPCM_16_SR_ACCU:
4172        decode_sr_accu(env, ctx);
4173        break;
4174    case OPC1_16_SR_JI:
4175        r1 = MASK_OP_SR_S1D(ctx->opcode);
4176        gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4177        break;
4178    case OPC1_16_SR_NOT:
4179        r1 = MASK_OP_SR_S1D(ctx->opcode);
4180        tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4181        break;
4182    default:
4183        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4184    }
4185}
4186
4187/*
4188 * 32 bit instructions
4189 */
4190
4191/* ABS-format */
4192static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4193{
4194    int32_t op2;
4195    int32_t r1;
4196    uint32_t address;
4197    TCGv temp;
4198
4199    r1 = MASK_OP_ABS_S1D(ctx->opcode);
4200    address = MASK_OP_ABS_OFF18(ctx->opcode);
4201    op2 = MASK_OP_ABS_OP2(ctx->opcode);
4202
4203    temp = tcg_const_i32(EA_ABS_FORMAT(address));
4204
4205    switch (op2) {
4206    case OPC2_32_ABS_LD_A:
4207        tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4208        break;
4209    case OPC2_32_ABS_LD_D:
4210        CHECK_REG_PAIR(r1);
4211        gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4212        break;
4213    case OPC2_32_ABS_LD_DA:
4214        CHECK_REG_PAIR(r1);
4215        gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4216        break;
4217    case OPC2_32_ABS_LD_W:
4218        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4219        break;
4220    default:
4221        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4222    }
4223
4224    tcg_temp_free(temp);
4225}
4226
4227static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4228{
4229    int32_t op2;
4230    int32_t r1;
4231    uint32_t address;
4232    TCGv temp;
4233
4234    r1 = MASK_OP_ABS_S1D(ctx->opcode);
4235    address = MASK_OP_ABS_OFF18(ctx->opcode);
4236    op2 = MASK_OP_ABS_OP2(ctx->opcode);
4237
4238    temp = tcg_const_i32(EA_ABS_FORMAT(address));
4239
4240    switch (op2) {
4241    case OPC2_32_ABS_LD_B:
4242        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4243        break;
4244    case OPC2_32_ABS_LD_BU:
4245        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4246        break;
4247    case OPC2_32_ABS_LD_H:
4248        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4249        break;
4250    case OPC2_32_ABS_LD_HU:
4251        tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4252        break;
4253    default:
4254        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4255    }
4256
4257    tcg_temp_free(temp);
4258}
4259
4260static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4261{
4262    int32_t op2;
4263    int32_t r1;
4264    uint32_t address;
4265    TCGv temp;
4266
4267    r1 = MASK_OP_ABS_S1D(ctx->opcode);
4268    address = MASK_OP_ABS_OFF18(ctx->opcode);
4269    op2 = MASK_OP_ABS_OP2(ctx->opcode);
4270
4271    temp = tcg_const_i32(EA_ABS_FORMAT(address));
4272
4273    switch (op2) {
4274    case OPC2_32_ABS_LDMST:
4275        gen_ldmst(ctx, r1, temp);
4276        break;
4277    case OPC2_32_ABS_SWAP_W:
4278        gen_swap(ctx, r1, temp);
4279        break;
4280    default:
4281        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4282    }
4283
4284    tcg_temp_free(temp);
4285}
4286
4287static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4288{
4289    uint32_t op2;
4290    int32_t off18;
4291
4292    off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4293    op2   = MASK_OP_ABS_OP2(ctx->opcode);
4294
4295    switch (op2) {
4296    case OPC2_32_ABS_LDLCX:
4297        gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4298        break;
4299    case OPC2_32_ABS_LDUCX:
4300        gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4301        break;
4302    case OPC2_32_ABS_STLCX:
4303        gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4304        break;
4305    case OPC2_32_ABS_STUCX:
4306        gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4307        break;
4308    default:
4309        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4310    }
4311}
4312
4313static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4314{
4315    int32_t op2;
4316    int32_t r1;
4317    uint32_t address;
4318    TCGv temp;
4319
4320    r1 = MASK_OP_ABS_S1D(ctx->opcode);
4321    address = MASK_OP_ABS_OFF18(ctx->opcode);
4322    op2 = MASK_OP_ABS_OP2(ctx->opcode);
4323
4324    temp = tcg_const_i32(EA_ABS_FORMAT(address));
4325
4326    switch (op2) {
4327    case OPC2_32_ABS_ST_A:
4328        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4329        break;
4330    case OPC2_32_ABS_ST_D:
4331        CHECK_REG_PAIR(r1);
4332        gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4333        break;
4334    case OPC2_32_ABS_ST_DA:
4335        CHECK_REG_PAIR(r1);
4336        gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4337        break;
4338    case OPC2_32_ABS_ST_W:
4339        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4340        break;
4341    default:
4342        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4343    }
4344    tcg_temp_free(temp);
4345}
4346
4347static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4348{
4349    int32_t op2;
4350    int32_t r1;
4351    uint32_t address;
4352    TCGv temp;
4353
4354    r1 = MASK_OP_ABS_S1D(ctx->opcode);
4355    address = MASK_OP_ABS_OFF18(ctx->opcode);
4356    op2 = MASK_OP_ABS_OP2(ctx->opcode);
4357
4358    temp = tcg_const_i32(EA_ABS_FORMAT(address));
4359
4360    switch (op2) {
4361    case OPC2_32_ABS_ST_B:
4362        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4363        break;
4364    case OPC2_32_ABS_ST_H:
4365        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4366        break;
4367    default:
4368        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4369    }
4370    tcg_temp_free(temp);
4371}
4372
4373/* Bit-format */
4374
4375static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4376{
4377    uint32_t op2;
4378    int r1, r2, r3;
4379    int pos1, pos2;
4380
4381    r1 = MASK_OP_BIT_S1(ctx->opcode);
4382    r2 = MASK_OP_BIT_S2(ctx->opcode);
4383    r3 = MASK_OP_BIT_D(ctx->opcode);
4384    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4385    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4386    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4387
4388
4389    switch (op2) {
4390    case OPC2_32_BIT_AND_AND_T:
4391        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4392                    pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4393        break;
4394    case OPC2_32_BIT_AND_ANDN_T:
4395        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4396                    pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4397        break;
4398    case OPC2_32_BIT_AND_NOR_T:
4399        if (TCG_TARGET_HAS_andc_i32) {
4400            gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4401                        pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4402        } else {
4403            gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4404                        pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4405        }
4406        break;
4407    case OPC2_32_BIT_AND_OR_T:
4408        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4409                    pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4410        break;
4411    default:
4412        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4413    }
4414}
4415
4416static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4417{
4418    uint32_t op2;
4419    int r1, r2, r3;
4420    int pos1, pos2;
4421    r1 = MASK_OP_BIT_S1(ctx->opcode);
4422    r2 = MASK_OP_BIT_S2(ctx->opcode);
4423    r3 = MASK_OP_BIT_D(ctx->opcode);
4424    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4425    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4426    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4427
4428    switch (op2) {
4429    case OPC2_32_BIT_AND_T:
4430        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4431                    pos1, pos2, &tcg_gen_and_tl);
4432        break;
4433    case OPC2_32_BIT_ANDN_T:
4434        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4435                    pos1, pos2, &tcg_gen_andc_tl);
4436        break;
4437    case OPC2_32_BIT_NOR_T:
4438        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4439                    pos1, pos2, &tcg_gen_nor_tl);
4440        break;
4441    case OPC2_32_BIT_OR_T:
4442        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4443                    pos1, pos2, &tcg_gen_or_tl);
4444        break;
4445    default:
4446        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4447    }
4448}
4449
4450static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4451{
4452    uint32_t op2;
4453    int r1, r2, r3;
4454    int pos1, pos2;
4455    TCGv temp;
4456    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4457    r1 = MASK_OP_BIT_S1(ctx->opcode);
4458    r2 = MASK_OP_BIT_S2(ctx->opcode);
4459    r3 = MASK_OP_BIT_D(ctx->opcode);
4460    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4461    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4462
4463    temp = tcg_temp_new();
4464
4465    tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4466    if (op2 == OPC2_32_BIT_INSN_T) {
4467        tcg_gen_not_tl(temp, temp);
4468    }
4469    tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4470    tcg_temp_free(temp);
4471}
4472
4473static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4474{
4475    uint32_t op2;
4476
4477    int r1, r2, r3;
4478    int pos1, pos2;
4479
4480    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4481    r1 = MASK_OP_BIT_S1(ctx->opcode);
4482    r2 = MASK_OP_BIT_S2(ctx->opcode);
4483    r3 = MASK_OP_BIT_D(ctx->opcode);
4484    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4485    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4486
4487    switch (op2) {
4488    case OPC2_32_BIT_NAND_T:
4489        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4490                    pos1, pos2, &tcg_gen_nand_tl);
4491        break;
4492    case OPC2_32_BIT_ORN_T:
4493        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4494                    pos1, pos2, &tcg_gen_orc_tl);
4495        break;
4496    case OPC2_32_BIT_XNOR_T:
4497        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4498                    pos1, pos2, &tcg_gen_eqv_tl);
4499        break;
4500    case OPC2_32_BIT_XOR_T:
4501        gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4502                    pos1, pos2, &tcg_gen_xor_tl);
4503        break;
4504    default:
4505        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4506    }
4507}
4508
4509static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4510{
4511    uint32_t op2;
4512
4513    int r1, r2, r3;
4514    int pos1, pos2;
4515
4516    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4517    r1 = MASK_OP_BIT_S1(ctx->opcode);
4518    r2 = MASK_OP_BIT_S2(ctx->opcode);
4519    r3 = MASK_OP_BIT_D(ctx->opcode);
4520    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4521    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4522
4523    switch (op2) {
4524    case OPC2_32_BIT_OR_AND_T:
4525        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4526                    pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4527        break;
4528    case OPC2_32_BIT_OR_ANDN_T:
4529        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4530                    pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4531        break;
4532    case OPC2_32_BIT_OR_NOR_T:
4533        if (TCG_TARGET_HAS_orc_i32) {
4534            gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4535                        pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4536        } else {
4537            gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4538                        pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4539        }
4540        break;
4541    case OPC2_32_BIT_OR_OR_T:
4542        gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4543                    pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4544        break;
4545    default:
4546        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4547    }
4548}
4549
4550static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4551{
4552    uint32_t op2;
4553    int r1, r2, r3;
4554    int pos1, pos2;
4555    TCGv temp;
4556
4557    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4558    r1 = MASK_OP_BIT_S1(ctx->opcode);
4559    r2 = MASK_OP_BIT_S2(ctx->opcode);
4560    r3 = MASK_OP_BIT_D(ctx->opcode);
4561    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4562    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4563
4564    temp = tcg_temp_new();
4565
4566    switch (op2) {
4567    case OPC2_32_BIT_SH_AND_T:
4568        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4569                    pos1, pos2, &tcg_gen_and_tl);
4570        break;
4571    case OPC2_32_BIT_SH_ANDN_T:
4572        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4573                    pos1, pos2, &tcg_gen_andc_tl);
4574        break;
4575    case OPC2_32_BIT_SH_NOR_T:
4576        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4577                    pos1, pos2, &tcg_gen_nor_tl);
4578        break;
4579    case OPC2_32_BIT_SH_OR_T:
4580        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4581                    pos1, pos2, &tcg_gen_or_tl);
4582        break;
4583    default:
4584        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4585    }
4586    tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4587    tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4588    tcg_temp_free(temp);
4589}
4590
4591static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4592{
4593    uint32_t op2;
4594    int r1, r2, r3;
4595    int pos1, pos2;
4596    TCGv temp;
4597
4598    op2 = MASK_OP_BIT_OP2(ctx->opcode);
4599    r1 = MASK_OP_BIT_S1(ctx->opcode);
4600    r2 = MASK_OP_BIT_S2(ctx->opcode);
4601    r3 = MASK_OP_BIT_D(ctx->opcode);
4602    pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4603    pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4604
4605    temp = tcg_temp_new();
4606
4607    switch (op2) {
4608    case OPC2_32_BIT_SH_NAND_T:
4609        gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4610                    pos1, pos2, &tcg_gen_nand_tl);
4611        break;
4612    case OPC2_32_BIT_SH_ORN_T:
4613        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4614                    pos1, pos2, &tcg_gen_orc_tl);
4615        break;
4616    case OPC2_32_BIT_SH_XNOR_T:
4617        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4618                    pos1, pos2, &tcg_gen_eqv_tl);
4619        break;
4620    case OPC2_32_BIT_SH_XOR_T:
4621        gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4622                    pos1, pos2, &tcg_gen_xor_tl);
4623        break;
4624    default:
4625        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4626    }
4627    tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4628    tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4629    tcg_temp_free(temp);
4630}
4631
4632/* BO-format */
4633
4634
4635static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4636                                             DisasContext *ctx)
4637{
4638    uint32_t op2;
4639    uint32_t off10;
4640    int32_t r1, r2;
4641    TCGv temp;
4642
4643    r1 = MASK_OP_BO_S1D(ctx->opcode);
4644    r2  = MASK_OP_BO_S2(ctx->opcode);
4645    off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4646    op2 = MASK_OP_BO_OP2(ctx->opcode);
4647
4648    switch (op2) {
4649    case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4650    case OPC2_32_BO_CACHEA_W_SHORTOFF:
4651    case OPC2_32_BO_CACHEA_I_SHORTOFF:
4652        /* instruction to access the cache */
4653        break;
4654    case OPC2_32_BO_CACHEA_WI_POSTINC:
4655    case OPC2_32_BO_CACHEA_W_POSTINC:
4656    case OPC2_32_BO_CACHEA_I_POSTINC:
4657        /* instruction to access the cache, but we still need to handle
4658           the addressing mode */
4659        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4660        break;
4661    case OPC2_32_BO_CACHEA_WI_PREINC:
4662    case OPC2_32_BO_CACHEA_W_PREINC:
4663    case OPC2_32_BO_CACHEA_I_PREINC:
4664        /* instruction to access the cache, but we still need to handle
4665           the addressing mode */
4666        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4667        break;
4668    case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4669    case OPC2_32_BO_CACHEI_W_SHORTOFF:
4670        if (!tricore_feature(env, TRICORE_FEATURE_131)) {
4671            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4672        }
4673        break;
4674    case OPC2_32_BO_CACHEI_W_POSTINC:
4675    case OPC2_32_BO_CACHEI_WI_POSTINC:
4676        if (tricore_feature(env, TRICORE_FEATURE_131)) {
4677            tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4678        } else {
4679            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4680        }
4681        break;
4682    case OPC2_32_BO_CACHEI_W_PREINC:
4683    case OPC2_32_BO_CACHEI_WI_PREINC:
4684        if (tricore_feature(env, TRICORE_FEATURE_131)) {
4685            tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4686        } else {
4687            generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4688        }
4689        break;
4690    case OPC2_32_BO_ST_A_SHORTOFF:
4691        gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4692        break;
4693    case OPC2_32_BO_ST_A_POSTINC:
4694        tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4695                           MO_LESL);
4696        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4697        break;
4698    case OPC2_32_BO_ST_A_PREINC:
4699        gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4700        break;
4701    case OPC2_32_BO_ST_B_SHORTOFF:
4702        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4703        break;
4704    case OPC2_32_BO_ST_B_POSTINC:
4705        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4706                           MO_UB);
4707        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4708        break;
4709    case OPC2_32_BO_ST_B_PREINC:
4710        gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4711        break;
4712    case OPC2_32_BO_ST_D_SHORTOFF:
4713        CHECK_REG_PAIR(r1);
4714        gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4715                            off10, ctx);
4716        break;
4717    case OPC2_32_BO_ST_D_POSTINC:
4718        CHECK_REG_PAIR(r1);
4719        gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4720        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4721        break;
4722    case OPC2_32_BO_ST_D_PREINC:
4723        CHECK_REG_PAIR(r1);
4724        temp = tcg_temp_new();
4725        tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4726        gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4727        tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4728        tcg_temp_free(temp);
4729        break;
4730    case OPC2_32_BO_ST_DA_SHORTOFF:
4731        CHECK_REG_PAIR(r1);
4732        gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4733                            off10, ctx);
4734        break;
4735    case OPC2_32_BO_ST_DA_POSTINC:
4736        CHECK_REG_PAIR(r1);
4737        gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4738        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4739        break;
4740    case OPC2_32_BO_ST_DA_PREINC:
4741        CHECK_REG_PAIR(r1);
4742        temp = tcg_temp_new();
4743        tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4744        gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4745        tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4746        tcg_temp_free(temp);
4747        break;
4748    case OPC2_32_BO_ST_H_SHORTOFF:
4749        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4750        break;
4751    case OPC2_32_BO_ST_H_POSTINC:
4752        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4753                           MO_LEUW);
4754        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4755        break;
4756    case OPC2_32_BO_ST_H_PREINC:
4757        gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4758        break;
4759    case OPC2_32_BO_ST_Q_SHORTOFF:
4760        temp = tcg_temp_new();
4761        tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4762        gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4763        tcg_temp_free(temp);
4764        break;
4765    case OPC2_32_BO_ST_Q_POSTINC:
4766        temp = tcg_temp_new();
4767        tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4768        tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4769                           MO_LEUW);
4770        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4771        tcg_temp_free(temp);
4772        break;
4773    case OPC2_32_BO_ST_Q_PREINC:
4774        temp = tcg_temp_new();
4775        tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4776        gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4777        tcg_temp_free(temp);
4778        break;
4779    case OPC2_32_BO_ST_W_SHORTOFF:
4780        gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4781        break;
4782    case OPC2_32_BO_ST_W_POSTINC:
4783        tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4784                           MO_LEUL);
4785        tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4786        break;
4787    case OPC2_32_BO_ST_W_PREINC:
4788        gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4789        break;
4790    default:
4791        generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC);
4792    }
4793}
4794
4795static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4796                                                   DisasContext *ctx)
4797{
4798    uint32_t op2;
4799    uint32_t off10;
4800    int32_t r1, r2;
4801    TCGv temp, temp2, temp3;
4802
4803    r1 = MASK_OP_BO_S1D(ctx->opcode);
4804    r2  = MASK_OP_BO_S2(ctx->opcode);
4805    off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4806    op2 = MASK_OP_BO_OP2(ctx->opcode);
480