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11#ifndef QEMU_UNICORE32_CPU_H
12#define QEMU_UNICORE32_CPU_H
13
14#define TARGET_LONG_BITS 32
15#define TARGET_PAGE_BITS 12
16
17#define TARGET_PHYS_ADDR_SPACE_BITS 32
18#define TARGET_VIRT_ADDR_SPACE_BITS 32
19
20#define CPUArchState struct CPUUniCore32State
21
22#include "qemu-common.h"
23#include "exec/cpu-defs.h"
24#include "fpu/softfloat.h"
25
26#define NB_MMU_MODES 2
27
28typedef struct CPUUniCore32State {
29
30 uint32_t regs[32];
31
32
33
34 uint32_t uncached_asr;
35 uint32_t bsr;
36
37
38 uint32_t banked_bsr[6];
39 uint32_t banked_r29[6];
40 uint32_t banked_r30[6];
41
42
43 uint32_t CF;
44 uint32_t VF;
45 uint32_t NF;
46 uint32_t ZF;
47
48
49 struct {
50 uint32_t c0_cpuid;
51 uint32_t c0_cachetype;
52 uint32_t c1_sys;
53 uint32_t c2_base;
54 uint32_t c3_faultstatus;
55 uint32_t c4_faultaddr;
56 uint32_t c5_cacheop;
57 uint32_t c6_tlbop;
58 } cp0;
59
60
61 struct {
62 float64 regs[16];
63 uint32_t xregs[32];
64 float_status fp_status;
65 } ucf64;
66
67 CPU_COMMON
68
69
70 uint32_t features;
71
72} CPUUniCore32State;
73
74#define ASR_M (0x1f)
75#define ASR_MODE_USER (0x10)
76#define ASR_MODE_INTR (0x12)
77#define ASR_MODE_PRIV (0x13)
78#define ASR_MODE_TRAP (0x17)
79#define ASR_MODE_EXTN (0x1b)
80#define ASR_MODE_SUSR (0x1f)
81#define ASR_I (1 << 7)
82#define ASR_V (1 << 28)
83#define ASR_C (1 << 29)
84#define ASR_Z (1 << 30)
85#define ASR_N (1 << 31)
86#define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
87#define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
88
89#define UC32_EXCP_PRIV (1)
90#define UC32_EXCP_ITRAP (2)
91#define UC32_EXCP_DTRAP (3)
92#define UC32_EXCP_INTR (4)
93
94
95target_ulong cpu_asr_read(CPUUniCore32State *env1);
96
97void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
98
99
100#define UC32_UCF64_FPSCR (31)
101#define UCF64_FPSCR_MASK (0x27ffffff)
102#define UCF64_FPSCR_RND_MASK (0x7)
103#define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
104#define UCF64_FPSCR_TRAPEN_MASK (0x7f)
105#define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
106#define UCF64_FPSCR_FLAG_MASK (0x3ff)
107#define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
108#define UCF64_FPSCR_FLAG_ZERO (1 << 17)
109#define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
110#define UCF64_FPSCR_FLAG_INVALID (1 << 19)
111#define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
112#define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
113#define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
114#define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
115#define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
116#define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
117#define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
118
119#define UC32_HWCAP_CMOV 4
120#define UC32_HWCAP_UCF64 8
121
122#define cpu_exec uc32_cpu_exec
123#define cpu_signal_handler uc32_cpu_signal_handler
124
125int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
126
127
128#define MMU_MODE0_SUFFIX _kernel
129#define MMU_MODE1_SUFFIX _user
130#define MMU_USER_IDX 1
131static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
132{
133 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
134}
135
136#include "exec/cpu-all.h"
137#include "cpu-qom.h"
138#include "exec/exec-all.h"
139
140int uc32_cpu_exec(CPUState *s);
141
142UniCore32CPU *uc32_cpu_init(const char *cpu_model);
143
144#define cpu_init(cpu_model) CPU(uc32_cpu_init(cpu_model))
145
146static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
147 target_ulong *cs_base, int *flags)
148{
149 *pc = env->regs[31];
150 *cs_base = 0;
151 *flags = 0;
152 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
153 *flags |= (1 << 6);
154 }
155}
156
157int uc32_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
158 int mmu_idx);
159void uc32_translate_init(void);
160void switch_mode(CPUUniCore32State *, int);
161
162#endif
163