LXR qemu/target-unicore32/ucf64

   1/*
   2 * UniCore-F64 simulation helpers for QEMU.
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#include "qemu/osdep.h"
  12#include "cpu.h"
  13#include "exec/helper-proto.h"
  14
  15/*
  16 * The convention used for UniCore-F64 instructions:
  17 *  Single precition routines have a "s" suffix
  18 *  Double precision routines have a "d" suffix.
  19 */
  20
  21/* Convert host exception flags to f64 form.  */
  22static inline int ucf64_exceptbits_from_host(int host_bits)
  23{
  24    int target_bits = 0;
  25
  26    if (host_bits & float_flag_invalid) {
  27        target_bits |= UCF64_FPSCR_FLAG_INVALID;
  28    }
  29    if (host_bits & float_flag_divbyzero) {
  30        target_bits |= UCF64_FPSCR_FLAG_DIVZERO;
  31    }
  32    if (host_bits & float_flag_overflow) {
  33        target_bits |= UCF64_FPSCR_FLAG_OVERFLOW;
  34    }
  35    if (host_bits & float_flag_underflow) {
  36        target_bits |= UCF64_FPSCR_FLAG_UNDERFLOW;
  37    }
  38    if (host_bits & float_flag_inexact) {
  39        target_bits |= UCF64_FPSCR_FLAG_INEXACT;
  40    }
  41    return target_bits;
  42}
  43
  44uint32_t HELPER(ucf64_get_fpscr)(CPUUniCore32State *env)
  45{
  46    int i;
  47    uint32_t fpscr;
  48
  49    fpscr = (env->ucf64.xregs[UC32_UCF64_FPSCR] & UCF64_FPSCR_MASK);
  50    i = get_float_exception_flags(&env->ucf64.fp_status);
  51    fpscr |= ucf64_exceptbits_from_host(i);
  52    return fpscr;
  53}
  54
  55/* Convert ucf64 exception flags to target form.  */
  56static inline int ucf64_exceptbits_to_host(int target_bits)
  57{
  58    int host_bits = 0;
  59
  60    if (target_bits & UCF64_FPSCR_FLAG_INVALID) {
  61        host_bits |= float_flag_invalid;
  62    }
  63    if (target_bits & UCF64_FPSCR_FLAG_DIVZERO) {
  64        host_bits |= float_flag_divbyzero;
  65    }
  66    if (target_bits & UCF64_FPSCR_FLAG_OVERFLOW) {
  67        host_bits |= float_flag_overflow;
  68    }
  69    if (target_bits & UCF64_FPSCR_FLAG_UNDERFLOW) {
  70        host_bits |= float_flag_underflow;
  71    }
  72    if (target_bits & UCF64_FPSCR_FLAG_INEXACT) {
  73        host_bits |= float_flag_inexact;
  74    }
  75    return host_bits;
  76}
  77
  78void HELPER(ucf64_set_fpscr)(CPUUniCore32State *env, uint32_t val)
  79{
  80    UniCore32CPU *cpu = uc32_env_get_cpu(env);
  81    int i;
  82    uint32_t changed;
  83
  84    changed = env->ucf64.xregs[UC32_UCF64_FPSCR];
  85    env->ucf64.xregs[UC32_UCF64_FPSCR] = (val & UCF64_FPSCR_MASK);
  86
  87    changed ^= val;
  88    if (changed & (UCF64_FPSCR_RND_MASK)) {
  89        i = UCF64_FPSCR_RND(val);
  90        switch (i) {
  91        case 0:
  92            i = float_round_nearest_even;
  93            break;
  94        case 1:
  95            i = float_round_to_zero;
  96            break;
  97        case 2:
  98            i = float_round_up;
  99            break;
 100        case 3:
 101            i = float_round_down;
 102            break;
 103        default: /* 100 and 101 not implement */
 104            cpu_abort(CPU(cpu), "Unsupported UniCore-F64 round mode");
 105        }
 106        set_float_rounding_mode(i, &env->ucf64.fp_status);
 107    }
 108
 109    i = ucf64_exceptbits_to_host(UCF64_FPSCR_TRAPEN(val));
 110    set_float_exception_flags(i, &env->ucf64.fp_status);
 111}
 112
 113float32 HELPER(ucf64_adds)(float32 a, float32 b, CPUUniCore32State *env)
 114{
 115    return float32_add(a, b, &env->ucf64.fp_status);
 116}
 117
 118float64 HELPER(ucf64_addd)(float64 a, float64 b, CPUUniCore32State *env)
 119{
 120    return float64_add(a, b, &env->ucf64.fp_status);
 121}
 122
 123float32 HELPER(ucf64_subs)(float32 a, float32 b, CPUUniCore32State *env)
 124{
 125    return float32_sub(a, b, &env->ucf64.fp_status);
 126}
 127
 128float64 HELPER(ucf64_subd)(float64 a, float64 b, CPUUniCore32State *env)
 129{
 130    return float64_sub(a, b, &env->ucf64.fp_status);
 131}
 132
 133float32 HELPER(ucf64_muls)(float32 a, float32 b, CPUUniCore32State *env)
 134{
 135    return float32_mul(a, b, &env->ucf64.fp_status);
 136}
 137
 138float64 HELPER(ucf64_muld)(float64 a, float64 b, CPUUniCore32State *env)
 139{
 140    return float64_mul(a, b, &env->ucf64.fp_status);
 141}
 142
 143float32 HELPER(ucf64_divs)(float32 a, float32 b, CPUUniCore32State *env)
 144{
 145    return float32_div(a, b, &env->ucf64.fp_status);
 146}
 147
 148float64 HELPER(ucf64_divd)(float64 a, float64 b, CPUUniCore32State *env)
 149{
 150    return float64_div(a, b, &env->ucf64.fp_status);
 151}
 152
 153float32 HELPER(ucf64_negs)(float32 a)
 154{
 155    return float32_chs(a);
 156}
 157
 158float64 HELPER(ucf64_negd)(float64 a)
 159{
 160    return float64_chs(a);
 161}
 162
 163float32 HELPER(ucf64_abss)(float32 a)
 164{
 165    return float32_abs(a);
 166}
 167
 168float64 HELPER(ucf64_absd)(float64 a)
 169{
 170    return float64_abs(a);
 171}
 172
 173void HELPER(ucf64_cmps)(float32 a, float32 b, uint32_t c,
 174        CPUUniCore32State *env)
 175{
 176    int flag;
 177    flag = float32_compare_quiet(a, b, &env->ucf64.fp_status);
 178    env->CF = 0;
 179    switch (c & 0x7) {
 180    case 0: /* F */
 181        break;
 182    case 1: /* UN */
 183        if (flag == 2) {
 184            env->CF = 1;
 185        }
 186        break;
 187    case 2: /* EQ */
 188        if (flag == 0) {
 189            env->CF = 1;
 190        }
 191        break;
 192    case 3: /* UEQ */
 193        if ((flag == 0) || (flag == 2)) {
 194            env->CF = 1;
 195        }
 196        break;
 197    case 4: /* OLT */
 198        if (flag == -1) {
 199            env->CF = 1;
 200        }
 201        break;
 202    case 5: /* ULT */
 203        if ((flag == -1) || (flag == 2)) {
 204            env->CF = 1;
 205        }
 206        break;
 207    case 6: /* OLE */
 208        if ((flag == -1) || (flag == 0)) {
 209            env->CF = 1;
 210        }
 211        break;
 212    case 7: /* ULE */
 213        if (flag != 1) {
 214            env->CF = 1;
 215        }
 216        break;
 217    }
 218    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 219                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 220}
 221
 222void HELPER(ucf64_cmpd)(float64 a, float64 b, uint32_t c,
 223        CPUUniCore32State *env)
 224{
 225    int flag;
 226    flag = float64_compare_quiet(a, b, &env->ucf64.fp_status);
 227    env->CF = 0;
 228    switch (c & 0x7) {
 229    case 0: /* F */
 230        break;
 231    case 1: /* UN */
 232        if (flag == 2) {
 233            env->CF = 1;
 234        }
 235        break;
 236    case 2: /* EQ */
 237        if (flag == 0) {
 238            env->CF = 1;
 239        }
 240        break;
 241    case 3: /* UEQ */
 242        if ((flag == 0) || (flag == 2)) {
 243            env->CF = 1;
 244        }
 245        break;
 246    case 4: /* OLT */
 247        if (flag == -1) {
 248            env->CF = 1;
 249        }
 250        break;
 251    case 5: /* ULT */
 252        if ((flag == -1) || (flag == 2)) {
 253            env->CF = 1;
 254        }
 255        break;
 256    case 6: /* OLE */
 257        if ((flag == -1) || (flag == 0)) {
 258            env->CF = 1;
 259        }
 260        break;
 261    case 7: /* ULE */
 262        if (flag != 1) {
 263            env->CF = 1;
 264        }
 265        break;
 266    }
 267    env->ucf64.xregs[UC32_UCF64_FPSCR] = (env->CF << 29)
 268                    | (env->ucf64.xregs[UC32_UCF64_FPSCR] & 0x0fffffff);
 269}
 270
 271/* Helper routines to perform bitwise copies between float and int.  */
 272static inline float32 ucf64_itos(uint32_t i)
 273{
 274    union {
 275        uint32_t i;
 276        float32 s;
 277    } v;
 278
 279    v.i = i;
 280    return v.s;
 281}
 282
 283static inline uint32_t ucf64_stoi(float32 s)
 284{
 285    union {
 286        uint32_t i;
 287        float32 s;
 288    } v;
 289
 290    v.s = s;
 291    return v.i;
 292}
 293
 294/* Integer to float conversion.  */
 295float32 HELPER(ucf64_si2sf)(float32 x, CPUUniCore32State *env)
 296{
 297    return int32_to_float32(ucf64_stoi(x), &env->ucf64.fp_status);
 298}
 299
 300float64 HELPER(ucf64_si2df)(float32 x, CPUUniCore32State *env)
 301{
 302    return int32_to_float64(ucf64_stoi(x), &env->ucf64.fp_status);
 303}
 304
 305/* Float to integer conversion.  */
 306float32 HELPER(ucf64_sf2si)(float32 x, CPUUniCore32State *env)
 307{
 308    return ucf64_itos(float32_to_int32(x, &env->ucf64.fp_status));
 309}
 310
 311float32 HELPER(ucf64_df2si)(float64 x, CPUUniCore32State *env)
 312{
 313    return ucf64_itos(float64_to_int32(x, &env->ucf64.fp_status));
 314}
 315
 316/* floating point conversion */
 317float64 HELPER(ucf64_sf2df)(float32 x, CPUUniCore32State *env)
 318{
 319    return float32_to_float64(x, &env->ucf64.fp_status);
 320}
 321
 322float32 HELPER(ucf64_df2sf)(float64 x, CPUUniCore32State *env)
 323{
 324    return float64_to_float32(x, &env->ucf64.fp_status);
 325}
 326