1/* 2 * QEMU Xtensa CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * * Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * * Neither the name of the Open Source and Linux Lab nor the 15 * names of its contributors may be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 22 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 25 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29#ifndef QEMU_XTENSA_CPU_QOM_H 30#define QEMU_XTENSA_CPU_QOM_H 31 32#include "qom/cpu.h" 33#include "cpu.h" 34 35#define TYPE_XTENSA_CPU "xtensa-cpu" 36 37#define XTENSA_CPU_CLASS(class) \ 38 OBJECT_CLASS_CHECK(XtensaCPUClass, (class), TYPE_XTENSA_CPU) 39#define XTENSA_CPU(obj) \ 40 OBJECT_CHECK(XtensaCPU, (obj), TYPE_XTENSA_CPU) 41#define XTENSA_CPU_GET_CLASS(obj) \ 42 OBJECT_GET_CLASS(XtensaCPUClass, (obj), TYPE_XTENSA_CPU) 43 44/** 45 * XtensaCPUClass: 46 * @parent_realize: The parent class' realize handler. 47 * @parent_reset: The parent class' reset handler. 48 * @config: The CPU core configuration. 49 * 50 * An Xtensa CPU model. 51 */ 52typedef struct XtensaCPUClass { 53 /*< private >*/ 54 CPUClass parent_class; 55 /*< public >*/ 56 57 DeviceRealize parent_realize; 58 void (*parent_reset)(CPUState *cpu); 59 60 const XtensaConfig *config; 61} XtensaCPUClass; 62 63/** 64 * XtensaCPU: 65 * @env: #CPUXtensaState 66 * 67 * An Xtensa CPU. 68 */ 69typedef struct XtensaCPU { 70 /*< private >*/ 71 CPUState parent_obj; 72 /*< public >*/ 73 74 CPUXtensaState env; 75} XtensaCPU; 76 77static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) 78{ 79 return container_of(env, XtensaCPU, env); 80} 81 82#define ENV_GET_CPU(e) CPU(xtensa_env_get_cpu(e)) 83 84#define ENV_OFFSET offsetof(XtensaCPU, env) 85 86void xtensa_cpu_do_interrupt(CPUState *cpu); 87bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); 88void xtensa_cpu_do_unassigned_access(CPUState *cpu, hwaddr addr, 89 bool is_write, bool is_exec, int opaque, 90 unsigned size); 91void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, 92 fprintf_function cpu_fprintf, int flags); 93hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 94int xtensa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 95int xtensa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 96void xtensa_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, 97 int is_write, int is_user, uintptr_t retaddr); 98 99#endif 100