LXR qemu/tcg/sparc/tcg-target.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2008 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24#ifndef TCG_TARGET_SPARC 
  25#define TCG_TARGET_SPARC 1
  26
  27#define TCG_TARGET_REG_BITS 64
  28
  29#define TCG_TARGET_INSN_UNIT_SIZE 4
  30#define TCG_TARGET_TLB_DISPLACEMENT_BITS 32
  31#define TCG_TARGET_NB_REGS 32
  32
  33typedef enum {
  34    TCG_REG_G0 = 0,
  35    TCG_REG_G1,
  36    TCG_REG_G2,
  37    TCG_REG_G3,
  38    TCG_REG_G4,
  39    TCG_REG_G5,
  40    TCG_REG_G6,
  41    TCG_REG_G7,
  42    TCG_REG_O0,
  43    TCG_REG_O1,
  44    TCG_REG_O2,
  45    TCG_REG_O3,
  46    TCG_REG_O4,
  47    TCG_REG_O5,
  48    TCG_REG_O6,
  49    TCG_REG_O7,
  50    TCG_REG_L0,
  51    TCG_REG_L1,
  52    TCG_REG_L2,
  53    TCG_REG_L3,
  54    TCG_REG_L4,
  55    TCG_REG_L5,
  56    TCG_REG_L6,
  57    TCG_REG_L7,
  58    TCG_REG_I0,
  59    TCG_REG_I1,
  60    TCG_REG_I2,
  61    TCG_REG_I3,
  62    TCG_REG_I4,
  63    TCG_REG_I5,
  64    TCG_REG_I6,
  65    TCG_REG_I7,
  66} TCGReg;
  67
  68#define TCG_CT_CONST_S11  0x100
  69#define TCG_CT_CONST_S13  0x200
  70#define TCG_CT_CONST_ZERO 0x400
  71
  72/* used for function call generation */
  73#define TCG_REG_CALL_STACK TCG_REG_O6
  74
  75#ifdef __arch64__
  76#define TCG_TARGET_STACK_BIAS           2047
  77#define TCG_TARGET_STACK_ALIGN          16
  78#define TCG_TARGET_CALL_STACK_OFFSET    (128 + 6*8 + TCG_TARGET_STACK_BIAS)
  79#else
  80#define TCG_TARGET_STACK_BIAS           0
  81#define TCG_TARGET_STACK_ALIGN          8
  82#define TCG_TARGET_CALL_STACK_OFFSET    (64 + 4 + 6*4)
  83#endif
  84
  85#ifdef __arch64__
  86#define TCG_TARGET_EXTEND_ARGS 1
  87#endif
  88
  89#if defined(__VIS__) && __VIS__ >= 0x300
  90#define use_vis3_instructions  1
  91#else
  92extern bool use_vis3_instructions;
  93#endif
  94
  95/* optional instructions */
  96#define TCG_TARGET_HAS_div_i32          1
  97#define TCG_TARGET_HAS_rem_i32          0
  98#define TCG_TARGET_HAS_rot_i32          0
  99#define TCG_TARGET_HAS_ext8s_i32        0
 100#define TCG_TARGET_HAS_ext16s_i32       0
 101#define TCG_TARGET_HAS_ext8u_i32        0
 102#define TCG_TARGET_HAS_ext16u_i32       0
 103#define TCG_TARGET_HAS_bswap16_i32      0
 104#define TCG_TARGET_HAS_bswap32_i32      0
 105#define TCG_TARGET_HAS_neg_i32          1
 106#define TCG_TARGET_HAS_not_i32          1
 107#define TCG_TARGET_HAS_andc_i32         1
 108#define TCG_TARGET_HAS_orc_i32          1
 109#define TCG_TARGET_HAS_eqv_i32          0
 110#define TCG_TARGET_HAS_nand_i32         0
 111#define TCG_TARGET_HAS_nor_i32          0
 112#define TCG_TARGET_HAS_deposit_i32      0
 113#define TCG_TARGET_HAS_movcond_i32      1
 114#define TCG_TARGET_HAS_add2_i32         1
 115#define TCG_TARGET_HAS_sub2_i32         1
 116#define TCG_TARGET_HAS_mulu2_i32        1
 117#define TCG_TARGET_HAS_muls2_i32        1
 118#define TCG_TARGET_HAS_muluh_i32        0
 119#define TCG_TARGET_HAS_mulsh_i32        0
 120
 121#define TCG_TARGET_HAS_extrl_i64_i32    1
 122#define TCG_TARGET_HAS_extrh_i64_i32    1
 123#define TCG_TARGET_HAS_div_i64          1
 124#define TCG_TARGET_HAS_rem_i64          0
 125#define TCG_TARGET_HAS_rot_i64          0
 126#define TCG_TARGET_HAS_ext8s_i64        0
 127#define TCG_TARGET_HAS_ext16s_i64       0
 128#define TCG_TARGET_HAS_ext32s_i64       1
 129#define TCG_TARGET_HAS_ext8u_i64        0
 130#define TCG_TARGET_HAS_ext16u_i64       0
 131#define TCG_TARGET_HAS_ext32u_i64       1
 132#define TCG_TARGET_HAS_bswap16_i64      0
 133#define TCG_TARGET_HAS_bswap32_i64      0
 134#define TCG_TARGET_HAS_bswap64_i64      0
 135#define TCG_TARGET_HAS_neg_i64          1
 136#define TCG_TARGET_HAS_not_i64          1
 137#define TCG_TARGET_HAS_andc_i64         1
 138#define TCG_TARGET_HAS_orc_i64          1
 139#define TCG_TARGET_HAS_eqv_i64          0
 140#define TCG_TARGET_HAS_nand_i64         0
 141#define TCG_TARGET_HAS_nor_i64          0
 142#define TCG_TARGET_HAS_deposit_i64      0
 143#define TCG_TARGET_HAS_movcond_i64      1
 144#define TCG_TARGET_HAS_add2_i64         1
 145#define TCG_TARGET_HAS_sub2_i64         1
 146#define TCG_TARGET_HAS_mulu2_i64        0
 147#define TCG_TARGET_HAS_muls2_i64        0
 148#define TCG_TARGET_HAS_muluh_i64        use_vis3_instructions
 149#define TCG_TARGET_HAS_mulsh_i64        0
 150
 151#define TCG_AREG0 TCG_REG_I0
 152
 153static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 154{
 155    uintptr_t p;
 156    for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
 157        __asm__ __volatile__("flush\t%0" : : "r" (p));
 158    }
 159}
 160
 161#endif
 162