LXR qemu/tcg/tcg-opc.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2008 Fabrice Bellard
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25/*
  26 * DEF(name, oargs, iargs, cargs, flags)
  27 */
  28
  29/* predefined ops */
  30DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
  31DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
  32
  33/* variable number of parameters */
  34DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
  35
  36DEF(br, 0, 0, 1, TCG_OPF_BB_END)
  37
  38#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
  39#if TCG_TARGET_REG_BITS == 32
  40# define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
  41#else
  42# define IMPL64  TCG_OPF_64BIT
  43#endif
  44
  45DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
  46DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
  47DEF(setcond_i32, 1, 2, 1, 0)
  48DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
  49/* load/store */
  50DEF(ld8u_i32, 1, 1, 1, 0)
  51DEF(ld8s_i32, 1, 1, 1, 0)
  52DEF(ld16u_i32, 1, 1, 1, 0)
  53DEF(ld16s_i32, 1, 1, 1, 0)
  54DEF(ld_i32, 1, 1, 1, 0)
  55DEF(st8_i32, 0, 2, 1, 0)
  56DEF(st16_i32, 0, 2, 1, 0)
  57DEF(st_i32, 0, 2, 1, 0)
  58/* arith */
  59DEF(add_i32, 1, 2, 0, 0)
  60DEF(sub_i32, 1, 2, 0, 0)
  61DEF(mul_i32, 1, 2, 0, 0)
  62DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  63DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
  64DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  65DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
  66DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  67DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
  68DEF(and_i32, 1, 2, 0, 0)
  69DEF(or_i32, 1, 2, 0, 0)
  70DEF(xor_i32, 1, 2, 0, 0)
  71/* shifts/rotates */
  72DEF(shl_i32, 1, 2, 0, 0)
  73DEF(shr_i32, 1, 2, 0, 0)
  74DEF(sar_i32, 1, 2, 0, 0)
  75DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  76DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
  77DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
  78
  79DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
  80
  81DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
  82DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
  83DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
  84DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
  85DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
  86DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
  87DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
  88DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
  89
  90DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
  91DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
  92DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
  93DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
  94DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
  95DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
  96DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
  97DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
  98DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
  99DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
 100DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
 101DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
 102DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
 103
 104DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 105DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
 106DEF(setcond_i64, 1, 2, 1, IMPL64)
 107DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
 108/* load/store */
 109DEF(ld8u_i64, 1, 1, 1, IMPL64)
 110DEF(ld8s_i64, 1, 1, 1, IMPL64)
 111DEF(ld16u_i64, 1, 1, 1, IMPL64)
 112DEF(ld16s_i64, 1, 1, 1, IMPL64)
 113DEF(ld32u_i64, 1, 1, 1, IMPL64)
 114DEF(ld32s_i64, 1, 1, 1, IMPL64)
 115DEF(ld_i64, 1, 1, 1, IMPL64)
 116DEF(st8_i64, 0, 2, 1, IMPL64)
 117DEF(st16_i64, 0, 2, 1, IMPL64)
 118DEF(st32_i64, 0, 2, 1, IMPL64)
 119DEF(st_i64, 0, 2, 1, IMPL64)
 120/* arith */
 121DEF(add_i64, 1, 2, 0, IMPL64)
 122DEF(sub_i64, 1, 2, 0, IMPL64)
 123DEF(mul_i64, 1, 2, 0, IMPL64)
 124DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 125DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
 126DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 127DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
 128DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 129DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
 130DEF(and_i64, 1, 2, 0, IMPL64)
 131DEF(or_i64, 1, 2, 0, IMPL64)
 132DEF(xor_i64, 1, 2, 0, IMPL64)
 133/* shifts/rotates */
 134DEF(shl_i64, 1, 2, 0, IMPL64)
 135DEF(shr_i64, 1, 2, 0, IMPL64)
 136DEF(sar_i64, 1, 2, 0, IMPL64)
 137DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 138DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
 139DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
 140
 141/* size changing ops */
 142DEF(ext_i32_i64, 1, 1, 0, IMPL64)
 143DEF(extu_i32_i64, 1, 1, 0, IMPL64)
 144DEF(extrl_i64_i32, 1, 1, 0,
 145    IMPL(TCG_TARGET_HAS_extrl_i64_i32)
 146    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 147DEF(extrh_i64_i32, 1, 1, 0,
 148    IMPL(TCG_TARGET_HAS_extrh_i64_i32)
 149    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
 150
 151DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
 152DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
 153DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
 154DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
 155DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
 156DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
 157DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
 158DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
 159DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
 160DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
 161DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
 162DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
 163DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
 164DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
 165DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
 166DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
 167DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
 168
 169DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
 170DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
 171DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
 172DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
 173DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
 174DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
 175
 176#define TLADDR_ARGS  (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
 177#define DATA64_ARGS  (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
 178
 179/* QEMU specific */
 180DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
 181    TCG_OPF_NOT_PRESENT)
 182DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
 183DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
 184
 185DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
 186    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 187DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
 188    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
 189DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
 190    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 191DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
 192    TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
 193
 194#undef TLADDR_ARGS
 195#undef DATA64_ARGS
 196#undef IMPL
 197#undef IMPL64
 198#undef DEF
 199