LXR qemu/tests/i440fx-test.c

   1/*
   2 * qtest I440FX test case
   3 *
   4 * Copyright IBM, Corp. 2012-2013
   5 * Copyright Red Hat, Inc. 2013
   6 *
   7 * Authors:
   8 *  Anthony Liguori   <aliguori@us.ibm.com>
   9 *  Laszlo Ersek      <lersek@redhat.com>
  10 *
  11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12 * See the COPYING file in the top-level directory.
  13 */
  14
  15#include "qemu/osdep.h"
  16#include <glib.h>
  17#include <sys/mman.h>
  18
  19#include "libqtest.h"
  20#include "libqos/pci.h"
  21#include "libqos/pci-pc.h"
  22#include "hw/pci/pci_regs.h"
  23
  24#define BROKEN 1
  25
  26typedef struct TestData
  27{
  28    int num_cpus;
  29} TestData;
  30
  31typedef struct FirmwareTestFixture {
  32    /* decides whether we're testing -bios or -pflash */
  33    bool is_bios;
  34} FirmwareTestFixture;
  35
  36static QPCIBus *test_start_get_bus(const TestData *s)
  37{
  38    char *cmdline;
  39
  40    cmdline = g_strdup_printf("-smp %d", s->num_cpus);
  41    qtest_start(cmdline);
  42    g_free(cmdline);
  43    return qpci_init_pc();
  44}
  45
  46static void test_i440fx_defaults(gconstpointer opaque)
  47{
  48    const TestData *s = opaque;
  49    QPCIBus *bus;
  50    QPCIDevice *dev;
  51    uint32_t value;
  52
  53    bus = test_start_get_bus(s);
  54    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
  55    g_assert(dev != NULL);
  56
  57    /* 3.2.2 */
  58    g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  59    /* 3.2.3 */
  60    g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  61#ifndef BROKEN
  62    /* 3.2.4 */
  63    g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  64    /* 3.2.5 */
  65    g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  66#endif
  67    /* 3.2.7 */
  68    g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  69    g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  70    /* 3.2.8 */
  71    g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  72    /* 3.2.9 */
  73    g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  74    /* 3.2.10 */
  75    g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  76
  77    /* 3.2.11 */
  78    value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  79    if (s->num_cpus == 1) { /* WPE */
  80        g_assert(!(value & (1 << 15)));
  81    } else {
  82        g_assert((value & (1 << 15)));
  83    }
  84
  85    g_assert(!(value & (1 << 6))); /* EPTE */
  86
  87    /* 3.2.12 */
  88    g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  89    /* 3.2.13 */
  90#ifndef BROKEN
  91    g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  92#endif
  93    /* 3.2.14 */
  94    g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
  95    /* 3.2.15 */
  96    g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
  97#ifndef BROKEN
  98    /* 3.2.16 */
  99    g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
 100    /* 3.2.17 */
 101    g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
 102#endif
 103    /* 3.2.18 */
 104    g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
 105    g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
 106    g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
 107    g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
 108    g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
 109    g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
 110    g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
 111#ifndef BROKEN
 112    /* 3.2.19 */
 113    g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 114    g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 115    g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 116    g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 117    g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 118    g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 119    g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 120    g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 121#endif
 122    /* 3.2.20 */
 123    g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 124    /* 3.2.21 */
 125    g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 126#ifndef BROKEN
 127    /* 3.2.22 */
 128    g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 129#endif
 130    /* 3.2.23 */
 131    g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 132    /* 3.2.24 */
 133    g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 134    /* 3.2.25 */
 135    g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 136    /* 3.2.26 */
 137    g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 138
 139    qtest_end();
 140}
 141
 142#define PAM_RE 1
 143#define PAM_WE 2
 144
 145static void pam_set(QPCIDevice *dev, int index, int flags)
 146{
 147    int regno = 0x59 + (index / 2);
 148    uint8_t reg;
 149
 150    reg = qpci_config_readb(dev, regno);
 151    if (index & 1) {
 152        reg = (reg & 0x0F) | (flags << 4);
 153    } else {
 154        reg = (reg & 0xF0) | flags;
 155    }
 156    qpci_config_writeb(dev, regno, reg);
 157}
 158
 159static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 160{
 161    uint32_t size = end - start + 1;
 162    gboolean ret = TRUE;
 163    uint8_t *data;
 164    int i;
 165
 166    data = g_malloc0(size);
 167    memread(start, data, size);
 168
 169    g_test_message("verify_area: data[0] = 0x%x", data[0]);
 170
 171    for (i = 0; i < size; i++) {
 172        if (data[i] != value) {
 173            ret = FALSE;
 174            break;
 175        }
 176    }
 177
 178    g_free(data);
 179
 180    return ret;
 181}
 182
 183static void write_area(uint32_t start, uint32_t end, uint8_t value)
 184{
 185    uint32_t size = end - start + 1;
 186    uint8_t *data;
 187
 188    data = g_malloc(size);
 189    memset(data, value, size);
 190    memwrite(start, data, size);
 191
 192    g_free(data);
 193}
 194
 195static void test_i440fx_pam(gconstpointer opaque)
 196{
 197    const TestData *s = opaque;
 198    QPCIBus *bus;
 199    QPCIDevice *dev;
 200    int i;
 201    static struct {
 202        uint32_t start;
 203        uint32_t end;
 204    } pam_area[] = {
 205        { 0, 0 },             /* Reserved */
 206        { 0xF0000, 0xFFFFF }, /* BIOS Area */
 207        { 0xC0000, 0xC3FFF }, /* Option ROM */
 208        { 0xC4000, 0xC7FFF }, /* Option ROM */
 209        { 0xC8000, 0xCBFFF }, /* Option ROM */
 210        { 0xCC000, 0xCFFFF }, /* Option ROM */
 211        { 0xD0000, 0xD3FFF }, /* Option ROM */
 212        { 0xD4000, 0xD7FFF }, /* Option ROM */
 213        { 0xD8000, 0xDBFFF }, /* Option ROM */
 214        { 0xDC000, 0xDFFFF }, /* Option ROM */
 215        { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 216        { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 217        { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 218        { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 219    };
 220
 221    bus = test_start_get_bus(s);
 222    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
 223    g_assert(dev != NULL);
 224
 225    for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 226        if (pam_area[i].start == pam_area[i].end) {
 227            continue;
 228        }
 229
 230        g_test_message("Checking area 0x%05x..0x%05x",
 231                       pam_area[i].start, pam_area[i].end);
 232        /* Switch to RE for the area */
 233        pam_set(dev, i, PAM_RE);
 234        /* Verify the RAM is all zeros */
 235        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 236
 237        /* Switch to WE for the area */
 238        pam_set(dev, i, PAM_RE | PAM_WE);
 239        /* Write out a non-zero mask to the full area */
 240        write_area(pam_area[i].start, pam_area[i].end, 0x42);
 241
 242#ifndef BROKEN
 243        /* QEMU only supports a limited form of PAM */
 244
 245        /* Switch to !RE for the area */
 246        pam_set(dev, i, PAM_WE);
 247        /* Verify the area is not our mask */
 248        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 249#endif
 250
 251        /* Verify the area is our new mask */
 252        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 253
 254        /* Write out a new mask */
 255        write_area(pam_area[i].start, pam_area[i].end, 0x82);
 256
 257#ifndef BROKEN
 258        /* QEMU only supports a limited form of PAM */
 259
 260        /* Verify the area is not our mask */
 261        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 262
 263        /* Switch to RE for the area */
 264        pam_set(dev, i, PAM_RE | PAM_WE);
 265#endif
 266        /* Verify the area is our new mask */
 267        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 268
 269        /* Reset area */
 270        pam_set(dev, i, 0);
 271
 272        /* Verify the area is not our new mask */
 273        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 274    }
 275    qtest_end();
 276}
 277
 278#define BLOB_SIZE ((size_t)65536)
 279#define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))
 280
 281/* Create a blob file, and return its absolute pathname as a dynamically
 282 * allocated string.
 283 * The file is closed before the function returns.
 284 * In case of error, NULL is returned. The function prints the error message.
 285 */
 286static char *create_blob_file(void)
 287{
 288    int ret, fd;
 289    char *pathname;
 290    GError *error = NULL;
 291
 292    ret = -1;
 293    fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
 294    if (fd == -1) {
 295        fprintf(stderr, "unable to create blob file: %s\n", error->message);
 296        g_error_free(error);
 297    } else {
 298        if (ftruncate(fd, BLOB_SIZE) == -1) {
 299            fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
 300                    BLOB_SIZE, strerror(errno));
 301        } else {
 302            void *buf;
 303
 304            buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
 305            if (buf == MAP_FAILED) {
 306                fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
 307                        strerror(errno));
 308            } else {
 309                size_t i;
 310
 311                for (i = 0; i < BLOB_SIZE; ++i) {
 312                    ((uint8_t *)buf)[i] = i;
 313                }
 314                munmap(buf, BLOB_SIZE);
 315                ret = 0;
 316            }
 317        }
 318        close(fd);
 319        if (ret == -1) {
 320            unlink(pathname);
 321            g_free(pathname);
 322        }
 323    }
 324
 325    return ret == -1 ? NULL : pathname;
 326}
 327
 328static void test_i440fx_firmware(FirmwareTestFixture *fixture,
 329                                 gconstpointer user_data)
 330{
 331    char *fw_pathname, *cmdline;
 332    uint8_t *buf;
 333    size_t i, isa_bios_size;
 334
 335    fw_pathname = create_blob_file();
 336    g_assert(fw_pathname != NULL);
 337
 338    /* Better hope the user didn't put metacharacters in TMPDIR and co. */
 339    cmdline = g_strdup_printf("-S %s%s", fixture->is_bios
 340                                         ? "-bios "
 341                                         : "-drive if=pflash,format=raw,file=",
 342                              fw_pathname);
 343    g_test_message("qemu cmdline: %s", cmdline);
 344    qtest_start(cmdline);
 345    g_free(cmdline);
 346
 347    /* QEMU has loaded the firmware (because qtest_start() only returns after
 348     * the QMP handshake completes). We must unlink the firmware blob right
 349     * here, because any assertion firing below would leak it in the
 350     * filesystem. This is also the reason why we recreate the blob every time
 351     * this function is invoked.
 352     */
 353    unlink(fw_pathname);
 354    g_free(fw_pathname);
 355
 356    /* check below 4G */
 357    buf = g_malloc0(BLOB_SIZE);
 358    memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
 359    for (i = 0; i < BLOB_SIZE; ++i) {
 360        g_assert_cmphex(buf[i], ==, (uint8_t)i);
 361    }
 362
 363    /* check in ISA space too */
 364    memset(buf, 0, BLOB_SIZE);
 365    isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
 366    memread(0x100000 - isa_bios_size, buf, isa_bios_size);
 367    for (i = 0; i < isa_bios_size; ++i) {
 368        g_assert_cmphex(buf[i], ==,
 369                        (uint8_t)((BLOB_SIZE - isa_bios_size) + i));
 370    }
 371
 372    g_free(buf);
 373    qtest_end();
 374}
 375
 376static void add_firmware_test(const char *testpath,
 377                              void (*setup_fixture)(FirmwareTestFixture *f,
 378                                                    gconstpointer test_data))
 379{
 380    qtest_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
 381              test_i440fx_firmware, NULL);
 382}
 383
 384static void request_bios(FirmwareTestFixture *fixture,
 385                         gconstpointer user_data)
 386{
 387    fixture->is_bios = true;
 388}
 389
 390static void request_pflash(FirmwareTestFixture *fixture,
 391                           gconstpointer user_data)
 392{
 393    fixture->is_bios = false;
 394}
 395
 396int main(int argc, char **argv)
 397{
 398    TestData data;
 399    int ret;
 400
 401    g_test_init(&argc, &argv, NULL);
 402
 403    data.num_cpus = 1;
 404
 405    qtest_add_data_func("i440fx/defaults", &data, test_i440fx_defaults);
 406    qtest_add_data_func("i440fx/pam", &data, test_i440fx_pam);
 407    add_firmware_test("i440fx/firmware/bios", request_bios);
 408    add_firmware_test("i440fx/firmware/pflash", request_pflash);
 409
 410    ret = g_test_run();
 411    return ret;
 412}
 413