1#ifndef HW_NVME_H
2#define HW_NVME_H
3#include "qemu/cutils.h"
4
5typedef struct NvmeBar {
6 uint64_t cap;
7 uint32_t vs;
8 uint32_t intms;
9 uint32_t intmc;
10 uint32_t cc;
11 uint32_t rsvd1;
12 uint32_t csts;
13 uint32_t nssrc;
14 uint32_t aqa;
15 uint64_t asq;
16 uint64_t acq;
17} NvmeBar;
18
19enum NvmeCapShift {
20 CAP_MQES_SHIFT = 0,
21 CAP_CQR_SHIFT = 16,
22 CAP_AMS_SHIFT = 17,
23 CAP_TO_SHIFT = 24,
24 CAP_DSTRD_SHIFT = 32,
25 CAP_NSSRS_SHIFT = 33,
26 CAP_CSS_SHIFT = 37,
27 CAP_MPSMIN_SHIFT = 48,
28 CAP_MPSMAX_SHIFT = 52,
29};
30
31enum NvmeCapMask {
32 CAP_MQES_MASK = 0xffff,
33 CAP_CQR_MASK = 0x1,
34 CAP_AMS_MASK = 0x3,
35 CAP_TO_MASK = 0xff,
36 CAP_DSTRD_MASK = 0xf,
37 CAP_NSSRS_MASK = 0x1,
38 CAP_CSS_MASK = 0xff,
39 CAP_MPSMIN_MASK = 0xf,
40 CAP_MPSMAX_MASK = 0xf,
41};
42
43#define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK)
44#define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK)
45#define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK)
46#define NVME_CAP_TO(cap) (((cap) >> CAP_TO_SHIFT) & CAP_TO_MASK)
47#define NVME_CAP_DSTRD(cap) (((cap) >> CAP_DSTRD_SHIFT) & CAP_DSTRD_MASK)
48#define NVME_CAP_NSSRS(cap) (((cap) >> CAP_NSSRS_SHIFT) & CAP_NSSRS_MASK)
49#define NVME_CAP_CSS(cap) (((cap) >> CAP_CSS_SHIFT) & CAP_CSS_MASK)
50#define NVME_CAP_MPSMIN(cap)(((cap) >> CAP_MPSMIN_SHIFT) & CAP_MPSMIN_MASK)
51#define NVME_CAP_MPSMAX(cap)(((cap) >> CAP_MPSMAX_SHIFT) & CAP_MPSMAX_MASK)
52
53#define NVME_CAP_SET_MQES(cap, val) (cap |= (uint64_t)(val & CAP_MQES_MASK) \
54 << CAP_MQES_SHIFT)
55#define NVME_CAP_SET_CQR(cap, val) (cap |= (uint64_t)(val & CAP_CQR_MASK) \
56 << CAP_CQR_SHIFT)
57#define NVME_CAP_SET_AMS(cap, val) (cap |= (uint64_t)(val & CAP_AMS_MASK) \
58 << CAP_AMS_SHIFT)
59#define NVME_CAP_SET_TO(cap, val) (cap |= (uint64_t)(val & CAP_TO_MASK) \
60 << CAP_TO_SHIFT)
61#define NVME_CAP_SET_DSTRD(cap, val) (cap |= (uint64_t)(val & CAP_DSTRD_MASK) \
62 << CAP_DSTRD_SHIFT)
63#define NVME_CAP_SET_NSSRS(cap, val) (cap |= (uint64_t)(val & CAP_NSSRS_MASK) \
64 << CAP_NSSRS_SHIFT)
65#define NVME_CAP_SET_CSS(cap, val) (cap |= (uint64_t)(val & CAP_CSS_MASK) \
66 << CAP_CSS_SHIFT)
67#define NVME_CAP_SET_MPSMIN(cap, val) (cap |= (uint64_t)(val & CAP_MPSMIN_MASK)\
68 << CAP_MPSMIN_SHIFT)
69#define NVME_CAP_SET_MPSMAX(cap, val) (cap |= (uint64_t)(val & CAP_MPSMAX_MASK)\
70 << CAP_MPSMAX_SHIFT)
71
72enum NvmeCcShift {
73 CC_EN_SHIFT = 0,
74 CC_CSS_SHIFT = 4,
75 CC_MPS_SHIFT = 7,
76 CC_AMS_SHIFT = 11,
77 CC_SHN_SHIFT = 14,
78 CC_IOSQES_SHIFT = 16,
79 CC_IOCQES_SHIFT = 20,
80};
81
82enum NvmeCcMask {
83 CC_EN_MASK = 0x1,
84 CC_CSS_MASK = 0x7,
85 CC_MPS_MASK = 0xf,
86 CC_AMS_MASK = 0x7,
87 CC_SHN_MASK = 0x3,
88 CC_IOSQES_MASK = 0xf,
89 CC_IOCQES_MASK = 0xf,
90};
91
92#define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK)
93#define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK)
94#define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK)
95#define NVME_CC_AMS(cc) ((cc >> CC_AMS_SHIFT) & CC_AMS_MASK)
96#define NVME_CC_SHN(cc) ((cc >> CC_SHN_SHIFT) & CC_SHN_MASK)
97#define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK)
98#define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK)
99
100enum NvmeCstsShift {
101 CSTS_RDY_SHIFT = 0,
102 CSTS_CFS_SHIFT = 1,
103 CSTS_SHST_SHIFT = 2,
104 CSTS_NSSRO_SHIFT = 4,
105};
106
107enum NvmeCstsMask {
108 CSTS_RDY_MASK = 0x1,
109 CSTS_CFS_MASK = 0x1,
110 CSTS_SHST_MASK = 0x3,
111 CSTS_NSSRO_MASK = 0x1,
112};
113
114enum NvmeCsts {
115 NVME_CSTS_READY = 1 << CSTS_RDY_SHIFT,
116 NVME_CSTS_FAILED = 1 << CSTS_CFS_SHIFT,
117 NVME_CSTS_SHST_NORMAL = 0 << CSTS_SHST_SHIFT,
118 NVME_CSTS_SHST_PROGRESS = 1 << CSTS_SHST_SHIFT,
119 NVME_CSTS_SHST_COMPLETE = 2 << CSTS_SHST_SHIFT,
120 NVME_CSTS_NSSRO = 1 << CSTS_NSSRO_SHIFT,
121};
122
123#define NVME_CSTS_RDY(csts) ((csts >> CSTS_RDY_SHIFT) & CSTS_RDY_MASK)
124#define NVME_CSTS_CFS(csts) ((csts >> CSTS_CFS_SHIFT) & CSTS_CFS_MASK)
125#define NVME_CSTS_SHST(csts) ((csts >> CSTS_SHST_SHIFT) & CSTS_SHST_MASK)
126#define NVME_CSTS_NSSRO(csts) ((csts >> CSTS_NSSRO_SHIFT) & CSTS_NSSRO_MASK)
127
128enum NvmeAqaShift {
129 AQA_ASQS_SHIFT = 0,
130 AQA_ACQS_SHIFT = 16,
131};
132
133enum NvmeAqaMask {
134 AQA_ASQS_MASK = 0xfff,
135 AQA_ACQS_MASK = 0xfff,
136};
137
138#define NVME_AQA_ASQS(aqa) ((aqa >> AQA_ASQS_SHIFT) & AQA_ASQS_MASK)
139#define NVME_AQA_ACQS(aqa) ((aqa >> AQA_ACQS_SHIFT) & AQA_ACQS_MASK)
140
141typedef struct NvmeCmd {
142 uint8_t opcode;
143 uint8_t fuse;
144 uint16_t cid;
145 uint32_t nsid;
146 uint64_t res1;
147 uint64_t mptr;
148 uint64_t prp1;
149 uint64_t prp2;
150 uint32_t cdw10;
151 uint32_t cdw11;
152 uint32_t cdw12;
153 uint32_t cdw13;
154 uint32_t cdw14;
155 uint32_t cdw15;
156} NvmeCmd;
157
158enum NvmeAdminCommands {
159 NVME_ADM_CMD_DELETE_SQ = 0x00,
160 NVME_ADM_CMD_CREATE_SQ = 0x01,
161 NVME_ADM_CMD_GET_LOG_PAGE = 0x02,
162 NVME_ADM_CMD_DELETE_CQ = 0x04,
163 NVME_ADM_CMD_CREATE_CQ = 0x05,
164 NVME_ADM_CMD_IDENTIFY = 0x06,
165 NVME_ADM_CMD_ABORT = 0x08,
166 NVME_ADM_CMD_SET_FEATURES = 0x09,
167 NVME_ADM_CMD_GET_FEATURES = 0x0a,
168 NVME_ADM_CMD_ASYNC_EV_REQ = 0x0c,
169 NVME_ADM_CMD_ACTIVATE_FW = 0x10,
170 NVME_ADM_CMD_DOWNLOAD_FW = 0x11,
171 NVME_ADM_CMD_FORMAT_NVM = 0x80,
172 NVME_ADM_CMD_SECURITY_SEND = 0x81,
173 NVME_ADM_CMD_SECURITY_RECV = 0x82,
174};
175
176enum NvmeIoCommands {
177 NVME_CMD_FLUSH = 0x00,
178 NVME_CMD_WRITE = 0x01,
179 NVME_CMD_READ = 0x02,
180 NVME_CMD_WRITE_UNCOR = 0x04,
181 NVME_CMD_COMPARE = 0x05,
182 NVME_CMD_DSM = 0x09,
183};
184
185typedef struct NvmeDeleteQ {
186 uint8_t opcode;
187 uint8_t flags;
188 uint16_t cid;
189 uint32_t rsvd1[9];
190 uint16_t qid;
191 uint16_t rsvd10;
192 uint32_t rsvd11[5];
193} NvmeDeleteQ;
194
195typedef struct NvmeCreateCq {
196 uint8_t opcode;
197 uint8_t flags;
198 uint16_t cid;
199 uint32_t rsvd1[5];
200 uint64_t prp1;
201 uint64_t rsvd8;
202 uint16_t cqid;
203 uint16_t qsize;
204 uint16_t cq_flags;
205 uint16_t irq_vector;
206 uint32_t rsvd12[4];
207} NvmeCreateCq;
208
209#define NVME_CQ_FLAGS_PC(cq_flags) (cq_flags & 0x1)
210#define NVME_CQ_FLAGS_IEN(cq_flags) ((cq_flags >> 1) & 0x1)
211
212typedef struct NvmeCreateSq {
213 uint8_t opcode;
214 uint8_t flags;
215 uint16_t cid;
216 uint32_t rsvd1[5];
217 uint64_t prp1;
218 uint64_t rsvd8;
219 uint16_t sqid;
220 uint16_t qsize;
221 uint16_t sq_flags;
222 uint16_t cqid;
223 uint32_t rsvd12[4];
224} NvmeCreateSq;
225
226#define NVME_SQ_FLAGS_PC(sq_flags) (sq_flags & 0x1)
227#define NVME_SQ_FLAGS_QPRIO(sq_flags) ((sq_flags >> 1) & 0x3)
228
229enum NvmeQueueFlags {
230 NVME_Q_PC = 1,
231 NVME_Q_PRIO_URGENT = 0,
232 NVME_Q_PRIO_HIGH = 1,
233 NVME_Q_PRIO_NORMAL = 2,
234 NVME_Q_PRIO_LOW = 3,
235};
236
237typedef struct NvmeIdentify {
238 uint8_t opcode;
239 uint8_t flags;
240 uint16_t cid;
241 uint32_t nsid;
242 uint64_t rsvd2[2];
243 uint64_t prp1;
244 uint64_t prp2;
245 uint32_t cns;
246 uint32_t rsvd11[5];
247} NvmeIdentify;
248
249typedef struct NvmeRwCmd {
250 uint8_t opcode;
251 uint8_t flags;
252 uint16_t cid;
253 uint32_t nsid;
254 uint64_t rsvd2;
255 uint64_t mptr;
256 uint64_t prp1;
257 uint64_t prp2;
258 uint64_t slba;
259 uint16_t nlb;
260 uint16_t control;
261 uint32_t dsmgmt;
262 uint32_t reftag;
263 uint16_t apptag;
264 uint16_t appmask;
265} NvmeRwCmd;
266
267enum {
268 NVME_RW_LR = 1 << 15,
269 NVME_RW_FUA = 1 << 14,
270 NVME_RW_DSM_FREQ_UNSPEC = 0,
271 NVME_RW_DSM_FREQ_TYPICAL = 1,
272 NVME_RW_DSM_FREQ_RARE = 2,
273 NVME_RW_DSM_FREQ_READS = 3,
274 NVME_RW_DSM_FREQ_WRITES = 4,
275 NVME_RW_DSM_FREQ_RW = 5,
276 NVME_RW_DSM_FREQ_ONCE = 6,
277 NVME_RW_DSM_FREQ_PREFETCH = 7,
278 NVME_RW_DSM_FREQ_TEMP = 8,
279 NVME_RW_DSM_LATENCY_NONE = 0 << 4,
280 NVME_RW_DSM_LATENCY_IDLE = 1 << 4,
281 NVME_RW_DSM_LATENCY_NORM = 2 << 4,
282 NVME_RW_DSM_LATENCY_LOW = 3 << 4,
283 NVME_RW_DSM_SEQ_REQ = 1 << 6,
284 NVME_RW_DSM_COMPRESSED = 1 << 7,
285 NVME_RW_PRINFO_PRACT = 1 << 13,
286 NVME_RW_PRINFO_PRCHK_GUARD = 1 << 12,
287 NVME_RW_PRINFO_PRCHK_APP = 1 << 11,
288 NVME_RW_PRINFO_PRCHK_REF = 1 << 10,
289};
290
291typedef struct NvmeDsmCmd {
292 uint8_t opcode;
293 uint8_t flags;
294 uint16_t cid;
295 uint32_t nsid;
296 uint64_t rsvd2[2];
297 uint64_t prp1;
298 uint64_t prp2;
299 uint32_t nr;
300 uint32_t attributes;
301 uint32_t rsvd12[4];
302} NvmeDsmCmd;
303
304enum {
305 NVME_DSMGMT_IDR = 1 << 0,
306 NVME_DSMGMT_IDW = 1 << 1,
307 NVME_DSMGMT_AD = 1 << 2,
308};
309
310typedef struct NvmeDsmRange {
311 uint32_t cattr;
312 uint32_t nlb;
313 uint64_t slba;
314} NvmeDsmRange;
315
316enum NvmeAsyncEventRequest {
317 NVME_AER_TYPE_ERROR = 0,
318 NVME_AER_TYPE_SMART = 1,
319 NVME_AER_TYPE_IO_SPECIFIC = 6,
320 NVME_AER_TYPE_VENDOR_SPECIFIC = 7,
321 NVME_AER_INFO_ERR_INVALID_SQ = 0,
322 NVME_AER_INFO_ERR_INVALID_DB = 1,
323 NVME_AER_INFO_ERR_DIAG_FAIL = 2,
324 NVME_AER_INFO_ERR_PERS_INTERNAL_ERR = 3,
325 NVME_AER_INFO_ERR_TRANS_INTERNAL_ERR = 4,
326 NVME_AER_INFO_ERR_FW_IMG_LOAD_ERR = 5,
327 NVME_AER_INFO_SMART_RELIABILITY = 0,
328 NVME_AER_INFO_SMART_TEMP_THRESH = 1,
329 NVME_AER_INFO_SMART_SPARE_THRESH = 2,
330};
331
332typedef struct NvmeAerResult {
333 uint8_t event_type;
334 uint8_t event_info;
335 uint8_t log_page;
336 uint8_t resv;
337} NvmeAerResult;
338
339typedef struct NvmeCqe {
340 uint32_t result;
341 uint32_t rsvd;
342 uint16_t sq_head;
343 uint16_t sq_id;
344 uint16_t cid;
345 uint16_t status;
346} NvmeCqe;
347
348enum NvmeStatusCodes {
349 NVME_SUCCESS = 0x0000,
350 NVME_INVALID_OPCODE = 0x0001,
351 NVME_INVALID_FIELD = 0x0002,
352 NVME_CID_CONFLICT = 0x0003,
353 NVME_DATA_TRAS_ERROR = 0x0004,
354 NVME_POWER_LOSS_ABORT = 0x0005,
355 NVME_INTERNAL_DEV_ERROR = 0x0006,
356 NVME_CMD_ABORT_REQ = 0x0007,
357 NVME_CMD_ABORT_SQ_DEL = 0x0008,
358 NVME_CMD_ABORT_FAILED_FUSE = 0x0009,
359 NVME_CMD_ABORT_MISSING_FUSE = 0x000a,
360 NVME_INVALID_NSID = 0x000b,
361 NVME_CMD_SEQ_ERROR = 0x000c,
362 NVME_LBA_RANGE = 0x0080,
363 NVME_CAP_EXCEEDED = 0x0081,
364 NVME_NS_NOT_READY = 0x0082,
365 NVME_NS_RESV_CONFLICT = 0x0083,
366 NVME_INVALID_CQID = 0x0100,
367 NVME_INVALID_QID = 0x0101,
368 NVME_MAX_QSIZE_EXCEEDED = 0x0102,
369 NVME_ACL_EXCEEDED = 0x0103,
370 NVME_RESERVED = 0x0104,
371 NVME_AER_LIMIT_EXCEEDED = 0x0105,
372 NVME_INVALID_FW_SLOT = 0x0106,
373 NVME_INVALID_FW_IMAGE = 0x0107,
374 NVME_INVALID_IRQ_VECTOR = 0x0108,
375 NVME_INVALID_LOG_ID = 0x0109,
376 NVME_INVALID_FORMAT = 0x010a,
377 NVME_FW_REQ_RESET = 0x010b,
378 NVME_INVALID_QUEUE_DEL = 0x010c,
379 NVME_FID_NOT_SAVEABLE = 0x010d,
380 NVME_FID_NOT_NSID_SPEC = 0x010f,
381 NVME_FW_REQ_SUSYSTEM_RESET = 0x0110,
382 NVME_CONFLICTING_ATTRS = 0x0180,
383 NVME_INVALID_PROT_INFO = 0x0181,
384 NVME_WRITE_TO_RO = 0x0182,
385 NVME_WRITE_FAULT = 0x0280,
386 NVME_UNRECOVERED_READ = 0x0281,
387 NVME_E2E_GUARD_ERROR = 0x0282,
388 NVME_E2E_APP_ERROR = 0x0283,
389 NVME_E2E_REF_ERROR = 0x0284,
390 NVME_CMP_FAILURE = 0x0285,
391 NVME_ACCESS_DENIED = 0x0286,
392 NVME_MORE = 0x2000,
393 NVME_DNR = 0x4000,
394 NVME_NO_COMPLETE = 0xffff,
395};
396
397typedef struct NvmeFwSlotInfoLog {
398 uint8_t afi;
399 uint8_t reserved1[7];
400 uint8_t frs1[8];
401 uint8_t frs2[8];
402 uint8_t frs3[8];
403 uint8_t frs4[8];
404 uint8_t frs5[8];
405 uint8_t frs6[8];
406 uint8_t frs7[8];
407 uint8_t reserved2[448];
408} NvmeFwSlotInfoLog;
409
410typedef struct NvmeErrorLog {
411 uint64_t error_count;
412 uint16_t sqid;
413 uint16_t cid;
414 uint16_t status_field;
415 uint16_t param_error_location;
416 uint64_t lba;
417 uint32_t nsid;
418 uint8_t vs;
419 uint8_t resv[35];
420} NvmeErrorLog;
421
422typedef struct NvmeSmartLog {
423 uint8_t critical_warning;
424 uint8_t temperature[2];
425 uint8_t available_spare;
426 uint8_t available_spare_threshold;
427 uint8_t percentage_used;
428 uint8_t reserved1[26];
429 uint64_t data_units_read[2];
430 uint64_t data_units_written[2];
431 uint64_t host_read_commands[2];
432 uint64_t host_write_commands[2];
433 uint64_t controller_busy_time[2];
434 uint64_t power_cycles[2];
435 uint64_t power_on_hours[2];
436 uint64_t unsafe_shutdowns[2];
437 uint64_t media_errors[2];
438 uint64_t number_of_error_log_entries[2];
439 uint8_t reserved2[320];
440} NvmeSmartLog;
441
442enum NvmeSmartWarn {
443 NVME_SMART_SPARE = 1 << 0,
444 NVME_SMART_TEMPERATURE = 1 << 1,
445 NVME_SMART_RELIABILITY = 1 << 2,
446 NVME_SMART_MEDIA_READ_ONLY = 1 << 3,
447 NVME_SMART_FAILED_VOLATILE_MEDIA = 1 << 4,
448};
449
450enum LogIdentifier {
451 NVME_LOG_ERROR_INFO = 0x01,
452 NVME_LOG_SMART_INFO = 0x02,
453 NVME_LOG_FW_SLOT_INFO = 0x03,
454};
455
456typedef struct NvmePSD {
457 uint16_t mp;
458 uint16_t reserved;
459 uint32_t enlat;
460 uint32_t exlat;
461 uint8_t rrt;
462 uint8_t rrl;
463 uint8_t rwt;
464 uint8_t rwl;
465 uint8_t resv[16];
466} NvmePSD;
467
468typedef struct NvmeIdCtrl {
469 uint16_t vid;
470 uint16_t ssvid;
471 uint8_t sn[20];
472 uint8_t mn[40];
473 uint8_t fr[8];
474 uint8_t rab;
475 uint8_t ieee[3];
476 uint8_t cmic;
477 uint8_t mdts;
478 uint8_t rsvd255[178];
479 uint16_t oacs;
480 uint8_t acl;
481 uint8_t aerl;
482 uint8_t frmw;
483 uint8_t lpa;
484 uint8_t elpe;
485 uint8_t npss;
486 uint8_t rsvd511[248];
487 uint8_t sqes;
488 uint8_t cqes;
489 uint16_t rsvd515;
490 uint32_t nn;
491 uint16_t oncs;
492 uint16_t fuses;
493 uint8_t fna;
494 uint8_t vwc;
495 uint16_t awun;
496 uint16_t awupf;
497 uint8_t rsvd703[174];
498 uint8_t rsvd2047[1344];
499 NvmePSD psd[32];
500 uint8_t vs[1024];
501} NvmeIdCtrl;
502
503enum NvmeIdCtrlOacs {
504 NVME_OACS_SECURITY = 1 << 0,
505 NVME_OACS_FORMAT = 1 << 1,
506 NVME_OACS_FW = 1 << 2,
507};
508
509enum NvmeIdCtrlOncs {
510 NVME_ONCS_COMPARE = 1 << 0,
511 NVME_ONCS_WRITE_UNCORR = 1 << 1,
512 NVME_ONCS_DSM = 1 << 2,
513 NVME_ONCS_WRITE_ZEROS = 1 << 3,
514 NVME_ONCS_FEATURES = 1 << 4,
515 NVME_ONCS_RESRVATIONS = 1 << 5,
516};
517
518#define NVME_CTRL_SQES_MIN(sqes) ((sqes) & 0xf)
519#define NVME_CTRL_SQES_MAX(sqes) (((sqes) >> 4) & 0xf)
520#define NVME_CTRL_CQES_MIN(cqes) ((cqes) & 0xf)
521#define NVME_CTRL_CQES_MAX(cqes) (((cqes) >> 4) & 0xf)
522
523typedef struct NvmeFeatureVal {
524 uint32_t arbitration;
525 uint32_t power_mgmt;
526 uint32_t temp_thresh;
527 uint32_t err_rec;
528 uint32_t volatile_wc;
529 uint32_t num_queues;
530 uint32_t int_coalescing;
531 uint32_t *int_vector_config;
532 uint32_t write_atomicity;
533 uint32_t async_config;
534 uint32_t sw_prog_marker;
535} NvmeFeatureVal;
536
537#define NVME_ARB_AB(arb) (arb & 0x7)
538#define NVME_ARB_LPW(arb) ((arb >> 8) & 0xff)
539#define NVME_ARB_MPW(arb) ((arb >> 16) & 0xff)
540#define NVME_ARB_HPW(arb) ((arb >> 24) & 0xff)
541
542#define NVME_INTC_THR(intc) (intc & 0xff)
543#define NVME_INTC_TIME(intc) ((intc >> 8) & 0xff)
544
545enum NvmeFeatureIds {
546 NVME_ARBITRATION = 0x1,
547 NVME_POWER_MANAGEMENT = 0x2,
548 NVME_LBA_RANGE_TYPE = 0x3,
549 NVME_TEMPERATURE_THRESHOLD = 0x4,
550 NVME_ERROR_RECOVERY = 0x5,
551 NVME_VOLATILE_WRITE_CACHE = 0x6,
552 NVME_NUMBER_OF_QUEUES = 0x7,
553 NVME_INTERRUPT_COALESCING = 0x8,
554 NVME_INTERRUPT_VECTOR_CONF = 0x9,
555 NVME_WRITE_ATOMICITY = 0xa,
556 NVME_ASYNCHRONOUS_EVENT_CONF = 0xb,
557 NVME_SOFTWARE_PROGRESS_MARKER = 0x80
558};
559
560typedef struct NvmeRangeType {
561 uint8_t type;
562 uint8_t attributes;
563 uint8_t rsvd2[14];
564 uint64_t slba;
565 uint64_t nlb;
566 uint8_t guid[16];
567 uint8_t rsvd48[16];
568} NvmeRangeType;
569
570typedef struct NvmeLBAF {
571 uint16_t ms;
572 uint8_t ds;
573 uint8_t rp;
574} NvmeLBAF;
575
576typedef struct NvmeIdNs {
577 uint64_t nsze;
578 uint64_t ncap;
579 uint64_t nuse;
580 uint8_t nsfeat;
581 uint8_t nlbaf;
582 uint8_t flbas;
583 uint8_t mc;
584 uint8_t dpc;
585 uint8_t dps;
586 uint8_t res30[98];
587 NvmeLBAF lbaf[16];
588 uint8_t res192[192];
589 uint8_t vs[3712];
590} NvmeIdNs;
591
592#define NVME_ID_NS_NSFEAT_THIN(nsfeat) ((nsfeat & 0x1))
593#define NVME_ID_NS_FLBAS_EXTENDED(flbas) ((flbas >> 4) & 0x1)
594#define NVME_ID_NS_FLBAS_INDEX(flbas) ((flbas & 0xf))
595#define NVME_ID_NS_MC_SEPARATE(mc) ((mc >> 1) & 0x1)
596#define NVME_ID_NS_MC_EXTENDED(mc) ((mc & 0x1))
597#define NVME_ID_NS_DPC_LAST_EIGHT(dpc) ((dpc >> 4) & 0x1)
598#define NVME_ID_NS_DPC_FIRST_EIGHT(dpc) ((dpc >> 3) & 0x1)
599#define NVME_ID_NS_DPC_TYPE_3(dpc) ((dpc >> 2) & 0x1)
600#define NVME_ID_NS_DPC_TYPE_2(dpc) ((dpc >> 1) & 0x1)
601#define NVME_ID_NS_DPC_TYPE_1(dpc) ((dpc & 0x1))
602#define NVME_ID_NS_DPC_TYPE_MASK 0x7
603
604enum NvmeIdNsDps {
605 DPS_TYPE_NONE = 0,
606 DPS_TYPE_1 = 1,
607 DPS_TYPE_2 = 2,
608 DPS_TYPE_3 = 3,
609 DPS_TYPE_MASK = 0x7,
610 DPS_FIRST_EIGHT = 8,
611};
612
613static inline void _nvme_check_size(void)
614{
615 QEMU_BUILD_BUG_ON(sizeof(NvmeAerResult) != 4);
616 QEMU_BUILD_BUG_ON(sizeof(NvmeCqe) != 16);
617 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmRange) != 16);
618 QEMU_BUILD_BUG_ON(sizeof(NvmeCmd) != 64);
619 QEMU_BUILD_BUG_ON(sizeof(NvmeDeleteQ) != 64);
620 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateCq) != 64);
621 QEMU_BUILD_BUG_ON(sizeof(NvmeCreateSq) != 64);
622 QEMU_BUILD_BUG_ON(sizeof(NvmeIdentify) != 64);
623 QEMU_BUILD_BUG_ON(sizeof(NvmeRwCmd) != 64);
624 QEMU_BUILD_BUG_ON(sizeof(NvmeDsmCmd) != 64);
625 QEMU_BUILD_BUG_ON(sizeof(NvmeRangeType) != 64);
626 QEMU_BUILD_BUG_ON(sizeof(NvmeErrorLog) != 64);
627 QEMU_BUILD_BUG_ON(sizeof(NvmeFwSlotInfoLog) != 512);
628 QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) != 512);
629 QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) != 4096);
630 QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) != 4096);
631}
632
633typedef struct NvmeAsyncEvent {
634 QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry;
635 NvmeAerResult result;
636} NvmeAsyncEvent;
637
638typedef struct NvmeRequest {
639 struct NvmeSQueue *sq;
640 BlockAIOCB *aiocb;
641 uint16_t status;
642 bool has_sg;
643 NvmeCqe cqe;
644 BlockAcctCookie acct;
645 QEMUSGList qsg;
646 QTAILQ_ENTRY(NvmeRequest)entry;
647} NvmeRequest;
648
649typedef struct NvmeSQueue {
650 struct NvmeCtrl *ctrl;
651 uint16_t sqid;
652 uint16_t cqid;
653 uint32_t head;
654 uint32_t tail;
655 uint32_t size;
656 uint64_t dma_addr;
657 QEMUTimer *timer;
658 NvmeRequest *io_req;
659 QTAILQ_HEAD(sq_req_list, NvmeRequest) req_list;
660 QTAILQ_HEAD(out_req_list, NvmeRequest) out_req_list;
661 QTAILQ_ENTRY(NvmeSQueue) entry;
662} NvmeSQueue;
663
664typedef struct NvmeCQueue {
665 struct NvmeCtrl *ctrl;
666 uint8_t phase;
667 uint16_t cqid;
668 uint16_t irq_enabled;
669 uint32_t head;
670 uint32_t tail;
671 uint32_t vector;
672 uint32_t size;
673 uint64_t dma_addr;
674 QEMUTimer *timer;
675 QTAILQ_HEAD(sq_list, NvmeSQueue) sq_list;
676 QTAILQ_HEAD(cq_req_list, NvmeRequest) req_list;
677} NvmeCQueue;
678
679typedef struct NvmeNamespace {
680 NvmeIdNs id_ns;
681} NvmeNamespace;
682
683#define TYPE_NVME "nvme"
684#define NVME(obj) \
685 OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME)
686
687typedef struct NvmeCtrl {
688 PCIDevice parent_obj;
689 MemoryRegion iomem;
690 NvmeBar bar;
691 BlockConf conf;
692
693 uint32_t page_size;
694 uint16_t page_bits;
695 uint16_t max_prp_ents;
696 uint16_t cqe_size;
697 uint16_t sqe_size;
698 uint32_t reg_size;
699 uint32_t num_namespaces;
700 uint32_t num_queues;
701 uint32_t max_q_ents;
702 uint64_t ns_size;
703
704 char *serial;
705 NvmeNamespace *namespaces;
706 NvmeSQueue **sq;
707 NvmeCQueue **cq;
708 NvmeSQueue admin_sq;
709 NvmeCQueue admin_cq;
710 NvmeIdCtrl id_ctrl;
711} NvmeCtrl;
712
713#endif
714
