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19#include "qemu/osdep.h"
20#include "hw/char/cadence_uart.h"
21
22#ifdef CADENCE_UART_ERR_DEBUG
23#define DB_PRINT(...) do { \
24 fprintf(stderr, ": %s: ", __func__); \
25 fprintf(stderr, ## __VA_ARGS__); \
26 } while (0);
27#else
28 #define DB_PRINT(...)
29#endif
30
31#define UART_SR_INTR_RTRIG 0x00000001
32#define UART_SR_INTR_REMPTY 0x00000002
33#define UART_SR_INTR_RFUL 0x00000004
34#define UART_SR_INTR_TEMPTY 0x00000008
35#define UART_SR_INTR_TFUL 0x00000010
36
37#define UART_SR_TTRIG 0x00002000
38#define UART_INTR_TTRIG 0x00000400
39
40
41#define UART_SR_TO_CISR_MASK 0x0000001F
42
43#define UART_INTR_ROVR 0x00000020
44#define UART_INTR_FRAME 0x00000040
45#define UART_INTR_PARE 0x00000080
46#define UART_INTR_TIMEOUT 0x00000100
47#define UART_INTR_DMSI 0x00000200
48#define UART_INTR_TOVR 0x00001000
49
50#define UART_SR_RACTIVE 0x00000400
51#define UART_SR_TACTIVE 0x00000800
52#define UART_SR_FDELT 0x00001000
53
54#define UART_CR_RXRST 0x00000001
55#define UART_CR_TXRST 0x00000002
56#define UART_CR_RX_EN 0x00000004
57#define UART_CR_RX_DIS 0x00000008
58#define UART_CR_TX_EN 0x00000010
59#define UART_CR_TX_DIS 0x00000020
60#define UART_CR_RST_TO 0x00000040
61#define UART_CR_STARTBRK 0x00000080
62#define UART_CR_STOPBRK 0x00000100
63
64#define UART_MR_CLKS 0x00000001
65#define UART_MR_CHRL 0x00000006
66#define UART_MR_CHRL_SH 1
67#define UART_MR_PAR 0x00000038
68#define UART_MR_PAR_SH 3
69#define UART_MR_NBSTOP 0x000000C0
70#define UART_MR_NBSTOP_SH 6
71#define UART_MR_CHMODE 0x00000300
72#define UART_MR_CHMODE_SH 8
73#define UART_MR_UCLKEN 0x00000400
74#define UART_MR_IRMODE 0x00000800
75
76#define UART_DATA_BITS_6 (0x3 << UART_MR_CHRL_SH)
77#define UART_DATA_BITS_7 (0x2 << UART_MR_CHRL_SH)
78#define UART_PARITY_ODD (0x1 << UART_MR_PAR_SH)
79#define UART_PARITY_EVEN (0x0 << UART_MR_PAR_SH)
80#define UART_STOP_BITS_1 (0x3 << UART_MR_NBSTOP_SH)
81#define UART_STOP_BITS_2 (0x2 << UART_MR_NBSTOP_SH)
82#define NORMAL_MODE (0x0 << UART_MR_CHMODE_SH)
83#define ECHO_MODE (0x1 << UART_MR_CHMODE_SH)
84#define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH)
85#define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH)
86
87#define UART_INPUT_CLK 50000000
88
89#define R_CR (0x00/4)
90#define R_MR (0x04/4)
91#define R_IER (0x08/4)
92#define R_IDR (0x0C/4)
93#define R_IMR (0x10/4)
94#define R_CISR (0x14/4)
95#define R_BRGR (0x18/4)
96#define R_RTOR (0x1C/4)
97#define R_RTRIG (0x20/4)
98#define R_MCR (0x24/4)
99#define R_MSR (0x28/4)
100#define R_SR (0x2C/4)
101#define R_TX_RX (0x30/4)
102#define R_BDIV (0x34/4)
103#define R_FDEL (0x38/4)
104#define R_PMIN (0x3C/4)
105#define R_PWID (0x40/4)
106#define R_TTRIG (0x44/4)
107
108
109static void uart_update_status(CadenceUARTState *s)
110{
111 s->r[R_SR] = 0;
112
113 s->r[R_SR] |= s->rx_count == CADENCE_UART_RX_FIFO_SIZE ? UART_SR_INTR_RFUL
114 : 0;
115 s->r[R_SR] |= !s->rx_count ? UART_SR_INTR_REMPTY : 0;
116 s->r[R_SR] |= s->rx_count >= s->r[R_RTRIG] ? UART_SR_INTR_RTRIG : 0;
117
118 s->r[R_SR] |= s->tx_count == CADENCE_UART_TX_FIFO_SIZE ? UART_SR_INTR_TFUL
119 : 0;
120 s->r[R_SR] |= !s->tx_count ? UART_SR_INTR_TEMPTY : 0;
121 s->r[R_SR] |= s->tx_count >= s->r[R_TTRIG] ? UART_SR_TTRIG : 0;
122
123 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TO_CISR_MASK;
124 s->r[R_CISR] |= s->r[R_SR] & UART_SR_TTRIG ? UART_INTR_TTRIG : 0;
125 qemu_set_irq(s->irq, !!(s->r[R_IMR] & s->r[R_CISR]));
126}
127
128static void fifo_trigger_update(void *opaque)
129{
130 CadenceUARTState *s = opaque;
131
132 s->r[R_CISR] |= UART_INTR_TIMEOUT;
133
134 uart_update_status(s);
135}
136
137static void uart_rx_reset(CadenceUARTState *s)
138{
139 s->rx_wpos = 0;
140 s->rx_count = 0;
141 if (s->chr) {
142 qemu_chr_accept_input(s->chr);
143 }
144}
145
146static void uart_tx_reset(CadenceUARTState *s)
147{
148 s->tx_count = 0;
149}
150
151static void uart_send_breaks(CadenceUARTState *s)
152{
153 int break_enabled = 1;
154
155 if (s->chr) {
156 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
157 &break_enabled);
158 }
159}
160
161static void uart_parameters_setup(CadenceUARTState *s)
162{
163 QEMUSerialSetParams ssp;
164 unsigned int baud_rate, packet_size;
165
166 baud_rate = (s->r[R_MR] & UART_MR_CLKS) ?
167 UART_INPUT_CLK / 8 : UART_INPUT_CLK;
168
169 ssp.speed = baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1));
170 packet_size = 1;
171
172 switch (s->r[R_MR] & UART_MR_PAR) {
173 case UART_PARITY_EVEN:
174 ssp.parity = 'E';
175 packet_size++;
176 break;
177 case UART_PARITY_ODD:
178 ssp.parity = 'O';
179 packet_size++;
180 break;
181 default:
182 ssp.parity = 'N';
183 break;
184 }
185
186 switch (s->r[R_MR] & UART_MR_CHRL) {
187 case UART_DATA_BITS_6:
188 ssp.data_bits = 6;
189 break;
190 case UART_DATA_BITS_7:
191 ssp.data_bits = 7;
192 break;
193 default:
194 ssp.data_bits = 8;
195 break;
196 }
197
198 switch (s->r[R_MR] & UART_MR_NBSTOP) {
199 case UART_STOP_BITS_1:
200 ssp.stop_bits = 1;
201 break;
202 default:
203 ssp.stop_bits = 2;
204 break;
205 }
206
207 packet_size += ssp.data_bits + ssp.stop_bits;
208 s->char_tx_time = (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size;
209 if (s->chr) {
210 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
211 }
212}
213
214static int uart_can_receive(void *opaque)
215{
216 CadenceUARTState *s = opaque;
217 int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE);
218 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
219
220 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
221 ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count);
222 }
223 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
224 ret = MIN(ret, CADENCE_UART_TX_FIFO_SIZE - s->tx_count);
225 }
226 return ret;
227}
228
229static void uart_ctrl_update(CadenceUARTState *s)
230{
231 if (s->r[R_CR] & UART_CR_TXRST) {
232 uart_tx_reset(s);
233 }
234
235 if (s->r[R_CR] & UART_CR_RXRST) {
236 uart_rx_reset(s);
237 }
238
239 s->r[R_CR] &= ~(UART_CR_TXRST | UART_CR_RXRST);
240
241 if (s->r[R_CR] & UART_CR_STARTBRK && !(s->r[R_CR] & UART_CR_STOPBRK)) {
242 uart_send_breaks(s);
243 }
244}
245
246static void uart_write_rx_fifo(void *opaque, const uint8_t *buf, int size)
247{
248 CadenceUARTState *s = opaque;
249 uint64_t new_rx_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
250 int i;
251
252 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
253 return;
254 }
255
256 if (s->rx_count == CADENCE_UART_RX_FIFO_SIZE) {
257 s->r[R_CISR] |= UART_INTR_ROVR;
258 } else {
259 for (i = 0; i < size; i++) {
260 s->rx_fifo[s->rx_wpos] = buf[i];
261 s->rx_wpos = (s->rx_wpos + 1) % CADENCE_UART_RX_FIFO_SIZE;
262 s->rx_count++;
263 }
264 timer_mod(s->fifo_trigger_handle, new_rx_time +
265 (s->char_tx_time * 4));
266 }
267 uart_update_status(s);
268}
269
270static gboolean cadence_uart_xmit(GIOChannel *chan, GIOCondition cond,
271 void *opaque)
272{
273 CadenceUARTState *s = opaque;
274 int ret;
275
276
277 if (!s->chr) {
278 s->tx_count = 0;
279 return FALSE;
280 }
281
282 if (!s->tx_count) {
283 return FALSE;
284 }
285
286 ret = qemu_chr_fe_write(s->chr, s->tx_fifo, s->tx_count);
287 s->tx_count -= ret;
288 memmove(s->tx_fifo, s->tx_fifo + ret, s->tx_count);
289
290 if (s->tx_count) {
291 int r = qemu_chr_fe_add_watch(s->chr, G_IO_OUT|G_IO_HUP,
292 cadence_uart_xmit, s);
293 assert(r);
294 }
295
296 uart_update_status(s);
297 return FALSE;
298}
299
300static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf,
301 int size)
302{
303 if ((s->r[R_CR] & UART_CR_TX_DIS) || !(s->r[R_CR] & UART_CR_TX_EN)) {
304 return;
305 }
306
307 if (size > CADENCE_UART_TX_FIFO_SIZE - s->tx_count) {
308 size = CADENCE_UART_TX_FIFO_SIZE - s->tx_count;
309
310
311
312
313
314 qemu_log_mask(LOG_GUEST_ERROR, "cadence_uart: TxFIFO overflow");
315 s->r[R_CISR] |= UART_INTR_ROVR;
316 }
317
318 memcpy(s->tx_fifo + s->tx_count, buf, size);
319 s->tx_count += size;
320
321 cadence_uart_xmit(NULL, G_IO_OUT, s);
322}
323
324static void uart_receive(void *opaque, const uint8_t *buf, int size)
325{
326 CadenceUARTState *s = opaque;
327 uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE;
328
329 if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) {
330 uart_write_rx_fifo(opaque, buf, size);
331 }
332 if (ch_mode == REMOTE_LOOPBACK || ch_mode == ECHO_MODE) {
333 uart_write_tx_fifo(s, buf, size);
334 }
335}
336
337static void uart_event(void *opaque, int event)
338{
339 CadenceUARTState *s = opaque;
340 uint8_t buf = '\0';
341
342 if (event == CHR_EVENT_BREAK) {
343 uart_write_rx_fifo(opaque, &buf, 1);
344 }
345
346 uart_update_status(s);
347}
348
349static void uart_read_rx_fifo(CadenceUARTState *s, uint32_t *c)
350{
351 if ((s->r[R_CR] & UART_CR_RX_DIS) || !(s->r[R_CR] & UART_CR_RX_EN)) {
352 return;
353 }
354
355 if (s->rx_count) {
356 uint32_t rx_rpos = (CADENCE_UART_RX_FIFO_SIZE + s->rx_wpos -
357 s->rx_count) % CADENCE_UART_RX_FIFO_SIZE;
358 *c = s->rx_fifo[rx_rpos];
359 s->rx_count--;
360
361 if (s->chr) {
362 qemu_chr_accept_input(s->chr);
363 }
364 } else {
365 *c = 0;
366 }
367
368 uart_update_status(s);
369}
370
371static void uart_write(void *opaque, hwaddr offset,
372 uint64_t value, unsigned size)
373{
374 CadenceUARTState *s = opaque;
375
376 DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value);
377 offset >>= 2;
378 if (offset >= CADENCE_UART_R_MAX) {
379 return;
380 }
381 switch (offset) {
382 case R_IER:
383 s->r[R_IMR] |= value;
384 break;
385 case R_IDR:
386 s->r[R_IMR] &= ~value;
387 break;
388 case R_IMR:
389 break;
390 case R_CISR:
391 s->r[R_CISR] &= ~value;
392 break;
393 case R_TX_RX:
394 switch (s->r[R_MR] & UART_MR_CHMODE) {
395 case NORMAL_MODE:
396 uart_write_tx_fifo(s, (uint8_t *) &value, 1);
397 break;
398 case LOCAL_LOOPBACK:
399 uart_write_rx_fifo(opaque, (uint8_t *) &value, 1);
400 break;
401 }
402 break;
403 case R_BRGR:
404 if (value >= 0x01) {
405 s->r[offset] = value & 0xFFFF;
406 }
407 break;
408 case R_BDIV:
409 if (value >= 0x04) {
410 s->r[offset] = value & 0xFF;
411 }
412 break;
413 default:
414 s->r[offset] = value;
415 }
416
417 switch (offset) {
418 case R_CR:
419 uart_ctrl_update(s);
420 break;
421 case R_MR:
422 uart_parameters_setup(s);
423 break;
424 }
425 uart_update_status(s);
426}
427
428static uint64_t uart_read(void *opaque, hwaddr offset,
429 unsigned size)
430{
431 CadenceUARTState *s = opaque;
432 uint32_t c = 0;
433
434 offset >>= 2;
435 if (offset >= CADENCE_UART_R_MAX) {
436 c = 0;
437 } else if (offset == R_TX_RX) {
438 uart_read_rx_fifo(s, &c);
439 } else {
440 c = s->r[offset];
441 }
442
443 DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c);
444 return c;
445}
446
447static const MemoryRegionOps uart_ops = {
448 .read = uart_read,
449 .write = uart_write,
450 .endianness = DEVICE_NATIVE_ENDIAN,
451};
452
453static void cadence_uart_reset(DeviceState *dev)
454{
455 CadenceUARTState *s = CADENCE_UART(dev);
456
457 s->r[R_CR] = UART_CR_RX_EN | UART_CR_TX_EN | UART_CR_STOPBRK;
458 s->r[R_IMR] = 0;
459 s->r[R_CISR] = 0;
460 s->r[R_RTRIG] = 0x00000020;
461 s->r[R_BRGR] = 0x0000028B;
462 s->r[R_BDIV] = 0x0000000F;
463 s->r[R_TTRIG] = 0x00000020;
464
465 uart_rx_reset(s);
466 uart_tx_reset(s);
467
468 uart_update_status(s);
469}
470
471static void cadence_uart_realize(DeviceState *dev, Error **errp)
472{
473 CadenceUARTState *s = CADENCE_UART(dev);
474
475 s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
476 fifo_trigger_update, s);
477
478
479 s->chr = qemu_char_get_next_serial();
480
481 if (s->chr) {
482 qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
483 uart_event, s);
484 }
485}
486
487static void cadence_uart_init(Object *obj)
488{
489 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
490 CadenceUARTState *s = CADENCE_UART(obj);
491
492 memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);
493 sysbus_init_mmio(sbd, &s->iomem);
494 sysbus_init_irq(sbd, &s->irq);
495
496 s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10;
497}
498
499static int cadence_uart_post_load(void *opaque, int version_id)
500{
501 CadenceUARTState *s = opaque;
502
503 uart_parameters_setup(s);
504 uart_update_status(s);
505 return 0;
506}
507
508static const VMStateDescription vmstate_cadence_uart = {
509 .name = "cadence_uart",
510 .version_id = 2,
511 .minimum_version_id = 2,
512 .post_load = cadence_uart_post_load,
513 .fields = (VMStateField[]) {
514 VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX),
515 VMSTATE_UINT8_ARRAY(rx_fifo, CadenceUARTState,
516 CADENCE_UART_RX_FIFO_SIZE),
517 VMSTATE_UINT8_ARRAY(tx_fifo, CadenceUARTState,
518 CADENCE_UART_TX_FIFO_SIZE),
519 VMSTATE_UINT32(rx_count, CadenceUARTState),
520 VMSTATE_UINT32(tx_count, CadenceUARTState),
521 VMSTATE_UINT32(rx_wpos, CadenceUARTState),
522 VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState),
523 VMSTATE_END_OF_LIST()
524 }
525};
526
527static void cadence_uart_class_init(ObjectClass *klass, void *data)
528{
529 DeviceClass *dc = DEVICE_CLASS(klass);
530
531 dc->realize = cadence_uart_realize;
532 dc->vmsd = &vmstate_cadence_uart;
533 dc->reset = cadence_uart_reset;
534
535 dc->cannot_instantiate_with_device_add_yet = true;
536}
537
538static const TypeInfo cadence_uart_info = {
539 .name = TYPE_CADENCE_UART,
540 .parent = TYPE_SYS_BUS_DEVICE,
541 .instance_size = sizeof(CadenceUARTState),
542 .instance_init = cadence_uart_init,
543 .class_init = cadence_uart_class_init,
544};
545
546static void cadence_uart_register_types(void)
547{
548 type_register_static(&cadence_uart_info);
549}
550
551type_init(cadence_uart_register_types)
552
