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22#include "qemu/osdep.h"
23#include "hw/sysbus.h"
24#include "qemu/error-report.h"
25#include "sysemu/sysemu.h"
26#include "sysemu/char.h"
27
28#include "hw/arm/exynos4210.h"
29
30#undef DEBUG_UART
31#undef DEBUG_UART_EXTEND
32#undef DEBUG_IRQ
33#undef DEBUG_Rx_DATA
34#undef DEBUG_Tx_DATA
35
36#define DEBUG_UART 0
37#define DEBUG_UART_EXTEND 0
38#define DEBUG_IRQ 0
39#define DEBUG_Rx_DATA 0
40#define DEBUG_Tx_DATA 0
41
42#if DEBUG_UART
43#define PRINT_DEBUG(fmt, args...) \
44 do { \
45 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
46 } while (0)
47
48#if DEBUG_UART_EXTEND
49#define PRINT_DEBUG_EXTEND(fmt, args...) \
50 do { \
51 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
52 } while (0)
53#else
54#define PRINT_DEBUG_EXTEND(fmt, args...) \
55 do {} while (0)
56#endif
57
58#else
59#define PRINT_DEBUG(fmt, args...) \
60 do {} while (0)
61#define PRINT_DEBUG_EXTEND(fmt, args...) \
62 do {} while (0)
63#endif
64
65#define PRINT_ERROR(fmt, args...) \
66 do { \
67 fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
68 } while (0)
69
70
71
72
73
74
75#define ULCON 0x0000
76#define UCON 0x0004
77#define UFCON 0x0008
78#define UMCON 0x000C
79#define UTRSTAT 0x0010
80#define UERSTAT 0x0014
81#define UFSTAT 0x0018
82#define UMSTAT 0x001C
83#define UTXH 0x0020
84#define URXH 0x0024
85#define UBRDIV 0x0028
86#define UFRACVAL 0x002C
87#define UINTP 0x0030
88#define UINTSP 0x0034
89#define UINTM 0x0038
90
91
92
93
94
95
96
97#define I_(reg) (reg / sizeof(uint32_t))
98
99typedef struct Exynos4210UartReg {
100 const char *name;
101 hwaddr offset;
102 uint32_t reset_value;
103} Exynos4210UartReg;
104
105static Exynos4210UartReg exynos4210_uart_regs[] = {
106 {"ULCON", ULCON, 0x00000000},
107 {"UCON", UCON, 0x00003000},
108 {"UFCON", UFCON, 0x00000000},
109 {"UMCON", UMCON, 0x00000000},
110 {"UTRSTAT", UTRSTAT, 0x00000006},
111 {"UERSTAT", UERSTAT, 0x00000000},
112 {"UFSTAT", UFSTAT, 0x00000000},
113 {"UMSTAT", UMSTAT, 0x00000000},
114 {"UTXH", UTXH, 0x5c5c5c5c},
115 {"URXH", URXH, 0x00000000},
116 {"UBRDIV", UBRDIV, 0x00000000},
117 {"UFRACVAL", UFRACVAL, 0x00000000},
118 {"UINTP", UINTP, 0x00000000},
119 {"UINTSP", UINTSP, 0x00000000},
120 {"UINTM", UINTM, 0x00000000},
121};
122
123#define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
124
125
126#define UFCON_FIFO_ENABLE 0x1
127#define UFCON_Rx_FIFO_RESET 0x2
128#define UFCON_Tx_FIFO_RESET 0x4
129#define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
130#define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
131#define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
132#define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
133
134
135#define UFSTAT_Rx_FIFO_COUNT 0xff
136#define UFSTAT_Rx_FIFO_FULL 0x100
137#define UFSTAT_Rx_FIFO_ERROR 0x200
138#define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
139#define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
140#define UFSTAT_Tx_FIFO_FULL_SHIFT 24
141#define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
142
143
144#define UINTSP_RXD 0x1
145#define UINTSP_ERROR 0x2
146#define UINTSP_TXD 0x4
147#define UINTSP_MODEM 0x8
148
149
150#define ULCON_IR_MODE_SHIFT 6
151#define ULCON_PARITY_SHIFT 3
152#define ULCON_STOP_BIT_SHIFT 1
153
154
155#define UTRSTAT_TRANSMITTER_EMPTY 0x4
156#define UTRSTAT_Tx_BUFFER_EMPTY 0x2
157#define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
158
159
160#define UERSTAT_OVERRUN 0x1
161#define UERSTAT_PARITY 0x2
162#define UERSTAT_FRAME 0x4
163#define UERSTAT_BREAK 0x8
164
165typedef struct {
166 uint8_t *data;
167 uint32_t sp, rp;
168 uint32_t size;
169} Exynos4210UartFIFO;
170
171#define TYPE_EXYNOS4210_UART "exynos4210.uart"
172#define EXYNOS4210_UART(obj) \
173 OBJECT_CHECK(Exynos4210UartState, (obj), TYPE_EXYNOS4210_UART)
174
175typedef struct Exynos4210UartState {
176 SysBusDevice parent_obj;
177
178 MemoryRegion iomem;
179
180 uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
181 Exynos4210UartFIFO rx;
182 Exynos4210UartFIFO tx;
183
184 CharDriverState *chr;
185 qemu_irq irq;
186
187 uint32_t channel;
188
189} Exynos4210UartState;
190
191
192#if DEBUG_UART
193
194static const char *exynos4210_uart_regname(hwaddr offset)
195{
196
197 int i;
198
199 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
200 if (offset == exynos4210_uart_regs[i].offset) {
201 return exynos4210_uart_regs[i].name;
202 }
203 }
204
205 return NULL;
206}
207#endif
208
209
210static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
211{
212 q->data[q->sp] = ch;
213 q->sp = (q->sp + 1) % q->size;
214}
215
216static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
217{
218 uint8_t ret = q->data[q->rp];
219 q->rp = (q->rp + 1) % q->size;
220 return ret;
221}
222
223static int fifo_elements_number(Exynos4210UartFIFO *q)
224{
225 if (q->sp < q->rp) {
226 return q->size - q->rp + q->sp;
227 }
228
229 return q->sp - q->rp;
230}
231
232static int fifo_empty_elements_number(Exynos4210UartFIFO *q)
233{
234 return q->size - fifo_elements_number(q);
235}
236
237static void fifo_reset(Exynos4210UartFIFO *q)
238{
239 g_free(q->data);
240 q->data = NULL;
241
242 q->data = (uint8_t *)g_malloc0(q->size);
243
244 q->sp = 0;
245 q->rp = 0;
246}
247
248static uint32_t exynos4210_uart_Tx_FIFO_trigger_level(Exynos4210UartState *s)
249{
250 uint32_t level = 0;
251 uint32_t reg;
252
253 reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
254 UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
255
256 switch (s->channel) {
257 case 0:
258 level = reg * 32;
259 break;
260 case 1:
261 case 4:
262 level = reg * 8;
263 break;
264 case 2:
265 case 3:
266 level = reg * 2;
267 break;
268 default:
269 level = 0;
270 PRINT_ERROR("Wrong UART channel number: %d\n", s->channel);
271 }
272
273 return level;
274}
275
276static void exynos4210_uart_update_irq(Exynos4210UartState *s)
277{
278
279
280
281
282 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
283
284 uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
285 UFSTAT_Tx_FIFO_COUNT_SHIFT;
286
287 if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
288 s->reg[I_(UINTSP)] |= UINTSP_TXD;
289 }
290 }
291
292 s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
293
294 if (s->reg[I_(UINTP)]) {
295 qemu_irq_raise(s->irq);
296
297#if DEBUG_IRQ
298 fprintf(stderr, "UART%d: IRQ has been raised: %08x\n",
299 s->channel, s->reg[I_(UINTP)]);
300#endif
301
302 } else {
303 qemu_irq_lower(s->irq);
304 }
305}
306
307static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
308{
309 int speed, parity, data_bits, stop_bits, frame_size;
310 QEMUSerialSetParams ssp;
311 uint64_t uclk_rate;
312
313 if (s->reg[I_(UBRDIV)] == 0) {
314 return;
315 }
316
317 frame_size = 1;
318 if (s->reg[I_(ULCON)] & 0x20) {
319 frame_size++;
320 if (s->reg[I_(ULCON)] & 0x28) {
321 parity = 'E';
322 } else {
323 parity = 'O';
324 }
325 } else {
326 parity = 'N';
327 }
328
329 if (s->reg[I_(ULCON)] & 0x4) {
330 stop_bits = 2;
331 } else {
332 stop_bits = 1;
333 }
334
335 data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
336
337 frame_size += data_bits + stop_bits;
338
339 uclk_rate = 24000000;
340
341 speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
342 (s->reg[I_(UFRACVAL)] & 0x7) + 16);
343
344 ssp.speed = speed;
345 ssp.parity = parity;
346 ssp.data_bits = data_bits;
347 ssp.stop_bits = stop_bits;
348
349 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
350
351 PRINT_DEBUG("UART%d: speed: %d, parity: %c, data: %d, stop: %d\n",
352 s->channel, speed, parity, data_bits, stop_bits);
353}
354
355static void exynos4210_uart_write(void *opaque, hwaddr offset,
356 uint64_t val, unsigned size)
357{
358 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
359 uint8_t ch;
360
361 PRINT_DEBUG_EXTEND("UART%d: <0x%04x> %s <- 0x%08llx\n", s->channel,
362 offset, exynos4210_uart_regname(offset), (long long unsigned int)val);
363
364 switch (offset) {
365 case ULCON:
366 case UBRDIV:
367 case UFRACVAL:
368 s->reg[I_(offset)] = val;
369 exynos4210_uart_update_parameters(s);
370 break;
371 case UFCON:
372 s->reg[I_(UFCON)] = val;
373 if (val & UFCON_Rx_FIFO_RESET) {
374 fifo_reset(&s->rx);
375 s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
376 PRINT_DEBUG("UART%d: Rx FIFO Reset\n", s->channel);
377 }
378 if (val & UFCON_Tx_FIFO_RESET) {
379 fifo_reset(&s->tx);
380 s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
381 PRINT_DEBUG("UART%d: Tx FIFO Reset\n", s->channel);
382 }
383 break;
384
385 case UTXH:
386 if (s->chr) {
387 s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
388 UTRSTAT_Tx_BUFFER_EMPTY);
389 ch = (uint8_t)val;
390 qemu_chr_fe_write(s->chr, &ch, 1);
391#if DEBUG_Tx_DATA
392 fprintf(stderr, "%c", ch);
393#endif
394 s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
395 UTRSTAT_Tx_BUFFER_EMPTY;
396 s->reg[I_(UINTSP)] |= UINTSP_TXD;
397 exynos4210_uart_update_irq(s);
398 }
399 break;
400
401 case UINTP:
402 s->reg[I_(UINTP)] &= ~val;
403 s->reg[I_(UINTSP)] &= ~val;
404 PRINT_DEBUG("UART%d: UINTP [%04x] have been cleared: %08x\n",
405 s->channel, offset, s->reg[I_(UINTP)]);
406 exynos4210_uart_update_irq(s);
407 break;
408 case UTRSTAT:
409 case UERSTAT:
410 case UFSTAT:
411 case UMSTAT:
412 case URXH:
413 PRINT_DEBUG("UART%d: Trying to write into RO register: %s [%04x]\n",
414 s->channel, exynos4210_uart_regname(offset), offset);
415 break;
416 case UINTSP:
417 s->reg[I_(UINTSP)] &= ~val;
418 break;
419 case UINTM:
420 s->reg[I_(UINTM)] = val;
421 exynos4210_uart_update_irq(s);
422 break;
423 case UCON:
424 case UMCON:
425 default:
426 s->reg[I_(offset)] = val;
427 break;
428 }
429}
430static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
431 unsigned size)
432{
433 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
434 uint32_t res;
435
436 switch (offset) {
437 case UERSTAT:
438 res = s->reg[I_(UERSTAT)];
439 s->reg[I_(UERSTAT)] = 0;
440 return res;
441 case UFSTAT:
442 s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
443 if (fifo_empty_elements_number(&s->rx) == 0) {
444 s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
445 s->reg[I_(UFSTAT)] &= ~0xff;
446 }
447 return s->reg[I_(UFSTAT)];
448 case URXH:
449 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
450 if (fifo_elements_number(&s->rx)) {
451 res = fifo_retrieve(&s->rx);
452#if DEBUG_Rx_DATA
453 fprintf(stderr, "%c", res);
454#endif
455 if (!fifo_elements_number(&s->rx)) {
456 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
457 } else {
458 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
459 }
460 } else {
461 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
462 exynos4210_uart_update_irq(s);
463 res = 0;
464 }
465 } else {
466 s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
467 res = s->reg[I_(URXH)];
468 }
469 return res;
470 case UTXH:
471 PRINT_DEBUG("UART%d: Trying to read from WO register: %s [%04x]\n",
472 s->channel, exynos4210_uart_regname(offset), offset);
473 break;
474 default:
475 return s->reg[I_(offset)];
476 }
477
478 return 0;
479}
480
481static const MemoryRegionOps exynos4210_uart_ops = {
482 .read = exynos4210_uart_read,
483 .write = exynos4210_uart_write,
484 .endianness = DEVICE_NATIVE_ENDIAN,
485 .valid = {
486 .max_access_size = 4,
487 .unaligned = false
488 },
489};
490
491static int exynos4210_uart_can_receive(void *opaque)
492{
493 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
494
495 return fifo_empty_elements_number(&s->rx);
496}
497
498
499static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
500{
501 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
502 int i;
503
504 if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
505 if (fifo_empty_elements_number(&s->rx) < size) {
506 for (i = 0; i < fifo_empty_elements_number(&s->rx); i++) {
507 fifo_store(&s->rx, buf[i]);
508 }
509 s->reg[I_(UINTSP)] |= UINTSP_ERROR;
510 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
511 } else {
512 for (i = 0; i < size; i++) {
513 fifo_store(&s->rx, buf[i]);
514 }
515 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
516 }
517
518 s->reg[I_(UINTSP)] |= UINTSP_RXD;
519 } else {
520 s->reg[I_(URXH)] = buf[0];
521 s->reg[I_(UINTSP)] |= UINTSP_RXD;
522 s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
523 }
524
525 exynos4210_uart_update_irq(s);
526}
527
528
529static void exynos4210_uart_event(void *opaque, int event)
530{
531 Exynos4210UartState *s = (Exynos4210UartState *)opaque;
532
533 if (event == CHR_EVENT_BREAK) {
534
535
536 fifo_store(&s->rx, '\0');
537 s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
538 exynos4210_uart_update_irq(s);
539 }
540}
541
542
543static void exynos4210_uart_reset(DeviceState *dev)
544{
545 Exynos4210UartState *s = EXYNOS4210_UART(dev);
546 int i;
547
548 for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
549 s->reg[I_(exynos4210_uart_regs[i].offset)] =
550 exynos4210_uart_regs[i].reset_value;
551 }
552
553 fifo_reset(&s->rx);
554 fifo_reset(&s->tx);
555
556 PRINT_DEBUG("UART%d: Rx FIFO size: %d\n", s->channel, s->rx.size);
557}
558
559static const VMStateDescription vmstate_exynos4210_uart_fifo = {
560 .name = "exynos4210.uart.fifo",
561 .version_id = 1,
562 .minimum_version_id = 1,
563 .fields = (VMStateField[]) {
564 VMSTATE_UINT32(sp, Exynos4210UartFIFO),
565 VMSTATE_UINT32(rp, Exynos4210UartFIFO),
566 VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, 0, size),
567 VMSTATE_END_OF_LIST()
568 }
569};
570
571static const VMStateDescription vmstate_exynos4210_uart = {
572 .name = "exynos4210.uart",
573 .version_id = 1,
574 .minimum_version_id = 1,
575 .fields = (VMStateField[]) {
576 VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
577 vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
578 VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
579 EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
580 VMSTATE_END_OF_LIST()
581 }
582};
583
584DeviceState *exynos4210_uart_create(hwaddr addr,
585 int fifo_size,
586 int channel,
587 CharDriverState *chr,
588 qemu_irq irq)
589{
590 DeviceState *dev;
591 SysBusDevice *bus;
592
593 const char chr_name[] = "serial";
594 char label[ARRAY_SIZE(chr_name) + 1];
595
596 dev = qdev_create(NULL, TYPE_EXYNOS4210_UART);
597
598 if (!chr) {
599 if (channel >= MAX_SERIAL_PORTS) {
600 error_report("Only %d serial ports are supported by QEMU",
601 MAX_SERIAL_PORTS);
602 exit(1);
603 }
604 chr = serial_hds[channel];
605 if (!chr) {
606 snprintf(label, ARRAY_SIZE(label), "%s%d", chr_name, channel);
607 chr = qemu_chr_new(label, "null", NULL);
608 if (!(chr)) {
609 error_report("Can't assign serial port to UART%d", channel);
610 exit(1);
611 }
612 }
613 }
614
615 qdev_prop_set_chr(dev, "chardev", chr);
616 qdev_prop_set_uint32(dev, "channel", channel);
617 qdev_prop_set_uint32(dev, "rx-size", fifo_size);
618 qdev_prop_set_uint32(dev, "tx-size", fifo_size);
619
620 bus = SYS_BUS_DEVICE(dev);
621 qdev_init_nofail(dev);
622 if (addr != (hwaddr)-1) {
623 sysbus_mmio_map(bus, 0, addr);
624 }
625 sysbus_connect_irq(bus, 0, irq);
626
627 return dev;
628}
629
630static int exynos4210_uart_init(SysBusDevice *dev)
631{
632 Exynos4210UartState *s = EXYNOS4210_UART(dev);
633
634
635 memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
636 "exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
637 sysbus_init_mmio(dev, &s->iomem);
638
639 sysbus_init_irq(dev, &s->irq);
640
641 qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
642 exynos4210_uart_receive, exynos4210_uart_event, s);
643
644 return 0;
645}
646
647static Property exynos4210_uart_properties[] = {
648 DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
649 DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
650 DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
651 DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
652 DEFINE_PROP_END_OF_LIST(),
653};
654
655static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
656{
657 DeviceClass *dc = DEVICE_CLASS(klass);
658 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
659
660 k->init = exynos4210_uart_init;
661 dc->reset = exynos4210_uart_reset;
662 dc->props = exynos4210_uart_properties;
663 dc->vmsd = &vmstate_exynos4210_uart;
664}
665
666static const TypeInfo exynos4210_uart_info = {
667 .name = TYPE_EXYNOS4210_UART,
668 .parent = TYPE_SYS_BUS_DEVICE,
669 .instance_size = sizeof(Exynos4210UartState),
670 .class_init = exynos4210_uart_class_init,
671};
672
673static void exynos4210_uart_register(void)
674{
675 type_register_static(&exynos4210_uart_info);
676}
677
678type_init(exynos4210_uart_register)
679
