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25#include "qemu/osdep.h"
26#include "qapi/error.h"
27#include "hw/hw.h"
28#include "sysemu/char.h"
29#include "hw/isa/isa.h"
30#include "hw/i386/pc.h"
31#include "sysemu/sysemu.h"
32
33
34
35#ifdef DEBUG_PARALLEL
36#define pdebug(fmt, ...) printf("pp: " fmt, ## __VA_ARGS__)
37#else
38#define pdebug(fmt, ...) ((void)0)
39#endif
40
41#define PARA_REG_DATA 0
42#define PARA_REG_STS 1
43#define PARA_REG_CTR 2
44#define PARA_REG_EPP_ADDR 3
45#define PARA_REG_EPP_DATA 4
46
47
48
49
50#define PARA_STS_BUSY 0x80
51#define PARA_STS_ACK 0x40
52#define PARA_STS_PAPER 0x20
53#define PARA_STS_ONLINE 0x10
54#define PARA_STS_ERROR 0x08
55#define PARA_STS_TMOUT 0x01
56
57
58
59
60#define PARA_CTR_DIR 0x20
61#define PARA_CTR_INTEN 0x10
62#define PARA_CTR_SELECT 0x08
63#define PARA_CTR_INIT 0x04
64#define PARA_CTR_AUTOLF 0x02
65#define PARA_CTR_STROBE 0x01
66
67#define PARA_CTR_SIGNAL (PARA_CTR_SELECT|PARA_CTR_INIT|PARA_CTR_AUTOLF|PARA_CTR_STROBE)
68
69typedef struct ParallelState {
70 MemoryRegion iomem;
71 uint8_t dataw;
72 uint8_t datar;
73 uint8_t status;
74 uint8_t control;
75 qemu_irq irq;
76 int irq_pending;
77 CharDriverState *chr;
78 int hw_driver;
79 int epp_timeout;
80 uint32_t last_read_offset;
81
82 int it_shift;
83} ParallelState;
84
85#define TYPE_ISA_PARALLEL "isa-parallel"
86#define ISA_PARALLEL(obj) \
87 OBJECT_CHECK(ISAParallelState, (obj), TYPE_ISA_PARALLEL)
88
89typedef struct ISAParallelState {
90 ISADevice parent_obj;
91
92 uint32_t index;
93 uint32_t iobase;
94 uint32_t isairq;
95 ParallelState state;
96} ISAParallelState;
97
98static void parallel_update_irq(ParallelState *s)
99{
100 if (s->irq_pending)
101 qemu_irq_raise(s->irq);
102 else
103 qemu_irq_lower(s->irq);
104}
105
106static void
107parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
108{
109 ParallelState *s = opaque;
110
111 pdebug("write addr=0x%02x val=0x%02x\n", addr, val);
112
113 addr &= 7;
114 switch(addr) {
115 case PARA_REG_DATA:
116 s->dataw = val;
117 parallel_update_irq(s);
118 break;
119 case PARA_REG_CTR:
120 val |= 0xc0;
121 if ((val & PARA_CTR_INIT) == 0 ) {
122 s->status = PARA_STS_BUSY;
123 s->status |= PARA_STS_ACK;
124 s->status |= PARA_STS_ONLINE;
125 s->status |= PARA_STS_ERROR;
126 }
127 else if (val & PARA_CTR_SELECT) {
128 if (val & PARA_CTR_STROBE) {
129 s->status &= ~PARA_STS_BUSY;
130 if ((s->control & PARA_CTR_STROBE) == 0)
131 qemu_chr_fe_write(s->chr, &s->dataw, 1);
132 } else {
133 if (s->control & PARA_CTR_INTEN) {
134 s->irq_pending = 1;
135 }
136 }
137 }
138 parallel_update_irq(s);
139 s->control = val;
140 break;
141 }
142}
143
144static void parallel_ioport_write_hw(void *opaque, uint32_t addr, uint32_t val)
145{
146 ParallelState *s = opaque;
147 uint8_t parm = val;
148 int dir;
149
150
151
152
153 s->last_read_offset = ~0U;
154
155 addr &= 7;
156 switch(addr) {
157 case PARA_REG_DATA:
158 if (s->dataw == val)
159 return;
160 pdebug("wd%02x\n", val);
161 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_DATA, &parm);
162 s->dataw = val;
163 break;
164 case PARA_REG_STS:
165 pdebug("ws%02x\n", val);
166 if (val & PARA_STS_TMOUT)
167 s->epp_timeout = 0;
168 break;
169 case PARA_REG_CTR:
170 val |= 0xc0;
171 if (s->control == val)
172 return;
173 pdebug("wc%02x\n", val);
174
175 if ((val & PARA_CTR_DIR) != (s->control & PARA_CTR_DIR)) {
176 if (val & PARA_CTR_DIR) {
177 dir = 1;
178 } else {
179 dir = 0;
180 }
181 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_DATA_DIR, &dir);
182 parm &= ~PARA_CTR_DIR;
183 }
184
185 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_WRITE_CONTROL, &parm);
186 s->control = val;
187 break;
188 case PARA_REG_EPP_ADDR:
189 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
190
191 pdebug("wa%02x s\n", val);
192 else {
193 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
194 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE_ADDR, &ioarg)) {
195 s->epp_timeout = 1;
196 pdebug("wa%02x t\n", val);
197 }
198 else
199 pdebug("wa%02x\n", val);
200 }
201 break;
202 case PARA_REG_EPP_DATA:
203 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT)
204
205 pdebug("we%02x s\n", val);
206 else {
207 struct ParallelIOArg ioarg = { .buffer = &parm, .count = 1 };
208 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg)) {
209 s->epp_timeout = 1;
210 pdebug("we%02x t\n", val);
211 }
212 else
213 pdebug("we%02x\n", val);
214 }
215 break;
216 }
217}
218
219static void
220parallel_ioport_eppdata_write_hw2(void *opaque, uint32_t addr, uint32_t val)
221{
222 ParallelState *s = opaque;
223 uint16_t eppdata = cpu_to_le16(val);
224 int err;
225 struct ParallelIOArg ioarg = {
226 .buffer = &eppdata, .count = sizeof(eppdata)
227 };
228 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
229
230 pdebug("we%04x s\n", val);
231 return;
232 }
233 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
234 if (err) {
235 s->epp_timeout = 1;
236 pdebug("we%04x t\n", val);
237 }
238 else
239 pdebug("we%04x\n", val);
240}
241
242static void
243parallel_ioport_eppdata_write_hw4(void *opaque, uint32_t addr, uint32_t val)
244{
245 ParallelState *s = opaque;
246 uint32_t eppdata = cpu_to_le32(val);
247 int err;
248 struct ParallelIOArg ioarg = {
249 .buffer = &eppdata, .count = sizeof(eppdata)
250 };
251 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != PARA_CTR_INIT) {
252
253 pdebug("we%08x s\n", val);
254 return;
255 }
256 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_WRITE, &ioarg);
257 if (err) {
258 s->epp_timeout = 1;
259 pdebug("we%08x t\n", val);
260 }
261 else
262 pdebug("we%08x\n", val);
263}
264
265static uint32_t parallel_ioport_read_sw(void *opaque, uint32_t addr)
266{
267 ParallelState *s = opaque;
268 uint32_t ret = 0xff;
269
270 addr &= 7;
271 switch(addr) {
272 case PARA_REG_DATA:
273 if (s->control & PARA_CTR_DIR)
274 ret = s->datar;
275 else
276 ret = s->dataw;
277 break;
278 case PARA_REG_STS:
279 ret = s->status;
280 s->irq_pending = 0;
281 if ((s->status & PARA_STS_BUSY) == 0 && (s->control & PARA_CTR_STROBE) == 0) {
282
283 if (s->status & PARA_STS_ACK)
284 s->status &= ~PARA_STS_ACK;
285 else {
286
287 s->status |= PARA_STS_ACK;
288 s->status |= PARA_STS_BUSY;
289 }
290 }
291 parallel_update_irq(s);
292 break;
293 case PARA_REG_CTR:
294 ret = s->control;
295 break;
296 }
297 pdebug("read addr=0x%02x val=0x%02x\n", addr, ret);
298 return ret;
299}
300
301static uint32_t parallel_ioport_read_hw(void *opaque, uint32_t addr)
302{
303 ParallelState *s = opaque;
304 uint8_t ret = 0xff;
305 addr &= 7;
306 switch(addr) {
307 case PARA_REG_DATA:
308 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_DATA, &ret);
309 if (s->last_read_offset != addr || s->datar != ret)
310 pdebug("rd%02x\n", ret);
311 s->datar = ret;
312 break;
313 case PARA_REG_STS:
314 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &ret);
315 ret &= ~PARA_STS_TMOUT;
316 if (s->epp_timeout)
317 ret |= PARA_STS_TMOUT;
318 if (s->last_read_offset != addr || s->status != ret)
319 pdebug("rs%02x\n", ret);
320 s->status = ret;
321 break;
322 case PARA_REG_CTR:
323
324
325 if (s->control == 0) {
326 qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_CONTROL, &ret);
327 if (s->last_read_offset != addr)
328 pdebug("rc%02x\n", ret);
329 s->control = ret;
330 }
331 else {
332 ret = s->control;
333 if (s->last_read_offset != addr)
334 pdebug("rc%02x\n", ret);
335 }
336 break;
337 case PARA_REG_EPP_ADDR:
338 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
339
340 pdebug("ra%02x s\n", ret);
341 else {
342 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
343 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ_ADDR, &ioarg)) {
344 s->epp_timeout = 1;
345 pdebug("ra%02x t\n", ret);
346 }
347 else
348 pdebug("ra%02x\n", ret);
349 }
350 break;
351 case PARA_REG_EPP_DATA:
352 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT))
353
354 pdebug("re%02x s\n", ret);
355 else {
356 struct ParallelIOArg ioarg = { .buffer = &ret, .count = 1 };
357 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg)) {
358 s->epp_timeout = 1;
359 pdebug("re%02x t\n", ret);
360 }
361 else
362 pdebug("re%02x\n", ret);
363 }
364 break;
365 }
366 s->last_read_offset = addr;
367 return ret;
368}
369
370static uint32_t
371parallel_ioport_eppdata_read_hw2(void *opaque, uint32_t addr)
372{
373 ParallelState *s = opaque;
374 uint32_t ret;
375 uint16_t eppdata = ~0;
376 int err;
377 struct ParallelIOArg ioarg = {
378 .buffer = &eppdata, .count = sizeof(eppdata)
379 };
380 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
381
382 pdebug("re%04x s\n", eppdata);
383 return eppdata;
384 }
385 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
386 ret = le16_to_cpu(eppdata);
387
388 if (err) {
389 s->epp_timeout = 1;
390 pdebug("re%04x t\n", ret);
391 }
392 else
393 pdebug("re%04x\n", ret);
394 return ret;
395}
396
397static uint32_t
398parallel_ioport_eppdata_read_hw4(void *opaque, uint32_t addr)
399{
400 ParallelState *s = opaque;
401 uint32_t ret;
402 uint32_t eppdata = ~0U;
403 int err;
404 struct ParallelIOArg ioarg = {
405 .buffer = &eppdata, .count = sizeof(eppdata)
406 };
407 if ((s->control & (PARA_CTR_DIR|PARA_CTR_SIGNAL)) != (PARA_CTR_DIR|PARA_CTR_INIT)) {
408
409 pdebug("re%08x s\n", eppdata);
410 return eppdata;
411 }
412 err = qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_EPP_READ, &ioarg);
413 ret = le32_to_cpu(eppdata);
414
415 if (err) {
416 s->epp_timeout = 1;
417 pdebug("re%08x t\n", ret);
418 }
419 else
420 pdebug("re%08x\n", ret);
421 return ret;
422}
423
424static void parallel_ioport_ecp_write(void *opaque, uint32_t addr, uint32_t val)
425{
426 pdebug("wecp%d=%02x\n", addr & 7, val);
427}
428
429static uint32_t parallel_ioport_ecp_read(void *opaque, uint32_t addr)
430{
431 uint8_t ret = 0xff;
432
433 pdebug("recp%d:%02x\n", addr & 7, ret);
434 return ret;
435}
436
437static void parallel_reset(void *opaque)
438{
439 ParallelState *s = opaque;
440
441 s->datar = ~0;
442 s->dataw = ~0;
443 s->status = PARA_STS_BUSY;
444 s->status |= PARA_STS_ACK;
445 s->status |= PARA_STS_ONLINE;
446 s->status |= PARA_STS_ERROR;
447 s->status |= PARA_STS_TMOUT;
448 s->control = PARA_CTR_SELECT;
449 s->control |= PARA_CTR_INIT;
450 s->control |= 0xc0;
451 s->irq_pending = 0;
452 s->hw_driver = 0;
453 s->epp_timeout = 0;
454 s->last_read_offset = ~0U;
455}
456
457static const int isa_parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
458
459static const MemoryRegionPortio isa_parallel_portio_hw_list[] = {
460 { 0, 8, 1,
461 .read = parallel_ioport_read_hw,
462 .write = parallel_ioport_write_hw },
463 { 4, 1, 2,
464 .read = parallel_ioport_eppdata_read_hw2,
465 .write = parallel_ioport_eppdata_write_hw2 },
466 { 4, 1, 4,
467 .read = parallel_ioport_eppdata_read_hw4,
468 .write = parallel_ioport_eppdata_write_hw4 },
469 { 0x400, 8, 1,
470 .read = parallel_ioport_ecp_read,
471 .write = parallel_ioport_ecp_write },
472 PORTIO_END_OF_LIST(),
473};
474
475static const MemoryRegionPortio isa_parallel_portio_sw_list[] = {
476 { 0, 8, 1,
477 .read = parallel_ioport_read_sw,
478 .write = parallel_ioport_write_sw },
479 PORTIO_END_OF_LIST(),
480};
481
482
483static const VMStateDescription vmstate_parallel_isa = {
484 .name = "parallel_isa",
485 .version_id = 1,
486 .minimum_version_id = 1,
487 .fields = (VMStateField[]) {
488 VMSTATE_UINT8(state.dataw, ISAParallelState),
489 VMSTATE_UINT8(state.datar, ISAParallelState),
490 VMSTATE_UINT8(state.status, ISAParallelState),
491 VMSTATE_UINT8(state.control, ISAParallelState),
492 VMSTATE_INT32(state.irq_pending, ISAParallelState),
493 VMSTATE_INT32(state.epp_timeout, ISAParallelState),
494 VMSTATE_END_OF_LIST()
495 }
496};
497
498
499static void parallel_isa_realizefn(DeviceState *dev, Error **errp)
500{
501 static int index;
502 ISADevice *isadev = ISA_DEVICE(dev);
503 ISAParallelState *isa = ISA_PARALLEL(dev);
504 ParallelState *s = &isa->state;
505 int base;
506 uint8_t dummy;
507
508 if (!s->chr) {
509 error_setg(errp, "Can't create parallel device, empty char device");
510 return;
511 }
512
513 if (isa->index == -1) {
514 isa->index = index;
515 }
516 if (isa->index >= MAX_PARALLEL_PORTS) {
517 error_setg(errp, "Max. supported number of parallel ports is %d.",
518 MAX_PARALLEL_PORTS);
519 return;
520 }
521 if (isa->iobase == -1) {
522 isa->iobase = isa_parallel_io[isa->index];
523 }
524 index++;
525
526 base = isa->iobase;
527 isa_init_irq(isadev, &s->irq, isa->isairq);
528 qemu_register_reset(parallel_reset, s);
529
530 if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
531 s->hw_driver = 1;
532 s->status = dummy;
533 }
534
535 isa_register_portio_list(isadev, base,
536 (s->hw_driver
537 ? &isa_parallel_portio_hw_list[0]
538 : &isa_parallel_portio_sw_list[0]),
539 s, "parallel");
540}
541
542
543static uint32_t parallel_mm_readb (void *opaque, hwaddr addr)
544{
545 ParallelState *s = opaque;
546
547 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFF;
548}
549
550static void parallel_mm_writeb (void *opaque,
551 hwaddr addr, uint32_t value)
552{
553 ParallelState *s = opaque;
554
555 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFF);
556}
557
558static uint32_t parallel_mm_readw (void *opaque, hwaddr addr)
559{
560 ParallelState *s = opaque;
561
562 return parallel_ioport_read_sw(s, addr >> s->it_shift) & 0xFFFF;
563}
564
565static void parallel_mm_writew (void *opaque,
566 hwaddr addr, uint32_t value)
567{
568 ParallelState *s = opaque;
569
570 parallel_ioport_write_sw(s, addr >> s->it_shift, value & 0xFFFF);
571}
572
573static uint32_t parallel_mm_readl (void *opaque, hwaddr addr)
574{
575 ParallelState *s = opaque;
576
577 return parallel_ioport_read_sw(s, addr >> s->it_shift);
578}
579
580static void parallel_mm_writel (void *opaque,
581 hwaddr addr, uint32_t value)
582{
583 ParallelState *s = opaque;
584
585 parallel_ioport_write_sw(s, addr >> s->it_shift, value);
586}
587
588static const MemoryRegionOps parallel_mm_ops = {
589 .old_mmio = {
590 .read = { parallel_mm_readb, parallel_mm_readw, parallel_mm_readl },
591 .write = { parallel_mm_writeb, parallel_mm_writew, parallel_mm_writel },
592 },
593 .endianness = DEVICE_NATIVE_ENDIAN,
594};
595
596
597bool parallel_mm_init(MemoryRegion *address_space,
598 hwaddr base, int it_shift, qemu_irq irq,
599 CharDriverState *chr)
600{
601 ParallelState *s;
602
603 s = g_malloc0(sizeof(ParallelState));
604 s->irq = irq;
605 s->chr = chr;
606 s->it_shift = it_shift;
607 qemu_register_reset(parallel_reset, s);
608
609 memory_region_init_io(&s->iomem, NULL, ¶llel_mm_ops, s,
610 "parallel", 8 << it_shift);
611 memory_region_add_subregion(address_space, base, &s->iomem);
612 return true;
613}
614
615static Property parallel_isa_properties[] = {
616 DEFINE_PROP_UINT32("index", ISAParallelState, index, -1),
617 DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1),
618 DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7),
619 DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr),
620 DEFINE_PROP_END_OF_LIST(),
621};
622
623static void parallel_isa_class_initfn(ObjectClass *klass, void *data)
624{
625 DeviceClass *dc = DEVICE_CLASS(klass);
626
627 dc->realize = parallel_isa_realizefn;
628 dc->vmsd = &vmstate_parallel_isa;
629 dc->props = parallel_isa_properties;
630 set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
631}
632
633static const TypeInfo parallel_isa_info = {
634 .name = TYPE_ISA_PARALLEL,
635 .parent = TYPE_ISA_DEVICE,
636 .instance_size = sizeof(ISAParallelState),
637 .class_init = parallel_isa_class_initfn,
638};
639
640static void parallel_register_types(void)
641{
642 type_register_static(¶llel_isa_info);
643}
644
645type_init(parallel_register_types)
646
