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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "qapi/error.h"
28#include "qemu/timer.h"
29#include "hw/ptimer.h"
30#include "qemu/log.h"
31#include "qemu/main-loop.h"
32
33#include "sysemu/dma.h"
34#include "hw/stream.h"
35
36#define D(x)
37
38#define TYPE_XILINX_AXI_DMA "xlnx.axi-dma"
39#define TYPE_XILINX_AXI_DMA_DATA_STREAM "xilinx-axi-dma-data-stream"
40#define TYPE_XILINX_AXI_DMA_CONTROL_STREAM "xilinx-axi-dma-control-stream"
41
42#define XILINX_AXI_DMA(obj) \
43 OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
44
45#define XILINX_AXI_DMA_DATA_STREAM(obj) \
46 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
47 TYPE_XILINX_AXI_DMA_DATA_STREAM)
48
49#define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
50 OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
51 TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
52
53#define R_DMACR (0x00 / 4)
54#define R_DMASR (0x04 / 4)
55#define R_CURDESC (0x08 / 4)
56#define R_TAILDESC (0x10 / 4)
57#define R_MAX (0x30 / 4)
58
59#define CONTROL_PAYLOAD_WORDS 5
60#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
61
62typedef struct XilinxAXIDMA XilinxAXIDMA;
63typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
64
65enum {
66 DMACR_RUNSTOP = 1,
67 DMACR_TAILPTR_MODE = 2,
68 DMACR_RESET = 4
69};
70
71enum {
72 DMASR_HALTED = 1,
73 DMASR_IDLE = 2,
74 DMASR_IOC_IRQ = 1 << 12,
75 DMASR_DLY_IRQ = 1 << 13,
76
77 DMASR_IRQ_MASK = 7 << 12
78};
79
80struct SDesc {
81 uint64_t nxtdesc;
82 uint64_t buffer_address;
83 uint64_t reserved;
84 uint32_t control;
85 uint32_t status;
86 uint8_t app[CONTROL_PAYLOAD_SIZE];
87};
88
89enum {
90 SDESC_CTRL_EOF = (1 << 26),
91 SDESC_CTRL_SOF = (1 << 27),
92
93 SDESC_CTRL_LEN_MASK = (1 << 23) - 1
94};
95
96enum {
97 SDESC_STATUS_EOF = (1 << 26),
98 SDESC_STATUS_SOF_BIT = 27,
99 SDESC_STATUS_SOF = (1 << SDESC_STATUS_SOF_BIT),
100 SDESC_STATUS_COMPLETE = (1 << 31)
101};
102
103struct Stream {
104 QEMUBH *bh;
105 ptimer_state *ptimer;
106 qemu_irq irq;
107
108 int nr;
109
110 struct SDesc desc;
111 int pos;
112 unsigned int complete_cnt;
113 uint32_t regs[R_MAX];
114 uint8_t app[20];
115
116 MemoryRegion *data_mr;
117 AddressSpace *data_as;
118 AddressSpace *sg_as;
119};
120
121struct XilinxAXIDMAStreamSlave {
122 Object parent;
123
124 struct XilinxAXIDMA *dma;
125};
126
127struct XilinxAXIDMA {
128 SysBusDevice busdev;
129 MemoryRegion iomem;
130 uint32_t freqhz;
131 StreamSlave *tx_data_dev;
132 StreamSlave *tx_control_dev;
133 XilinxAXIDMAStreamSlave rx_data_dev;
134 XilinxAXIDMAStreamSlave rx_control_dev;
135
136 struct Stream streams[2];
137
138 MemoryRegion *sg_mr;
139
140 StreamCanPushNotifyFn notify;
141 void *notify_opaque;
142};
143
144
145
146
147
148static inline int stream_desc_sof(struct SDesc *d)
149{
150 return d->control & SDESC_CTRL_SOF;
151}
152
153static inline int stream_desc_eof(struct SDesc *d)
154{
155 return d->control & SDESC_CTRL_EOF;
156}
157
158static inline int stream_resetting(struct Stream *s)
159{
160 return !!(s->regs[R_DMACR] & DMACR_RESET);
161}
162
163static inline int stream_running(struct Stream *s)
164{
165 return s->regs[R_DMACR] & DMACR_RUNSTOP &&
166 !(s->regs[R_DMASR] & DMASR_HALTED);
167}
168
169static inline int stream_idle(struct Stream *s)
170{
171 return !!(s->regs[R_DMASR] & DMASR_IDLE);
172}
173
174static void stream_reset(struct Stream *s)
175{
176 s->regs[R_DMASR] = DMASR_HALTED;
177 s->regs[R_DMACR] = 1 << 16;
178}
179
180
181static inline int streamid_from_addr(hwaddr addr)
182{
183 int sid;
184
185 sid = addr / (0x30);
186 sid &= 1;
187 return sid;
188}
189
190static void stream_desc_load(struct Stream *s, hwaddr addr)
191{
192 struct SDesc *d = &s->desc;
193
194 dma_memory_read(s->sg_as, addr, d, sizeof *d);
195
196
197 d->buffer_address = le64_to_cpu(d->buffer_address);
198 d->nxtdesc = le64_to_cpu(d->nxtdesc);
199 d->control = le32_to_cpu(d->control);
200 d->status = le32_to_cpu(d->status);
201}
202
203static void stream_desc_store(struct Stream *s, hwaddr addr)
204{
205 struct SDesc *d = &s->desc;
206
207
208 d->buffer_address = cpu_to_le64(d->buffer_address);
209 d->nxtdesc = cpu_to_le64(d->nxtdesc);
210 d->control = cpu_to_le32(d->control);
211 d->status = cpu_to_le32(d->status);
212 dma_memory_write(s->sg_as, addr, d, sizeof *d);
213}
214
215static void stream_update_irq(struct Stream *s)
216{
217 unsigned int pending, mask, irq;
218
219 pending = s->regs[R_DMASR] & DMASR_IRQ_MASK;
220 mask = s->regs[R_DMACR] & DMASR_IRQ_MASK;
221
222 irq = pending & mask;
223
224 qemu_set_irq(s->irq, !!irq);
225}
226
227static void stream_reload_complete_cnt(struct Stream *s)
228{
229 unsigned int comp_th;
230 comp_th = (s->regs[R_DMACR] >> 16) & 0xff;
231 s->complete_cnt = comp_th;
232}
233
234static void timer_hit(void *opaque)
235{
236 struct Stream *s = opaque;
237
238 stream_reload_complete_cnt(s);
239 s->regs[R_DMASR] |= DMASR_DLY_IRQ;
240 stream_update_irq(s);
241}
242
243static void stream_complete(struct Stream *s)
244{
245 unsigned int comp_delay;
246
247
248 comp_delay = s->regs[R_DMACR] >> 24;
249 if (comp_delay) {
250 ptimer_stop(s->ptimer);
251 ptimer_set_count(s->ptimer, comp_delay);
252 ptimer_run(s->ptimer, 1);
253 }
254
255 s->complete_cnt--;
256 if (s->complete_cnt == 0) {
257
258 s->regs[R_DMASR] |= DMASR_IOC_IRQ;
259 stream_reload_complete_cnt(s);
260 }
261}
262
263static void stream_process_mem2s(struct Stream *s, StreamSlave *tx_data_dev,
264 StreamSlave *tx_control_dev)
265{
266 uint32_t prev_d;
267 unsigned char txbuf[16 * 1024];
268 unsigned int txlen;
269
270 if (!stream_running(s) || stream_idle(s)) {
271 return;
272 }
273
274 while (1) {
275 stream_desc_load(s, s->regs[R_CURDESC]);
276
277 if (s->desc.status & SDESC_STATUS_COMPLETE) {
278 s->regs[R_DMASR] |= DMASR_HALTED;
279 break;
280 }
281
282 if (stream_desc_sof(&s->desc)) {
283 s->pos = 0;
284 stream_push(tx_control_dev, s->desc.app, sizeof(s->desc.app),
285 STREAM_ATTR_EOP);
286 }
287
288 txlen = s->desc.control & SDESC_CTRL_LEN_MASK;
289 if ((txlen + s->pos) > sizeof txbuf) {
290 hw_error("%s: too small internal txbuf! %d\n", __func__,
291 txlen + s->pos);
292 }
293
294 dma_memory_read(s->data_as, s->desc.buffer_address,
295 txbuf + s->pos, txlen);
296 s->pos += txlen;
297
298 if (stream_desc_eof(&s->desc)) {
299 stream_push(tx_data_dev, txbuf, s->pos, STREAM_ATTR_EOP);
300 s->pos = 0;
301 stream_complete(s);
302 }
303
304
305 s->desc.status = txlen | SDESC_STATUS_COMPLETE;
306 stream_desc_store(s, s->regs[R_CURDESC]);
307
308
309 prev_d = s->regs[R_CURDESC];
310 s->regs[R_CURDESC] = s->desc.nxtdesc;
311 if (prev_d == s->regs[R_TAILDESC]) {
312 s->regs[R_DMASR] |= DMASR_IDLE;
313 break;
314 }
315 }
316}
317
318static size_t stream_process_s2mem(struct Stream *s, unsigned char *buf,
319 size_t len, uint32_t attr)
320{
321 uint32_t prev_d;
322 unsigned int rxlen;
323 size_t pos = 0;
324 int sof = 1;
325
326 if (!stream_running(s) || stream_idle(s)) {
327 return 0;
328 }
329
330 while (len) {
331 stream_desc_load(s, s->regs[R_CURDESC]);
332
333 if (s->desc.status & SDESC_STATUS_COMPLETE) {
334 s->regs[R_DMASR] |= DMASR_HALTED;
335 break;
336 }
337
338 rxlen = s->desc.control & SDESC_CTRL_LEN_MASK;
339 if (rxlen > len) {
340
341 rxlen = len;
342 }
343
344 dma_memory_write(s->data_as, s->desc.buffer_address, buf + pos, rxlen);
345 len -= rxlen;
346 pos += rxlen;
347
348
349 if (!len && stream_attr_has_eop(attr)) {
350 stream_complete(s);
351 memcpy(s->desc.app, s->app, sizeof(s->desc.app));
352 s->desc.status |= SDESC_STATUS_EOF;
353 }
354
355 s->desc.status |= sof << SDESC_STATUS_SOF_BIT;
356 s->desc.status |= SDESC_STATUS_COMPLETE;
357 stream_desc_store(s, s->regs[R_CURDESC]);
358 sof = 0;
359
360
361 prev_d = s->regs[R_CURDESC];
362 s->regs[R_CURDESC] = s->desc.nxtdesc;
363 if (prev_d == s->regs[R_TAILDESC]) {
364 s->regs[R_DMASR] |= DMASR_IDLE;
365 break;
366 }
367 }
368
369 return pos;
370}
371
372static void xilinx_axidma_reset(DeviceState *dev)
373{
374 int i;
375 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
376
377 for (i = 0; i < 2; i++) {
378 stream_reset(&s->streams[i]);
379 }
380}
381
382static size_t
383xilinx_axidma_control_stream_push(StreamSlave *obj, unsigned char *buf,
384 size_t len, uint32_t attr)
385{
386 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
387 struct Stream *s = &cs->dma->streams[1];
388
389 if (len != CONTROL_PAYLOAD_SIZE) {
390 hw_error("AXI DMA requires %d byte control stream payload\n",
391 (int)CONTROL_PAYLOAD_SIZE);
392 }
393
394 memcpy(s->app, buf, len);
395 return len;
396}
397
398static bool
399xilinx_axidma_data_stream_can_push(StreamSlave *obj,
400 StreamCanPushNotifyFn notify,
401 void *notify_opaque)
402{
403 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
404 struct Stream *s = &ds->dma->streams[1];
405
406 if (!stream_running(s) || stream_idle(s)) {
407 ds->dma->notify = notify;
408 ds->dma->notify_opaque = notify_opaque;
409 return false;
410 }
411
412 return true;
413}
414
415static size_t
416xilinx_axidma_data_stream_push(StreamSlave *obj, unsigned char *buf, size_t len,
417 uint32_t attr)
418{
419 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
420 struct Stream *s = &ds->dma->streams[1];
421 size_t ret;
422
423 ret = stream_process_s2mem(s, buf, len, attr);
424 stream_update_irq(s);
425 return ret;
426}
427
428static uint64_t axidma_read(void *opaque, hwaddr addr,
429 unsigned size)
430{
431 XilinxAXIDMA *d = opaque;
432 struct Stream *s;
433 uint32_t r = 0;
434 int sid;
435
436 sid = streamid_from_addr(addr);
437 s = &d->streams[sid];
438
439 addr = addr % 0x30;
440 addr >>= 2;
441 switch (addr) {
442 case R_DMACR:
443
444 s->regs[addr] &= ~DMACR_RESET;
445 r = s->regs[addr];
446 break;
447 case R_DMASR:
448 s->regs[addr] &= 0xffff;
449 s->regs[addr] |= (s->complete_cnt & 0xff) << 16;
450 s->regs[addr] |= (ptimer_get_count(s->ptimer) & 0xff) << 24;
451 r = s->regs[addr];
452 break;
453 default:
454 r = s->regs[addr];
455 D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n",
456 __func__, sid, addr * 4, r));
457 break;
458 }
459 return r;
460
461}
462
463static void axidma_write(void *opaque, hwaddr addr,
464 uint64_t value, unsigned size)
465{
466 XilinxAXIDMA *d = opaque;
467 struct Stream *s;
468 int sid;
469
470 sid = streamid_from_addr(addr);
471 s = &d->streams[sid];
472
473 addr = addr % 0x30;
474 addr >>= 2;
475 switch (addr) {
476 case R_DMACR:
477
478 value |= DMACR_TAILPTR_MODE;
479
480 value |= (s->regs[addr] & DMACR_RESET);
481 s->regs[addr] = value;
482
483 if (value & DMACR_RESET) {
484 stream_reset(s);
485 }
486
487 if ((value & 1) && !stream_resetting(s)) {
488
489 s->regs[R_DMASR] &= ~(DMASR_HALTED | DMASR_IDLE);
490 }
491 stream_reload_complete_cnt(s);
492 break;
493
494 case R_DMASR:
495
496 value &= ~(value & DMASR_IRQ_MASK);
497 s->regs[addr] = value;
498 break;
499
500 case R_TAILDESC:
501 s->regs[addr] = value;
502 s->regs[R_DMASR] &= ~DMASR_IDLE;
503 if (!sid) {
504 stream_process_mem2s(s, d->tx_data_dev, d->tx_control_dev);
505 }
506 break;
507 default:
508 D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n",
509 __func__, sid, addr * 4, (unsigned)value));
510 s->regs[addr] = value;
511 break;
512 }
513 if (sid == 1 && d->notify) {
514 StreamCanPushNotifyFn notifytmp = d->notify;
515 d->notify = NULL;
516 notifytmp(d->notify_opaque);
517 }
518 stream_update_irq(s);
519}
520
521static const MemoryRegionOps axidma_ops = {
522 .read = axidma_read,
523 .write = axidma_write,
524 .endianness = DEVICE_NATIVE_ENDIAN,
525};
526
527static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
528{
529 XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
530 XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
531 XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
532 &s->rx_control_dev);
533 Error *local_err = NULL;
534 AddressSpace *sg_as;
535
536 object_property_add_link(OBJECT(ds), "dma", TYPE_XILINX_AXI_DMA,
537 (Object **)&ds->dma,
538 object_property_allow_set_link,
539 OBJ_PROP_LINK_UNREF_ON_RELEASE,
540 &local_err);
541 object_property_add_link(OBJECT(cs), "dma", TYPE_XILINX_AXI_DMA,
542 (Object **)&cs->dma,
543 object_property_allow_set_link,
544 OBJ_PROP_LINK_UNREF_ON_RELEASE,
545 &local_err);
546 if (local_err) {
547 goto xilinx_axidma_realize_fail;
548 }
549 object_property_set_link(OBJECT(ds), OBJECT(s), "dma", &local_err);
550 object_property_set_link(OBJECT(cs), OBJECT(s), "dma", &local_err);
551 if (local_err) {
552 goto xilinx_axidma_realize_fail;
553 }
554
555 int i;
556
557 sg_as = address_space_init_shareable(s->sg_mr, NULL);
558
559 for (i = 0; i < 2; i++) {
560 struct Stream *st = &s->streams[i];
561
562 st->nr = i;
563 st->bh = qemu_bh_new(timer_hit, st);
564 st->ptimer = ptimer_init(st->bh);
565 ptimer_set_freq(st->ptimer, s->freqhz);
566 st->data_as = address_space_init_shareable(st->data_mr, NULL);
567 st->sg_as = sg_as;
568 }
569 return;
570
571xilinx_axidma_realize_fail:
572 if (!*errp) {
573 *errp = local_err;
574 }
575}
576
577static void xilinx_axidma_init(Object *obj)
578{
579 XilinxAXIDMA *s = XILINX_AXI_DMA(obj);
580 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
581
582 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
583 (Object **)&s->tx_data_dev,
584 qdev_prop_allow_set_link_before_realize,
585 OBJ_PROP_LINK_UNREF_ON_RELEASE,
586 &error_abort);
587 object_property_add_link(obj, "axistream-control-connected",
588 TYPE_STREAM_SLAVE,
589 (Object **)&s->tx_control_dev,
590 qdev_prop_allow_set_link_before_realize,
591 OBJ_PROP_LINK_UNREF_ON_RELEASE,
592 &error_abort);
593
594 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
595 TYPE_XILINX_AXI_DMA_DATA_STREAM);
596 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
597 TYPE_XILINX_AXI_DMA_CONTROL_STREAM);
598 object_property_add_child(OBJECT(s), "axistream-connected-target",
599 (Object *)&s->rx_data_dev, &error_abort);
600 object_property_add_child(OBJECT(s), "axistream-control-connected-target",
601 (Object *)&s->rx_control_dev, &error_abort);
602
603 sysbus_init_irq(sbd, &s->streams[0].irq);
604 sysbus_init_irq(sbd, &s->streams[1].irq);
605
606 memory_region_init_io(&s->iomem, obj, &axidma_ops, s,
607 "xlnx.axi-dma", R_MAX * 4 * 2);
608 sysbus_init_mmio(sbd, &s->iomem);
609
610 object_property_add_link(obj, "mm2s", TYPE_MEMORY_REGION,
611 (Object **)&s->streams[0].data_mr,
612 qdev_prop_allow_set_link_before_realize,
613 OBJ_PROP_LINK_UNREF_ON_RELEASE,
614 &error_abort);
615 object_property_add_link(obj, "s2mm", TYPE_MEMORY_REGION,
616 (Object **)&s->streams[1].data_mr,
617 qdev_prop_allow_set_link_before_realize,
618 OBJ_PROP_LINK_UNREF_ON_RELEASE,
619 &error_abort);
620 object_property_add_link(obj, "sg", TYPE_MEMORY_REGION,
621 (Object **)&s->sg_mr,
622 qdev_prop_allow_set_link_before_realize,
623 OBJ_PROP_LINK_UNREF_ON_RELEASE,
624 &error_abort);
625}
626
627static Property axidma_properties[] = {
628 DEFINE_PROP_UINT32("freqhz", XilinxAXIDMA, freqhz, 50000000),
629 DEFINE_PROP_END_OF_LIST(),
630};
631
632static void axidma_class_init(ObjectClass *klass, void *data)
633{
634 DeviceClass *dc = DEVICE_CLASS(klass);
635
636 dc->realize = xilinx_axidma_realize,
637 dc->reset = xilinx_axidma_reset;
638 dc->props = axidma_properties;
639}
640
641static StreamSlaveClass xilinx_axidma_data_stream_class = {
642 .push = xilinx_axidma_data_stream_push,
643 .can_push = xilinx_axidma_data_stream_can_push,
644};
645
646static StreamSlaveClass xilinx_axidma_control_stream_class = {
647 .push = xilinx_axidma_control_stream_push,
648};
649
650static void xilinx_axidma_stream_class_init(ObjectClass *klass, void *data)
651{
652 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
653
654 ssc->push = ((StreamSlaveClass *)data)->push;
655 ssc->can_push = ((StreamSlaveClass *)data)->can_push;
656}
657
658static const TypeInfo axidma_info = {
659 .name = TYPE_XILINX_AXI_DMA,
660 .parent = TYPE_SYS_BUS_DEVICE,
661 .instance_size = sizeof(XilinxAXIDMA),
662 .class_init = axidma_class_init,
663 .instance_init = xilinx_axidma_init,
664};
665
666static const TypeInfo xilinx_axidma_data_stream_info = {
667 .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
668 .parent = TYPE_OBJECT,
669 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
670 .class_init = xilinx_axidma_stream_class_init,
671 .class_data = &xilinx_axidma_data_stream_class,
672 .interfaces = (InterfaceInfo[]) {
673 { TYPE_STREAM_SLAVE },
674 { }
675 }
676};
677
678static const TypeInfo xilinx_axidma_control_stream_info = {
679 .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
680 .parent = TYPE_OBJECT,
681 .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
682 .class_init = xilinx_axidma_stream_class_init,
683 .class_data = &xilinx_axidma_control_stream_class,
684 .interfaces = (InterfaceInfo[]) {
685 { TYPE_STREAM_SLAVE },
686 { }
687 }
688};
689
690static void xilinx_axidma_register_types(void)
691{
692 type_register_static(&axidma_info);
693 type_register_static(&xilinx_axidma_data_stream_info);
694 type_register_static(&xilinx_axidma_control_stream_info);
695}
696
697type_init(xilinx_axidma_register_types)
698
