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28#include "qemu/osdep.h"
29#include "hw/sysbus.h"
30#include "qemu/log.h"
31
32#include "qemu/bitops.h"
33#include "qapi/qmp/qerror.h"
34#include "hw/register.h"
35
36#ifndef XILINX_CSU_CORE_ERR_DEBUG
37#define XILINX_CSU_CORE_ERR_DEBUG 0
38#endif
39
40#define TYPE_XILINX_CSU_CORE "xlnx.zynqmp-csu-core"
41
42#define XILINX_CSU_CORE(obj) \
43 OBJECT_CHECK(CSU, (obj), TYPE_XILINX_CSU_CORE)
44
45#define XFSBL_PLATFORM_QEMU 0X00003000U
46#define QEMU_IDCODE 0x4600093
47
48REG32(CSU_STATUS, 0x0)
49 FIELD(CSU_STATUS, BOOT_ENC, 1, 1)
50 FIELD(CSU_STATUS, BOOT_AUTH, 1, 0)
51REG32(CSU_CTRL, 0x4)
52 FIELD(CSU_CTRL, SLVERR_ENABLE, 1, 4)
53 FIELD(CSU_CTRL, CSU_CLK_SEL, 1, 0)
54REG32(CSU_SSS_CFG, 0x8)
55 FIELD(CSU_SSS_CFG, SHA_SSS, 4, 12)
56 FIELD(CSU_SSS_CFG, AES_SSS, 4, 8)
57 FIELD(CSU_SSS_CFG, DMA_SSS, 4, 4)
58 FIELD(CSU_SSS_CFG, PCAP_SSS, 4, 0)
59REG32(CSU_DMA_RESET, 0xc)
60 FIELD(CSU_DMA_RESET, RESET, 1, 0)
61REG32(CSU_MULTI_BOOT, 0x10)
62REG32(CSU_TAMPER_TRIG, 0x14)
63 FIELD(CSU_TAMPER_TRIG, TAMPER, 1, 0)
64REG32(CSU_FT_STATUS, 0x18)
65 FIELD(CSU_FT_STATUS, R_UE, 1, 31)
66 FIELD(CSU_FT_STATUS, R_VOTER_ERROR, 1, 30)
67 FIELD(CSU_FT_STATUS, R_COMP_ERR_23, 1, 29)
68 FIELD(CSU_FT_STATUS, R_COMP_ERR_13, 1, 28)
69 FIELD(CSU_FT_STATUS, R_COMP_ERR_12, 1, 27)
70 FIELD(CSU_FT_STATUS, R_MISMATCH_23_A, 1, 26)
71 FIELD(CSU_FT_STATUS, R_MISMATCH_13_A, 1, 25)
72 FIELD(CSU_FT_STATUS, R_MISMATCH_12_A, 1, 24)
73 FIELD(CSU_FT_STATUS, R_FT_ST_MISMATCH, 1, 23)
74 FIELD(CSU_FT_STATUS, R_CPU_ID_MISMATCH, 1, 22)
75 FIELD(CSU_FT_STATUS, R_SLEEP_RESET, 1, 19)
76 FIELD(CSU_FT_STATUS, R_MISMATCH_23_B, 1, 18)
77 FIELD(CSU_FT_STATUS, R_MISMATCH_13_B, 1, 17)
78 FIELD(CSU_FT_STATUS, R_MISMATCH_12_B, 1, 16)
79 FIELD(CSU_FT_STATUS, N_UE, 1, 15)
80 FIELD(CSU_FT_STATUS, N_VOTER_ERROR, 1, 14)
81 FIELD(CSU_FT_STATUS, N_COMP_ERR_23, 1, 13)
82 FIELD(CSU_FT_STATUS, N_COMP_ERR_13, 1, 12)
83 FIELD(CSU_FT_STATUS, N_COMP_ERR_12, 1, 11)
84 FIELD(CSU_FT_STATUS, N_MISMATCH_23_A, 1, 10)
85 FIELD(CSU_FT_STATUS, N_MISMATCH_13_A, 1, 9)
86 FIELD(CSU_FT_STATUS, N_MISMATCH_12_A, 1, 8)
87 FIELD(CSU_FT_STATUS, N_FT_ST_MISMATCH, 1, 7)
88 FIELD(CSU_FT_STATUS, N_CPU_ID_MISMATCH, 1, 6)
89 FIELD(CSU_FT_STATUS, N_SLEEP_RESET, 1, 3)
90 FIELD(CSU_FT_STATUS, N_MISMATCH_23_B, 1, 2)
91 FIELD(CSU_FT_STATUS, N_MISMATCH_13_B, 1, 1)
92 FIELD(CSU_FT_STATUS, N_MISMATCH_12_B, 1, 0)
93REG32(CSU_ISR, 0x20)
94 FIELD(CSU_ISR, CSU_PL_ISO, 1, 15)
95 FIELD(CSU_ISR, CSU_RAM_ECC_ERROR, 1, 14)
96 FIELD(CSU_ISR, TAMPER, 1, 13)
97 FIELD(CSU_ISR, APB_SLVERR, 1, 11)
98 FIELD(CSU_ISR, TMR_FATAL, 1, 10)
99 FIELD(CSU_ISR, PL_SEU_ERROR, 1, 9)
100 FIELD(CSU_ISR, AES_ERROR, 1, 8)
101 FIELD(CSU_ISR, PCAP_WR_OVERFLOW, 1, 7)
102 FIELD(CSU_ISR, PCAP_RD_OVERFLOW, 1, 6)
103 FIELD(CSU_ISR, PL_POR_B, 1, 5)
104 FIELD(CSU_ISR, PL_INIT, 1, 4)
105 FIELD(CSU_ISR, PL_DONE, 1, 3)
106 FIELD(CSU_ISR, SHA_DONE, 1, 2)
107 FIELD(CSU_ISR, RSA_DONE, 1, 1)
108 FIELD(CSU_ISR, AES_DONE, 1, 0)
109REG32(CSU_IMR, 0x24)
110 FIELD(CSU_IMR, CSU_PL_ISO, 1, 15)
111 FIELD(CSU_IMR, CSU_RAM_ECC_ERROR, 1, 14)
112 FIELD(CSU_IMR, TAMPER, 1, 13)
113 FIELD(CSU_IMR, APB_SLVERR, 1, 11)
114 FIELD(CSU_IMR, TMR_FATAL, 1, 10)
115 FIELD(CSU_IMR, PL_SEU_ERROR, 1, 9)
116 FIELD(CSU_IMR, AES_ERROR, 1, 8)
117 FIELD(CSU_IMR, PCAP_WR_OVERFLOW, 1, 7)
118 FIELD(CSU_IMR, PCAP_RD_OVERFLOW, 1, 6)
119 FIELD(CSU_IMR, PL_POR_B, 1, 5)
120 FIELD(CSU_IMR, PL_INIT, 1, 4)
121 FIELD(CSU_IMR, PL_DONE, 1, 3)
122 FIELD(CSU_IMR, SHA_DONE, 1, 2)
123 FIELD(CSU_IMR, RSA_DONE, 1, 1)
124 FIELD(CSU_IMR, AES_DONE, 1, 0)
125REG32(CSU_IER, 0x28)
126 FIELD(CSU_IER, CSU_PL_ISO, 1, 15)
127 FIELD(CSU_IER, CSU_RAM_ECC_ERROR, 1, 14)
128 FIELD(CSU_IER, TAMPER, 1, 13)
129 FIELD(CSU_IER, APB_SLVERR, 1, 11)
130 FIELD(CSU_IER, TMR_FATAL, 1, 10)
131 FIELD(CSU_IER, PL_SEU_ERROR, 1, 9)
132 FIELD(CSU_IER, AES_ERROR, 1, 8)
133 FIELD(CSU_IER, PCAP_WR_OVERFLOW, 1, 7)
134 FIELD(CSU_IER, PCAP_RD_OVERFLOW, 1, 6)
135 FIELD(CSU_IER, PL_POR_B, 1, 5)
136 FIELD(CSU_IER, PL_INIT, 1, 4)
137 FIELD(CSU_IER, PL_DONE, 1, 3)
138 FIELD(CSU_IER, SHA_DONE, 1, 2)
139 FIELD(CSU_IER, RSA_DONE, 1, 1)
140 FIELD(CSU_IER, AES_DONE, 1, 0)
141REG32(CSU_IDR, 0x2c)
142 FIELD(CSU_IDR, CSU_PL_ISO, 1, 15)
143 FIELD(CSU_IDR, CSU_RAM_ECC_ERROR, 1, 14)
144 FIELD(CSU_IDR, TAMPER, 1, 13)
145 FIELD(CSU_IDR, APB_SLVERR, 1, 11)
146 FIELD(CSU_IDR, TMR_FATAL, 1, 10)
147 FIELD(CSU_IDR, PL_SEU_ERROR, 1, 9)
148 FIELD(CSU_IDR, AES_ERROR, 1, 8)
149 FIELD(CSU_IDR, PCAP_WR_OVERFLOW, 1, 7)
150 FIELD(CSU_IDR, PCAP_RD_OVERFLOW, 1, 6)
151 FIELD(CSU_IDR, PL_POR_B, 1, 5)
152 FIELD(CSU_IDR, PL_INIT, 1, 4)
153 FIELD(CSU_IDR, PL_DONE, 1, 3)
154 FIELD(CSU_IDR, SHA_DONE, 1, 2)
155 FIELD(CSU_IDR, RSA_DONE, 1, 1)
156 FIELD(CSU_IDR, AES_DONE, 1, 0)
157REG32(JTAG_CHAIN_STATUS, 0x34)
158 FIELD(JTAG_CHAIN_STATUS, ARM_DAP, 1, 1)
159 FIELD(JTAG_CHAIN_STATUS, PL_TAP, 1, 0)
160REG32(JTAG_SEC, 0x38)
161 FIELD(JTAG_SEC, SSSS_PMU_SEC, 3, 6)
162 FIELD(JTAG_SEC, SSSS_PLTAP_SEC, 3, 3)
163 FIELD(JTAG_SEC, SSSS_DAP_SEC, 3, 0)
164REG32(JTAG_DAP_CFG, 0x3c)
165 FIELD(JTAG_DAP_CFG, SSSS_RPU_NIDEN, 1, 5)
166 FIELD(JTAG_DAP_CFG, SSSS_RPU_DBGEN, 1, 4)
167 FIELD(JTAG_DAP_CFG, SSSS_APU_SPNIDEN, 1, 3)
168 FIELD(JTAG_DAP_CFG, SSSS_APU_SPIDEN, 1, 2)
169 FIELD(JTAG_DAP_CFG, SSSS_APU_NIDEN, 1, 1)
170 FIELD(JTAG_DAP_CFG, SSSS_APU_DBGEN, 1, 0)
171REG32(IDCODE, 0x40)
172REG32(VERSION, 0x44)
173 FIELD(VERSION, PS_VERSION, 4, 0)
174REG32(CSU_ROM_DIGEST_0, 0x50)
175REG32(CSU_ROM_DIGEST_1, 0x54)
176REG32(CSU_ROM_DIGEST_2, 0x58)
177REG32(CSU_ROM_DIGEST_3, 0x5C)
178REG32(CSU_ROM_DIGEST_4, 0x60)
179REG32(CSU_ROM_DIGEST_5, 0x64)
180REG32(CSU_ROM_DIGEST_6, 0x68)
181REG32(CSU_ROM_DIGEST_7, 0x6C)
182REG32(CSU_ROM_DIGEST_8, 0x70)
183REG32(CSU_ROM_DIGEST_9, 0x74)
184REG32(CSU_ROM_DIGEST_10, 0x78)
185REG32(CSU_ROM_DIGEST_11, 0x7C)
186REG32(AES_STATUS, 0x1000)
187 FIELD(AES_STATUS, OKR_ZEROED, 1, 11)
188 FIELD(AES_STATUS, BOOT_ZEROED, 1, 10)
189 FIELD(AES_STATUS, KUP_ZEROED, 1, 9)
190 FIELD(AES_STATUS, AES_KEY_ZEROED, 1, 8)
191 FIELD(AES_STATUS, KEY_INIT_DONE, 1, 4)
192 FIELD(AES_STATUS, GCM_TAG_PASS, 1, 3)
193 FIELD(AES_STATUS, DONE, 1, 2)
194 FIELD(AES_STATUS, READY, 1, 1)
195 FIELD(AES_STATUS, BUSY, 1, 0)
196REG32(AES_KEY_SRC, 0x1004)
197 FIELD(AES_KEY_SRC, KEY_SRC, 4, 0)
198REG32(AES_KEY_LOAD, 0x1008)
199 FIELD(AES_KEY_LOAD, KEY_LOAD, 1, 0)
200REG32(AES_START_MSG, 0x100c)
201 FIELD(AES_START_MSG, START_MSG, 1, 0)
202REG32(AES_RESET, 0x1010)
203 FIELD(AES_RESET, RESET, 1, 0)
204REG32(AES_KEY_CLEAR, 0x1014)
205 FIELD(AES_KEY_CLEAR, AES_KUP_ZERO, 1, 1)
206 FIELD(AES_KEY_CLEAR, AES_KEY_ZERO, 1, 0)
207REG32(AES_KUP_WR, 0x101c)
208 FIELD(AES_KUP_WR, IV_WRITE, 1, 1)
209 FIELD(AES_KUP_WR, KUP_WRITE, 1, 0)
210REG32(AES_KUP_0, 0x1020)
211REG32(AES_KUP_1, 0x1024)
212REG32(AES_KUP_2, 0x1028)
213REG32(AES_KUP_3, 0x102c)
214REG32(AES_KUP_4, 0x1030)
215REG32(AES_KUP_5, 0x1034)
216REG32(AES_KUP_6, 0x1038)
217REG32(AES_KUP_7, 0x103c)
218REG32(AES_IV_0, 0x1040)
219REG32(AES_IV_1, 0x1044)
220REG32(AES_IV_2, 0x1048)
221REG32(AES_IV_3, 0x104c)
222REG32(SHA_START, 0x2000)
223 FIELD(SHA_START, START_MSG, 1, 0)
224REG32(SHA_RESET, 0x2004)
225 FIELD(SHA_RESET, RESET, 1, 0)
226REG32(SHA_DONE, 0x2008)
227 FIELD(SHA_DONE, SHA_DONE, 1, 0)
228REG32(SHA_DIGEST_0, 0x2010)
229REG32(SHA_DIGEST_1, 0x2014)
230REG32(SHA_DIGEST_2, 0x2018)
231REG32(SHA_DIGEST_3, 0x201c)
232REG32(SHA_DIGEST_4, 0x2020)
233REG32(SHA_DIGEST_5, 0x2024)
234REG32(SHA_DIGEST_6, 0x2028)
235REG32(SHA_DIGEST_7, 0x202c)
236REG32(SHA_DIGEST_8, 0x2030)
237REG32(SHA_DIGEST_9, 0x2034)
238REG32(SHA_DIGEST_10, 0x2038)
239REG32(SHA_DIGEST_11, 0x203c)
240REG32(PCAP_PROG, 0x3000)
241 FIELD(PCAP_PROG, PCFG_PROG_B, 1, 0)
242REG32(PCAP_RDWR, 0x3004)
243 FIELD(PCAP_RDWR, PCAP_RDWR_B, 1, 0)
244REG32(PCAP_CTRL, 0x3008)
245 FIELD(PCAP_CTRL, PCFG_GSR, 1, 3)
246 FIELD(PCAP_CTRL, PCFG_GTS, 1, 2)
247 FIELD(PCAP_CTRL, PCFG_POR_CNT_4K, 1, 1)
248 FIELD(PCAP_CTRL, PCAP_PR, 1, 0)
249REG32(PCAP_RESET, 0x300c)
250 FIELD(PCAP_RESET, RESET, 1, 0)
251REG32(PCAP_STATUS, 0x3010)
252 FIELD(PCAP_STATUS, PCFG_GWE, 1, 13)
253 FIELD(PCAP_STATUS, PCFG_MCAP_MODE, 1, 12)
254 FIELD(PCAP_STATUS, PL_GTS_USR_B, 1, 11)
255 FIELD(PCAP_STATUS, PL_GTS_CFG_B, 1, 10)
256 FIELD(PCAP_STATUS, PL_GPWRDWN_B, 1, 9)
257 FIELD(PCAP_STATUS, PL_GHIGH_B, 1, 8)
258 FIELD(PCAP_STATUS, PL_FST_CFG, 1, 7)
259 FIELD(PCAP_STATUS, PL_CFG_RESET_B, 1, 6)
260 FIELD(PCAP_STATUS, PL_SEU_ERROR, 1, 5)
261 FIELD(PCAP_STATUS, PL_EOS, 1, 4)
262 FIELD(PCAP_STATUS, PL_DONE, 1, 3)
263 FIELD(PCAP_STATUS, PL_INIT, 1, 2)
264 FIELD(PCAP_STATUS, PCAP_RD_IDLE, 1, 1)
265 FIELD(PCAP_STATUS, PCAP_WR_IDLE, 1, 0)
266REG32(TAMPER_STATUS, 0x5000)
267 FIELD(TAMPER_STATUS, TAMPER_13, 1, 13)
268 FIELD(TAMPER_STATUS, TAMPER_12, 1, 12)
269 FIELD(TAMPER_STATUS, TAMPER_11, 1, 11)
270 FIELD(TAMPER_STATUS, TAMPER_10, 1, 10)
271 FIELD(TAMPER_STATUS, TAMPER_9, 1, 9)
272 FIELD(TAMPER_STATUS, TAMPER_8, 1, 8)
273 FIELD(TAMPER_STATUS, TAMPER_7, 1, 7)
274 FIELD(TAMPER_STATUS, TAMPER_6, 1, 6)
275 FIELD(TAMPER_STATUS, TAMPER_5, 1, 5)
276 FIELD(TAMPER_STATUS, TAMPER_4, 1, 4)
277 FIELD(TAMPER_STATUS, TAMPER_3, 1, 3)
278 FIELD(TAMPER_STATUS, TAMPER_2, 1, 2)
279 FIELD(TAMPER_STATUS, TAMPER_1, 1, 1)
280 FIELD(TAMPER_STATUS, TAMPER_0, 1, 0)
281REG32(CSU_TAMPER_0, 0x5004)
282 FIELD(CSU_TAMPER_0, BBRAM_ERASE, 1, 5)
283 FIELD(CSU_TAMPER_0, SEC_LOCKDOWN_1, 1, 3)
284 FIELD(CSU_TAMPER_0, SEC_LOCKDOWN_0, 1, 2)
285 FIELD(CSU_TAMPER_0, SYS_RESET, 1, 1)
286 FIELD(CSU_TAMPER_0, SYS_INTERRUPT, 1, 0)
287REG32(CSU_TAMPER_1, 0x5008)
288 FIELD(CSU_TAMPER_1, BBRAM_ERASE, 1, 5)
289 FIELD(CSU_TAMPER_1, SEC_LOCKDOWN_1, 1, 3)
290 FIELD(CSU_TAMPER_1, SEC_LOCKDOWN_0, 1, 2)
291 FIELD(CSU_TAMPER_1, SYS_RESET, 1, 1)
292 FIELD(CSU_TAMPER_1, SYS_INTERRUPT, 1, 0)
293REG32(CSU_TAMPER_2, 0x500C)
294 FIELD(CSU_TAMPER_2, BBRAM_ERASE, 1, 5)
295 FIELD(CSU_TAMPER_2, SEC_LOCKDOWN_1, 1, 3)
296 FIELD(CSU_TAMPER_2, SEC_LOCKDOWN_0, 1, 2)
297 FIELD(CSU_TAMPER_2, SYS_RESET, 1, 1)
298 FIELD(CSU_TAMPER_2, SYS_INTERRUPT, 1, 0)
299REG32(CSU_TAMPER_3, 0x5010)
300 FIELD(CSU_TAMPER_3, BBRAM_ERASE, 1, 5)
301 FIELD(CSU_TAMPER_3, SEC_LOCKDOWN_1, 1, 3)
302 FIELD(CSU_TAMPER_3, SEC_LOCKDOWN_0, 1, 2)
303 FIELD(CSU_TAMPER_3, SYS_RESET, 1, 1)
304 FIELD(CSU_TAMPER_3, SYS_INTERRUPT, 1, 0)
305REG32(CSU_TAMPER_4, 0x5014)
306 FIELD(CSU_TAMPER_4, BBRAM_ERASE, 1, 5)
307 FIELD(CSU_TAMPER_4, SEC_LOCKDOWN_1, 1, 3)
308 FIELD(CSU_TAMPER_4, SEC_LOCKDOWN_0, 1, 2)
309 FIELD(CSU_TAMPER_4, SYS_RESET, 1, 1)
310 FIELD(CSU_TAMPER_4, SYS_INTERRUPT, 1, 0)
311REG32(CSU_TAMPER_5, 0x5018)
312 FIELD(CSU_TAMPER_5, BBRAM_ERASE, 1, 5)
313 FIELD(CSU_TAMPER_5, SEC_LOCKDOWN_1, 1, 3)
314 FIELD(CSU_TAMPER_5, SEC_LOCKDOWN_0, 1, 2)
315 FIELD(CSU_TAMPER_5, SYS_RESET, 1, 1)
316 FIELD(CSU_TAMPER_5, SYS_INTERRUPT, 1, 0)
317REG32(CSU_TAMPER_6, 0x501C)
318 FIELD(CSU_TAMPER_6, BBRAM_ERASE, 1, 5)
319 FIELD(CSU_TAMPER_6, SEC_LOCKDOWN_1, 1, 3)
320 FIELD(CSU_TAMPER_6, SEC_LOCKDOWN_0, 1, 2)
321 FIELD(CSU_TAMPER_6, SYS_RESET, 1, 1)
322 FIELD(CSU_TAMPER_6, SYS_INTERRUPT, 1, 0)
323REG32(CSU_TAMPER_7, 0x5020)
324 FIELD(CSU_TAMPER_7, BBRAM_ERASE, 1, 5)
325 FIELD(CSU_TAMPER_7, SEC_LOCKDOWN_1, 1, 3)
326 FIELD(CSU_TAMPER_7, SEC_LOCKDOWN_0, 1, 2)
327 FIELD(CSU_TAMPER_7, SYS_RESET, 1, 1)
328 FIELD(CSU_TAMPER_7, SYS_INTERRUPT, 1, 0)
329REG32(CSU_TAMPER_8, 0x5024)
330 FIELD(CSU_TAMPER_8, BBRAM_ERASE, 1, 5)
331 FIELD(CSU_TAMPER_8, SEC_LOCKDOWN_1, 1, 3)
332 FIELD(CSU_TAMPER_8, SEC_LOCKDOWN_0, 1, 2)
333 FIELD(CSU_TAMPER_8, SYS_RESET, 1, 1)
334 FIELD(CSU_TAMPER_8, SYS_INTERRUPT, 1, 0)
335REG32(CSU_TAMPER_9, 0x5028)
336 FIELD(CSU_TAMPER_9, BBRAM_ERASE, 1, 5)
337 FIELD(CSU_TAMPER_9, SEC_LOCKDOWN_1, 1, 3)
338 FIELD(CSU_TAMPER_9, SEC_LOCKDOWN_0, 1, 2)
339 FIELD(CSU_TAMPER_9, SYS_RESET, 1, 1)
340 FIELD(CSU_TAMPER_9, SYS_INTERRUPT, 1, 0)
341REG32(CSU_TAMPER_10, 0x502C)
342 FIELD(CSU_TAMPER_10, BBRAM_ERASE, 1, 5)
343 FIELD(CSU_TAMPER_10, SEC_LOCKDOWN_1, 1, 3)
344 FIELD(CSU_TAMPER_10, SEC_LOCKDOWN_0, 1, 2)
345 FIELD(CSU_TAMPER_10, SYS_RESET, 1, 1)
346 FIELD(CSU_TAMPER_10, SYS_INTERRUPT, 1, 0)
347REG32(CSU_TAMPER_11, 0x5030)
348 FIELD(CSU_TAMPER_11, BBRAM_ERASE, 1, 5)
349 FIELD(CSU_TAMPER_11, SEC_LOCKDOWN_1, 1, 3)
350 FIELD(CSU_TAMPER_11, SEC_LOCKDOWN_0, 1, 2)
351 FIELD(CSU_TAMPER_11, SYS_RESET, 1, 1)
352 FIELD(CSU_TAMPER_11, SYS_INTERRUPT, 1, 0)
353REG32(CSU_TAMPER_12, 0x5034)
354 FIELD(CSU_TAMPER_12, BBRAM_ERASE, 1, 5)
355 FIELD(CSU_TAMPER_12, SEC_LOCKDOWN_1, 1, 3)
356 FIELD(CSU_TAMPER_12, SEC_LOCKDOWN_0, 1, 2)
357 FIELD(CSU_TAMPER_12, SYS_RESET, 1, 1)
358 FIELD(CSU_TAMPER_12, SYS_INTERRUPT, 1, 0)
359
360#define R_MAX (R_CSU_TAMPER_12 + 1)
361
362typedef struct CSU {
363 SysBusDevice parent_obj;
364 MemoryRegion iomem;
365
366 qemu_irq irq_csu;
367
368 uint32_t regs[R_MAX];
369 RegisterInfo regs_info[R_MAX];
370} CSU;
371
372static void csu_update_irq(CSU *s)
373{
374 bool pending = s->regs[R_CSU_ISR] & ~s->regs[R_CSU_IMR];
375 qemu_set_irq(s->irq_csu, pending);
376}
377
378static void csu_isr_postw(RegisterInfo *reg, uint64_t val64)
379{
380 CSU *s = XILINX_CSU_CORE(reg->opaque);
381 csu_update_irq(s);
382}
383
384static uint64_t int_enable_pre_write(RegisterInfo *reg, uint64_t val64)
385{
386 CSU *s = XILINX_CSU_CORE(reg->opaque);
387 uint32_t val = val64;
388
389 s->regs[R_CSU_IMR] &= ~val;
390 csu_update_irq(s);
391 return 0;
392}
393
394static uint64_t int_disable_pre_write(RegisterInfo *reg, uint64_t val64)
395{
396 CSU *s = XILINX_CSU_CORE(reg->opaque);
397 uint32_t val = val64;
398
399 s->regs[R_CSU_IMR] |= val;
400 csu_update_irq(s);
401 return 0;
402}
403
404static const RegisterAccessInfo csu_core_regs_info[] = {
405 { .name = "CSU_STATUS", .decode.addr = A_CSU_STATUS,
406 .ro = 0xffffffff,
407 },{ .name = "CSU_CTRL", .decode.addr = A_CSU_CTRL,
408 .rsvd = 0xe,
409 },{ .name = "CSU_SSS_CFG", .decode.addr = A_CSU_SSS_CFG,
410 },{ .name = "CSU_DMA_RESET", .decode.addr = A_CSU_DMA_RESET,
411 },{ .name = "CSU_MULTI_BOOT", .decode.addr = A_CSU_MULTI_BOOT,
412 },{ .name = "CSU_TAMPER_TRIG", .decode.addr = A_CSU_TAMPER_TRIG,
413 },{ .name = "CSU_FT_STATUS", .decode.addr = A_CSU_FT_STATUS,
414 .rsvd = 0x300030,
415 .ro = 0xffffffff,
416 },{ .name = "Interrupt Status", .decode.addr = A_CSU_ISR,
417 .w1c = 0xffffffff,
418 .post_write = csu_isr_postw,
419 },{ .name = "Interrupt Mask", .decode.addr = A_CSU_IMR,
420 .reset = 0xffffffff,
421 .ro = 0xffffffff,
422 },{ .name = "Interrupt Enable", .decode.addr = A_CSU_IER,
423 .pre_write = int_enable_pre_write,
424 },{ .name = "Interrupt Disable", .decode.addr = A_CSU_IDR,
425 .pre_write = int_disable_pre_write,
426 },{ .name = "JTAG_CHAIN_STATUS", .decode.addr = A_JTAG_CHAIN_STATUS,
427 .ro = 0x3,
428 },{ .name = "JTAG_SEC", .decode.addr = A_JTAG_SEC,
429 },{ .name = "JTAG_DAP_CFG", .decode.addr = A_JTAG_DAP_CFG,
430 },{ .name = "IDCODE", .decode.addr = A_IDCODE,
431 .ro = 0xffffffff, .reset = QEMU_IDCODE,
432 },{ .name = "VERSION", .decode.addr = A_VERSION,
433 .ro = 0xfffff,
434 .reset = XFSBL_PLATFORM_QEMU,
435 },
436#define P(n) \
437 { .name = "CSU_ROM_DIGEST_" #n, \
438 .decode.addr = A_CSU_ROM_DIGEST_0 + n * 4, \
439 .reset = 0xffffffff, \
440 .ro = 0xffffffff, },
441 P(0) P(1) P(2) P(3) P(4) P(5) P(6) P(7) P(8) P(9) P(10) P(11)
442#undef P
443 { .name = "AES_STATUS", .decode.addr = A_AES_STATUS,
444 .reset = 0xf00,
445 .rsvd = 0xc0,
446 .ro = 0xfff,
447 },{ .name = "AES_KEY_SRC", .decode.addr = A_AES_KEY_SRC,
448 },{ .name = "AES_KEY_LOAD", .decode.addr = A_AES_KEY_LOAD,
449 },{ .name = "AES_START_MSG", .decode.addr = A_AES_START_MSG,
450 },{ .name = "AES_RESET", .decode.addr = A_AES_RESET,
451 },{ .name = "AES_KEY_CLEAR", .decode.addr = A_AES_KEY_CLEAR,
452 },{ .name = "AES_KUP_WR", .decode.addr = A_AES_KUP_WR,
453 },{ .name = "AES_KUP_0", .decode.addr = A_AES_KUP_0,
454 },{ .name = "AES_KUP_1", .decode.addr = A_AES_KUP_1,
455 },{ .name = "AES_KUP_2", .decode.addr = A_AES_KUP_2,
456 },{ .name = "AES_KUP_3", .decode.addr = A_AES_KUP_3,
457 },{ .name = "AES_KUP_4", .decode.addr = A_AES_KUP_4,
458 },{ .name = "AES_KUP_5", .decode.addr = A_AES_KUP_5,
459 },{ .name = "AES_KUP_6", .decode.addr = A_AES_KUP_6,
460 },{ .name = "AES_KUP_7", .decode.addr = A_AES_KUP_7,
461 },{ .name = "AES_IV_0", .decode.addr = A_AES_IV_0,
462 .ro = 0xffffffff,
463 },{ .name = "AES_IV_1", .decode.addr = A_AES_IV_1,
464 .ro = 0xffffffff,
465 },{ .name = "AES_IV_2", .decode.addr = A_AES_IV_2,
466 .ro = 0xffffffff,
467 },{ .name = "AES_IV_3", .decode.addr = A_AES_IV_3,
468 .ro = 0xffffffff,
469 },{ .name = "SHA_START", .decode.addr = A_SHA_START,
470 },{ .name = "SHA_RESET", .decode.addr = A_SHA_RESET,
471 },{ .name = "SHA_DONE", .decode.addr = A_SHA_DONE,
472 .ro = 0x1,
473 },{ .name = "SHA_DIGEST_0", .decode.addr = A_SHA_DIGEST_0,
474 .ro = 0xffffffff,
475 },{ .name = "SHA_DIGEST_1", .decode.addr = A_SHA_DIGEST_1,
476 .ro = 0xffffffff,
477 },{ .name = "SHA_DIGEST_2", .decode.addr = A_SHA_DIGEST_2,
478 .ro = 0xffffffff,
479 },{ .name = "SHA_DIGEST_3", .decode.addr = A_SHA_DIGEST_3,
480 .ro = 0xffffffff,
481 },{ .name = "SHA_DIGEST_4", .decode.addr = A_SHA_DIGEST_4,
482 .ro = 0xffffffff,
483 },{ .name = "SHA_DIGEST_5", .decode.addr = A_SHA_DIGEST_5,
484 .ro = 0xffffffff,
485 },{ .name = "SHA_DIGEST_6", .decode.addr = A_SHA_DIGEST_6,
486 .ro = 0xffffffff,
487 },{ .name = "SHA_DIGEST_7", .decode.addr = A_SHA_DIGEST_7,
488 .ro = 0xffffffff,
489 },{ .name = "SHA_DIGEST_8", .decode.addr = A_SHA_DIGEST_8,
490 .ro = 0xffffffff,
491 },{ .name = "SHA_DIGEST_9", .decode.addr = A_SHA_DIGEST_9,
492 .ro = 0xffffffff,
493 },{ .name = "SHA_DIGEST_10", .decode.addr = A_SHA_DIGEST_10,
494 .ro = 0xffffffff,
495 },{ .name = "SHA_DIGEST_11", .decode.addr = A_SHA_DIGEST_11,
496 .ro = 0xffffffff,
497 },{ .name = "PCAP_PROG", .decode.addr = A_PCAP_PROG,
498 },{ .name = "PCAP_RDWR", .decode.addr = A_PCAP_RDWR,
499 },{ .name = "PCAP_CTRL", .decode.addr = A_PCAP_CTRL,
500 .reset = 0x1,
501 },{ .name = "PCAP_RESET", .decode.addr = A_PCAP_RESET,
502 },{ .name = "PCAP_STATUS", .decode.addr = A_PCAP_STATUS,
503 .reset = 0x3,
504 .rsvd = 0x1fffc000,
505 .ro = 0xffffffff,
506 },{ .name = "TAMPER_STATUS", .decode.addr = A_TAMPER_STATUS,
507 .w1c = 0x3fff,
508 },
509#define P(n) \
510 { .name = "CSU_TAMPER_" #n, .decode.addr = A_CSU_TAMPER_0 + n * 4 \
511 },
512 P(0) P(1) P(2) P(3) P(4) P(5) P(6) P(7) P(8) P(9) P(10) P(11) P(12)
513#undef P
514};
515
516static const MemoryRegionOps csu_core_ops = {
517 .read = register_read_memory_le,
518 .write = register_write_memory_le,
519 .endianness = DEVICE_LITTLE_ENDIAN,
520 .valid = {
521 .min_access_size = 4,
522 .max_access_size = 4,
523 }
524};
525
526static void csu_core_reset(DeviceState *dev)
527{
528 CSU *s = XILINX_CSU_CORE(dev);
529 int i;
530
531 for (i = 0; i < R_MAX; ++i) {
532 register_reset(&s->regs_info[i]);
533 }
534
535 csu_update_irq(s);
536}
537
538
539static void csu_core_realize(DeviceState *dev, Error **errp)
540{
541 CSU *s = XILINX_CSU_CORE(dev);
542 const char *prefix = object_get_canonical_path(OBJECT(dev));
543 int i;
544
545 for (i = 0; i < ARRAY_SIZE(csu_core_regs_info); ++i) {
546 RegisterInfo *r = &s->regs_info[i];
547
548 *r = (RegisterInfo) {
549 .data = (uint8_t *)&s->regs[
550 csu_core_regs_info[i].decode.addr/4],
551 .data_size = sizeof(uint32_t),
552 .access = &csu_core_regs_info[i],
553 .debug = XILINX_CSU_CORE_ERR_DEBUG,
554 .prefix = prefix,
555 .opaque = s,
556 };
557 memory_region_init_io(&r->mem, OBJECT(dev), &csu_core_ops, r,
558 r->access->name, 4);
559 memory_region_add_subregion(&s->iomem, r->access->decode.addr, &r->mem);
560 }
561 return;
562}
563
564static void csu_core_init(Object *obj)
565{
566 CSU *s = XILINX_CSU_CORE(obj);
567
568 memory_region_init(&s->iomem, obj, TYPE_XILINX_CSU_CORE, R_MAX * 4);
569 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
570 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_csu);
571}
572
573static const VMStateDescription vmstate_csu_core = {
574 .name = TYPE_XILINX_CSU_CORE,
575 .version_id = 1,
576 .minimum_version_id = 1,
577 .minimum_version_id_old = 1,
578 .fields = (VMStateField[]) {
579 VMSTATE_UINT32_ARRAY(regs, CSU, R_MAX),
580 VMSTATE_END_OF_LIST(),
581 }
582};
583
584static void csu_core_class_init(ObjectClass *klass, void *data)
585{
586 DeviceClass *dc = DEVICE_CLASS(klass);
587
588 dc->reset = csu_core_reset;
589 dc->realize = csu_core_realize;
590 dc->vmsd = &vmstate_csu_core;
591}
592
593static const TypeInfo csu_core_info = {
594 .name = TYPE_XILINX_CSU_CORE,
595 .parent = TYPE_SYS_BUS_DEVICE,
596 .instance_size = sizeof(CSU),
597 .class_init = csu_core_class_init,
598 .instance_init = csu_core_init,
599};
600
601static void csu_core_register_types(void)
602{
603 type_register_static(&csu_core_info);
604}
605
606type_init(csu_core_register_types)
607
