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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "hw/sysbus.h"
23
24#include "hw/misc/mips_cpc.h"
25
26static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
27{
28 return (1ULL << cpc->num_vp) - 1;
29}
30
31static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
32{
33 CPUState *cs = first_cpu;
34
35 CPU_FOREACH(cs) {
36 uint64_t i = 1ULL << cs->cpu_index;
37 if (i & vp_run & ~cpc->vp_running) {
38 cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
39 cpc->vp_running |= i;
40 }
41 }
42}
43
44static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
45{
46 CPUState *cs = first_cpu;
47
48 CPU_FOREACH(cs) {
49 uint64_t i = 1ULL << cs->cpu_index;
50 if (i & vp_stop & cpc->vp_running) {
51 cs->halted = 1;
52 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
53 cpc->vp_running &= ~i;
54 }
55 }
56}
57
58static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
59 unsigned size)
60{
61 MIPSCPCState *s = opaque;
62
63 switch (offset) {
64 case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
65 case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
66 cpc_run_vp(s, data & cpc_vp_run_mask(s));
67 break;
68 case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
69 case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
70 cpc_stop_vp(s, data & cpc_vp_run_mask(s));
71 break;
72 default:
73 qemu_log_mask(LOG_UNIMP,
74 "%s: Bad offset 0x%x\n", __func__, (int)offset);
75 break;
76 }
77
78 return;
79}
80
81static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
82{
83 MIPSCPCState *s = opaque;
84
85 switch (offset) {
86 case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
87 case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
88 return s->vp_running;
89 default:
90 qemu_log_mask(LOG_UNIMP,
91 "%s: Bad offset 0x%x\n", __func__, (int)offset);
92 return 0;
93 }
94}
95
96static const MemoryRegionOps cpc_ops = {
97 .read = cpc_read,
98 .write = cpc_write,
99 .endianness = DEVICE_NATIVE_ENDIAN,
100 .impl = {
101 .max_access_size = 8,
102 },
103};
104
105static void mips_cpc_init(Object *obj)
106{
107 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
108 MIPSCPCState *s = MIPS_CPC(obj);
109
110 memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
111 CPC_ADDRSPACE_SZ);
112 sysbus_init_mmio(sbd, &s->mr);
113}
114
115static void mips_cpc_realize(DeviceState *dev, Error **errp)
116{
117 MIPSCPCState *s = MIPS_CPC(dev);
118
119 if (s->vp_start_running > cpc_vp_run_mask(s)) {
120 error_setg(errp,
121 "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
122 s->vp_running, s->num_vp);
123 return;
124 }
125}
126
127static void mips_cpc_reset(DeviceState *dev)
128{
129 MIPSCPCState *s = MIPS_CPC(dev);
130
131
132 s->vp_running = 0;
133
134
135 cpc_run_vp(s, s->vp_start_running);
136}
137
138static const VMStateDescription vmstate_mips_cpc = {
139 .name = "mips-cpc",
140 .version_id = 0,
141 .minimum_version_id = 0,
142 .fields = (VMStateField[]) {
143 VMSTATE_UINT64(vp_running, MIPSCPCState),
144 VMSTATE_END_OF_LIST()
145 },
146};
147
148static Property mips_cpc_properties[] = {
149 DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
150 DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
151 DEFINE_PROP_END_OF_LIST(),
152};
153
154static void mips_cpc_class_init(ObjectClass *klass, void *data)
155{
156 DeviceClass *dc = DEVICE_CLASS(klass);
157
158 dc->realize = mips_cpc_realize;
159 dc->reset = mips_cpc_reset;
160 dc->vmsd = &vmstate_mips_cpc;
161 dc->props = mips_cpc_properties;
162}
163
164static const TypeInfo mips_cpc_info = {
165 .name = TYPE_MIPS_CPC,
166 .parent = TYPE_SYS_BUS_DEVICE,
167 .instance_size = sizeof(MIPSCPCState),
168 .instance_init = mips_cpc_init,
169 .class_init = mips_cpc_class_init,
170};
171
172static void mips_cpc_register_types(void)
173{
174 type_register_static(&mips_cpc_info);
175}
176
177type_init(mips_cpc_register_types)
178