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20#include "qemu/osdep.h"
21#include "qapi/error.h"
22#include "hw/hw.h"
23#include "hw/sysbus.h"
24#include "sysemu/sysemu.h"
25#include "hw/misc/mips_itu.h"
26
27#define ITC_TAG_ADDRSPACE_SZ (ITC_ADDRESSMAP_NUM * 8)
28
29
30#define ITC_STORAGE_ADDRSPACE_SZ 0x1000
31
32#define ITC_FIFO_NUM_MAX 16
33#define ITC_SEMAPH_NUM_MAX 16
34#define ITC_AM1_NUMENTRIES_OFS 20
35
36#define ITC_CELL_PV_MAX_VAL 0xFFFF
37
38#define ITC_CELL_TAG_FIFO_DEPTH 28
39#define ITC_CELL_TAG_FIFO_PTR 18
40#define ITC_CELL_TAG_FIFO 17
41#define ITC_CELL_TAG_T 16
42#define ITC_CELL_TAG_F 1
43#define ITC_CELL_TAG_E 0
44
45#define ITC_AM0_BASE_ADDRESS_MASK 0xFFFFFC00ULL
46#define ITC_AM0_EN_MASK 0x1
47
48#define ITC_AM1_ADDR_MASK_MASK 0x1FC00
49#define ITC_AM1_ENTRY_GRAIN_MASK 0x7
50
51typedef enum ITCView {
52 ITCVIEW_BYPASS = 0,
53 ITCVIEW_CONTROL = 1,
54 ITCVIEW_EF_SYNC = 2,
55 ITCVIEW_EF_TRY = 3,
56 ITCVIEW_PV_SYNC = 4,
57 ITCVIEW_PV_TRY = 5
58} ITCView;
59
60MemoryRegion *mips_itu_get_tag_region(MIPSITUState *itu)
61{
62 return &itu->tag_io;
63}
64
65static uint64_t itc_tag_read(void *opaque, hwaddr addr, unsigned size)
66{
67 MIPSITUState *tag = (MIPSITUState *)opaque;
68 uint64_t index = addr >> 3;
69
70 if (index >= ITC_ADDRESSMAP_NUM) {
71 qemu_log_mask(LOG_GUEST_ERROR, "Read 0x%" PRIx64 "\n", addr);
72 return 0;
73 }
74
75 return tag->ITCAddressMap[index];
76}
77
78static void itc_reconfigure(MIPSITUState *tag)
79{
80 uint64_t *am = &tag->ITCAddressMap[0];
81 MemoryRegion *mr = &tag->storage_io;
82 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK;
83 uint64_t size = (1 << 10) + (am[1] & ITC_AM1_ADDR_MASK_MASK);
84 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0;
85
86 memory_region_transaction_begin();
87 if (!(size & (size - 1))) {
88 memory_region_set_size(mr, size);
89 }
90 memory_region_set_address(mr, address);
91 memory_region_set_enabled(mr, is_enabled);
92 memory_region_transaction_commit();
93}
94
95static void itc_tag_write(void *opaque, hwaddr addr,
96 uint64_t data, unsigned size)
97{
98 MIPSITUState *tag = (MIPSITUState *)opaque;
99 uint64_t *am = &tag->ITCAddressMap[0];
100 uint64_t am_old, mask;
101 uint64_t index = addr >> 3;
102
103 switch (index) {
104 case 0:
105 mask = ITC_AM0_BASE_ADDRESS_MASK | ITC_AM0_EN_MASK;
106 break;
107 case 1:
108 mask = ITC_AM1_ADDR_MASK_MASK | ITC_AM1_ENTRY_GRAIN_MASK;
109 break;
110 default:
111 qemu_log_mask(LOG_GUEST_ERROR, "Bad write 0x%" PRIx64 "\n", addr);
112 return;
113 }
114
115 am_old = am[index];
116 am[index] = (data & mask) | (am_old & ~mask);
117 if (am_old != am[index]) {
118 itc_reconfigure(tag);
119 }
120}
121
122static const MemoryRegionOps itc_tag_ops = {
123 .read = itc_tag_read,
124 .write = itc_tag_write,
125 .impl = {
126 .max_access_size = 8,
127 },
128 .endianness = DEVICE_NATIVE_ENDIAN,
129};
130
131static inline uint32_t get_num_cells(MIPSITUState *s)
132{
133 return s->num_fifo + s->num_semaphores;
134}
135
136static inline ITCView get_itc_view(hwaddr addr)
137{
138 return (addr >> 3) & 0xf;
139}
140
141static inline int get_cell_stride_shift(const MIPSITUState *s)
142{
143
144 return 7 + (s->ITCAddressMap[1] & ITC_AM1_ENTRY_GRAIN_MASK);
145}
146
147static inline ITCStorageCell *get_cell(MIPSITUState *s,
148 hwaddr addr)
149{
150 uint32_t cell_idx = addr >> get_cell_stride_shift(s);
151 uint32_t num_cells = get_num_cells(s);
152
153 if (cell_idx >= num_cells) {
154 cell_idx = num_cells - 1;
155 }
156
157 return &s->cell[cell_idx];
158}
159
160static void wake_blocked_threads(ITCStorageCell *c)
161{
162 CPUState *cs;
163 CPU_FOREACH(cs) {
164 if (cs->halted && (c->blocked_threads & (1ULL << cs->cpu_index))) {
165 cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
166 }
167 }
168 c->blocked_threads = 0;
169}
170
171static void QEMU_NORETURN block_thread_and_exit(ITCStorageCell *c)
172{
173 c->blocked_threads |= 1ULL << current_cpu->cpu_index;
174 cpu_restore_state(current_cpu, current_cpu->mem_io_pc);
175 current_cpu->halted = 1;
176 current_cpu->exception_index = EXCP_HLT;
177 cpu_loop_exit(current_cpu);
178}
179
180
181
182static inline uint64_t view_bypass_read(ITCStorageCell *c)
183{
184 if (c->tag.FIFO) {
185 return c->data[c->fifo_out];
186 } else {
187 return c->data[0];
188 }
189}
190
191static inline void view_bypass_write(ITCStorageCell *c, uint64_t val)
192{
193 if (c->tag.FIFO && (c->tag.FIFOPtr > 0)) {
194 int idx = (c->fifo_out + c->tag.FIFOPtr - 1) % ITC_CELL_DEPTH;
195 c->data[idx] = val;
196 }
197
198
199}
200
201
202
203static inline uint64_t view_control_read(ITCStorageCell *c)
204{
205 return ((uint64_t)c->tag.FIFODepth << ITC_CELL_TAG_FIFO_DEPTH) |
206 (c->tag.FIFOPtr << ITC_CELL_TAG_FIFO_PTR) |
207 (c->tag.FIFO << ITC_CELL_TAG_FIFO) |
208 (c->tag.T << ITC_CELL_TAG_T) |
209 (c->tag.E << ITC_CELL_TAG_E) |
210 (c->tag.F << ITC_CELL_TAG_F);
211}
212
213static inline void view_control_write(ITCStorageCell *c, uint64_t val)
214{
215 c->tag.T = (val >> ITC_CELL_TAG_T) & 1;
216 c->tag.E = (val >> ITC_CELL_TAG_E) & 1;
217 c->tag.F = (val >> ITC_CELL_TAG_F) & 1;
218
219 if (c->tag.E) {
220 c->tag.FIFOPtr = 0;
221 }
222}
223
224
225
226static uint64_t view_ef_common_read(ITCStorageCell *c, bool blocking)
227{
228 uint64_t ret = 0;
229
230 if (!c->tag.FIFO) {
231 return 0;
232 }
233
234 c->tag.F = 0;
235
236 if (blocking && c->tag.E) {
237 block_thread_and_exit(c);
238 }
239
240 if (c->blocked_threads) {
241 wake_blocked_threads(c);
242 }
243
244 if (c->tag.FIFOPtr > 0) {
245 ret = c->data[c->fifo_out];
246 c->fifo_out = (c->fifo_out + 1) % ITC_CELL_DEPTH;
247 c->tag.FIFOPtr--;
248 }
249
250 if (c->tag.FIFOPtr == 0) {
251 c->tag.E = 1;
252 }
253
254 return ret;
255}
256
257static uint64_t view_ef_sync_read(ITCStorageCell *c)
258{
259 return view_ef_common_read(c, true);
260}
261
262static uint64_t view_ef_try_read(ITCStorageCell *c)
263{
264 return view_ef_common_read(c, false);
265}
266
267static inline void view_ef_common_write(ITCStorageCell *c, uint64_t val,
268 bool blocking)
269{
270 if (!c->tag.FIFO) {
271 return;
272 }
273
274 c->tag.E = 0;
275
276 if (blocking && c->tag.F) {
277 block_thread_and_exit(c);
278 }
279
280 if (c->blocked_threads) {
281 wake_blocked_threads(c);
282 }
283
284 if (c->tag.FIFOPtr < ITC_CELL_DEPTH) {
285 int idx = (c->fifo_out + c->tag.FIFOPtr) % ITC_CELL_DEPTH;
286 c->data[idx] = val;
287 c->tag.FIFOPtr++;
288 }
289
290 if (c->tag.FIFOPtr == ITC_CELL_DEPTH) {
291 c->tag.F = 1;
292 }
293}
294
295static void view_ef_sync_write(ITCStorageCell *c, uint64_t val)
296{
297 view_ef_common_write(c, val, true);
298}
299
300static void view_ef_try_write(ITCStorageCell *c, uint64_t val)
301{
302 view_ef_common_write(c, val, false);
303}
304
305
306
307static uint64_t view_pv_common_read(ITCStorageCell *c, bool blocking)
308{
309 uint64_t ret = c->data[0];
310
311 if (c->tag.FIFO) {
312 return 0;
313 }
314
315 if (c->data[0] > 0) {
316 c->data[0]--;
317 } else if (blocking) {
318 block_thread_and_exit(c);
319 }
320
321 return ret;
322}
323
324static uint64_t view_pv_sync_read(ITCStorageCell *c)
325{
326 return view_pv_common_read(c, true);
327}
328
329static uint64_t view_pv_try_read(ITCStorageCell *c)
330{
331 return view_pv_common_read(c, false);
332}
333
334static inline void view_pv_common_write(ITCStorageCell *c)
335{
336 if (c->tag.FIFO) {
337 return;
338 }
339
340 if (c->data[0] < ITC_CELL_PV_MAX_VAL) {
341 c->data[0]++;
342 }
343
344 if (c->blocked_threads) {
345 wake_blocked_threads(c);
346 }
347}
348
349static void view_pv_sync_write(ITCStorageCell *c)
350{
351 view_pv_common_write(c);
352}
353
354static void view_pv_try_write(ITCStorageCell *c)
355{
356 view_pv_common_write(c);
357}
358
359static uint64_t itc_storage_read(void *opaque, hwaddr addr, unsigned size)
360{
361 MIPSITUState *s = (MIPSITUState *)opaque;
362 ITCStorageCell *cell = get_cell(s, addr);
363 ITCView view = get_itc_view(addr);
364 uint64_t ret = -1;
365
366 switch (view) {
367 case ITCVIEW_BYPASS:
368 ret = view_bypass_read(cell);
369 break;
370 case ITCVIEW_CONTROL:
371 ret = view_control_read(cell);
372 break;
373 case ITCVIEW_EF_SYNC:
374 ret = view_ef_sync_read(cell);
375 break;
376 case ITCVIEW_EF_TRY:
377 ret = view_ef_try_read(cell);
378 break;
379 case ITCVIEW_PV_SYNC:
380 ret = view_pv_sync_read(cell);
381 break;
382 case ITCVIEW_PV_TRY:
383 ret = view_pv_try_read(cell);
384 break;
385 default:
386 qemu_log_mask(LOG_GUEST_ERROR,
387 "itc_storage_read: Bad ITC View %d\n", (int)view);
388 break;
389 }
390
391 return ret;
392}
393
394static void itc_storage_write(void *opaque, hwaddr addr, uint64_t data,
395 unsigned size)
396{
397 MIPSITUState *s = (MIPSITUState *)opaque;
398 ITCStorageCell *cell = get_cell(s, addr);
399 ITCView view = get_itc_view(addr);
400
401 switch (view) {
402 case ITCVIEW_BYPASS:
403 view_bypass_write(cell, data);
404 break;
405 case ITCVIEW_CONTROL:
406 view_control_write(cell, data);
407 break;
408 case ITCVIEW_EF_SYNC:
409 view_ef_sync_write(cell, data);
410 break;
411 case ITCVIEW_EF_TRY:
412 view_ef_try_write(cell, data);
413 break;
414 case ITCVIEW_PV_SYNC:
415 view_pv_sync_write(cell);
416 break;
417 case ITCVIEW_PV_TRY:
418 view_pv_try_write(cell);
419 break;
420 default:
421 qemu_log_mask(LOG_GUEST_ERROR,
422 "itc_storage_write: Bad ITC View %d\n", (int)view);
423 break;
424 }
425
426}
427
428static const MemoryRegionOps itc_storage_ops = {
429 .read = itc_storage_read,
430 .write = itc_storage_write,
431 .endianness = DEVICE_NATIVE_ENDIAN,
432};
433
434static void itc_reset_cells(MIPSITUState *s)
435{
436 int i;
437
438 memset(s->cell, 0, get_num_cells(s) * sizeof(s->cell[0]));
439
440 for (i = 0; i < s->num_fifo; i++) {
441 s->cell[i].tag.E = 1;
442 s->cell[i].tag.FIFO = 1;
443 s->cell[i].tag.FIFODepth = ITC_CELL_DEPTH_SHIFT;
444 }
445}
446
447static void mips_itu_init(Object *obj)
448{
449 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
450 MIPSITUState *s = MIPS_ITU(obj);
451
452 memory_region_init_io(&s->storage_io, OBJECT(s), &itc_storage_ops, s,
453 "mips-itc-storage", ITC_STORAGE_ADDRSPACE_SZ);
454 sysbus_init_mmio(sbd, &s->storage_io);
455
456 memory_region_init_io(&s->tag_io, OBJECT(s), &itc_tag_ops, s,
457 "mips-itc-tag", ITC_TAG_ADDRSPACE_SZ);
458}
459
460static void mips_itu_realize(DeviceState *dev, Error **errp)
461{
462 MIPSITUState *s = MIPS_ITU(dev);
463
464 if (s->num_fifo > ITC_FIFO_NUM_MAX) {
465 error_setg(errp, "Exceed maximum number of FIFO cells: %d",
466 s->num_fifo);
467 return;
468 }
469 if (s->num_semaphores > ITC_SEMAPH_NUM_MAX) {
470 error_setg(errp, "Exceed maximum number of Semaphore cells: %d",
471 s->num_semaphores);
472 return;
473 }
474
475 s->cell = g_new(ITCStorageCell, get_num_cells(s));
476}
477
478static void mips_itu_reset(DeviceState *dev)
479{
480 MIPSITUState *s = MIPS_ITU(dev);
481
482 s->ITCAddressMap[0] = 0;
483 s->ITCAddressMap[1] =
484 ((ITC_STORAGE_ADDRSPACE_SZ - 1) & ITC_AM1_ADDR_MASK_MASK) |
485 (get_num_cells(s) << ITC_AM1_NUMENTRIES_OFS);
486 itc_reconfigure(s);
487
488 itc_reset_cells(s);
489}
490
491static Property mips_itu_properties[] = {
492 DEFINE_PROP_INT32("num-fifo", MIPSITUState, num_fifo,
493 ITC_FIFO_NUM_MAX),
494 DEFINE_PROP_INT32("num-semaphores", MIPSITUState, num_semaphores,
495 ITC_SEMAPH_NUM_MAX),
496 DEFINE_PROP_END_OF_LIST(),
497};
498
499static void mips_itu_class_init(ObjectClass *klass, void *data)
500{
501 DeviceClass *dc = DEVICE_CLASS(klass);
502
503 dc->props = mips_itu_properties;
504 dc->realize = mips_itu_realize;
505 dc->reset = mips_itu_reset;
506}
507
508static const TypeInfo mips_itu_info = {
509 .name = TYPE_MIPS_ITU,
510 .parent = TYPE_SYS_BUS_DEVICE,
511 .instance_size = sizeof(MIPSITUState),
512 .instance_init = mips_itu_init,
513 .class_init = mips_itu_class_init,
514};
515
516static void mips_itu_register_types(void)
517{
518 type_register_static(&mips_itu_info);
519}
520
521type_init(mips_itu_register_types)
522
