LXR qemu/hw/misc/stm32f2xx

   1/*
   2 * STM32F2XX SYSCFG
   3 *
   4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#include "qemu/osdep.h"
  26#include "hw/misc/stm32f2xx_syscfg.h"
  27
  28#ifndef STM_SYSCFG_ERR_DEBUG
  29#define STM_SYSCFG_ERR_DEBUG 0
  30#endif
  31
  32#define DB_PRINT_L(lvl, fmt, args...) do { \
  33    if (STM_SYSCFG_ERR_DEBUG >= lvl) { \
  34        qemu_log("%s: " fmt, __func__, ## args); \
  35    } \
  36} while (0);
  37
  38#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
  39
  40static void stm32f2xx_syscfg_reset(DeviceState *dev)
  41{
  42    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(dev);
  43
  44    s->syscfg_memrmp = 0x00000000;
  45    s->syscfg_pmc = 0x00000000;
  46    s->syscfg_exticr1 = 0x00000000;
  47    s->syscfg_exticr2 = 0x00000000;
  48    s->syscfg_exticr3 = 0x00000000;
  49    s->syscfg_exticr4 = 0x00000000;
  50    s->syscfg_cmpcr = 0x00000000;
  51}
  52
  53static uint64_t stm32f2xx_syscfg_read(void *opaque, hwaddr addr,
  54                                     unsigned int size)
  55{
  56    STM32F2XXSyscfgState *s = opaque;
  57
  58    DB_PRINT("0x%"HWADDR_PRIx"\n", addr);
  59
  60    switch (addr) {
  61    case SYSCFG_MEMRMP:
  62        return s->syscfg_memrmp;
  63    case SYSCFG_PMC:
  64        return s->syscfg_pmc;
  65    case SYSCFG_EXTICR1:
  66        return s->syscfg_exticr1;
  67    case SYSCFG_EXTICR2:
  68        return s->syscfg_exticr2;
  69    case SYSCFG_EXTICR3:
  70        return s->syscfg_exticr3;
  71    case SYSCFG_EXTICR4:
  72        return s->syscfg_exticr4;
  73    case SYSCFG_CMPCR:
  74        return s->syscfg_cmpcr;
  75    default:
  76        qemu_log_mask(LOG_GUEST_ERROR,
  77                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
  78        return 0;
  79    }
  80
  81    return 0;
  82}
  83
  84static void stm32f2xx_syscfg_write(void *opaque, hwaddr addr,
  85                       uint64_t val64, unsigned int size)
  86{
  87    STM32F2XXSyscfgState *s = opaque;
  88    uint32_t value = val64;
  89
  90    DB_PRINT("0x%x, 0x%"HWADDR_PRIx"\n", value, addr);
  91
  92    switch (addr) {
  93    case SYSCFG_MEMRMP:
  94        qemu_log_mask(LOG_UNIMP,
  95                      "%s: Changeing the memory mapping isn't supported " \
  96                      "in QEMU\n", __func__);
  97        return;
  98    case SYSCFG_PMC:
  99        qemu_log_mask(LOG_UNIMP,
 100                      "%s: Changeing the memory mapping isn't supported " \
 101                      "in QEMU\n", __func__);
 102        return;
 103    case SYSCFG_EXTICR1:
 104        s->syscfg_exticr1 = (value & 0xFFFF);
 105        return;
 106    case SYSCFG_EXTICR2:
 107        s->syscfg_exticr2 = (value & 0xFFFF);
 108        return;
 109    case SYSCFG_EXTICR3:
 110        s->syscfg_exticr3 = (value & 0xFFFF);
 111        return;
 112    case SYSCFG_EXTICR4:
 113        s->syscfg_exticr4 = (value & 0xFFFF);
 114        return;
 115    case SYSCFG_CMPCR:
 116        s->syscfg_cmpcr = value;
 117        return;
 118    default:
 119        qemu_log_mask(LOG_GUEST_ERROR,
 120                      "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
 121    }
 122}
 123
 124static const MemoryRegionOps stm32f2xx_syscfg_ops = {
 125    .read = stm32f2xx_syscfg_read,
 126    .write = stm32f2xx_syscfg_write,
 127    .endianness = DEVICE_NATIVE_ENDIAN,
 128};
 129
 130static void stm32f2xx_syscfg_init(Object *obj)
 131{
 132    STM32F2XXSyscfgState *s = STM32F2XX_SYSCFG(obj);
 133
 134    sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
 135
 136    memory_region_init_io(&s->mmio, obj, &stm32f2xx_syscfg_ops, s,
 137                          TYPE_STM32F2XX_SYSCFG, 0x400);
 138    sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
 139}
 140
 141static void stm32f2xx_syscfg_class_init(ObjectClass *klass, void *data)
 142{
 143    DeviceClass *dc = DEVICE_CLASS(klass);
 144
 145    dc->reset = stm32f2xx_syscfg_reset;
 146}
 147
 148static const TypeInfo stm32f2xx_syscfg_info = {
 149    .name          = TYPE_STM32F2XX_SYSCFG,
 150    .parent        = TYPE_SYS_BUS_DEVICE,
 151    .instance_size = sizeof(STM32F2XXSyscfgState),
 152    .instance_init = stm32f2xx_syscfg_init,
 153    .class_init    = stm32f2xx_syscfg_class_init,
 154};
 155
 156static void stm32f2xx_syscfg_register_types(void)
 157{
 158    type_register_static(&stm32f2xx_syscfg_info);
 159}
 160
 161type_init(stm32f2xx_syscfg_register_types)
 162