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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "hw/register.h"
30#include "qemu/bitops.h"
31#include "qemu/log.h"
32
33#ifndef XILINX_AMS_ERR_DEBUG
34#define XILINX_AMS_ERR_DEBUG 0
35#endif
36
37#define TYPE_XILINX_AMS "xlnx.zynqmp_ams"
38
39#define XILINX_AMS(obj) \
40 OBJECT_CHECK(AMS, (obj), TYPE_XILINX_AMS)
41
42REG32(MISC_CTRL, 0x0)
43 FIELD(MISC_CTRL, SLVERR_ENABLE, 1, 0)
44REG32(ISR, 0x4)
45 FIELD(ISR, ADDR_DECODE_ERR, 1, 31)
46 FIELD(ISR, PL_OT, 1, 23)
47 FIELD(ISR, PL_ALM_6, 1, 22)
48 FIELD(ISR, PL_ALM_5, 1, 21)
49 FIELD(ISR, PL_ALM_4, 1, 20)
50 FIELD(ISR, PL_ALM_3, 1, 19)
51 FIELD(ISR, PL_ALM_2, 1, 18)
52 FIELD(ISR, PL_ALM_1, 1, 17)
53 FIELD(ISR, PL_ALM_0, 1, 16)
54 FIELD(ISR, EOS_ADC1, 1, 15)
55 FIELD(ISR, EOS_ADC0, 1, 14)
56 FIELD(ISR, EOC_ADC1, 1, 13)
57 FIELD(ISR, EOC_ADC0, 1, 12)
58 FIELD(ISR, PS_SYSMON_OT, 1, 11)
59 FIELD(ISR, PS_OT, 1, 10)
60 FIELD(ISR, PS_ALM_9, 1, 9)
61 FIELD(ISR, PS_ALM_8, 1, 8)
62 FIELD(ISR, PS_ALM_7, 1, 7)
63 FIELD(ISR, PS_ALM_6, 1, 6)
64 FIELD(ISR, PS_ALM_5, 1, 5)
65 FIELD(ISR, PS_ALM_4, 1, 4)
66 FIELD(ISR, PS_ALM_3, 1, 3)
67 FIELD(ISR, PS_ALM_2, 1, 2)
68 FIELD(ISR, PS_ALM_1, 1, 1)
69 FIELD(ISR, PS_ALM_0, 1, 0)
70REG32(IMR, 0x8)
71 FIELD(IMR, ADDR_DECODE_ERR, 1, 31)
72 FIELD(IMR, PL_OT, 1, 23)
73 FIELD(IMR, PL_ALM_6, 1, 22)
74 FIELD(IMR, PL_ALM_5, 1, 21)
75 FIELD(IMR, PL_ALM_4, 1, 20)
76 FIELD(IMR, PL_ALM_3, 1, 19)
77 FIELD(IMR, PL_ALM_2, 1, 18)
78 FIELD(IMR, PL_ALM_1, 1, 17)
79 FIELD(IMR, PL_ALM_0, 1, 16)
80 FIELD(IMR, EOS_ADC1, 1, 15)
81 FIELD(IMR, EOS_ADC0, 1, 14)
82 FIELD(IMR, EOC_ADC1, 1, 13)
83 FIELD(IMR, EOC_ADC0, 1, 12)
84 FIELD(IMR, PS_SYSMON_OT, 1, 11)
85 FIELD(IMR, PS_OT, 1, 10)
86 FIELD(IMR, PS_ALM_9, 1, 9)
87 FIELD(IMR, PS_ALM_8, 1, 8)
88 FIELD(IMR, PS_ALM_7, 1, 7)
89 FIELD(IMR, PS_ALM_6, 1, 6)
90 FIELD(IMR, PS_ALM_5, 1, 5)
91 FIELD(IMR, PS_ALM_4, 1, 4)
92 FIELD(IMR, PS_ALM_3, 1, 3)
93 FIELD(IMR, PS_ALM_2, 1, 2)
94 FIELD(IMR, PS_ALM_1, 1, 1)
95 FIELD(IMR, PS_ALM_0, 1, 0)
96REG32(IER, 0xc)
97 FIELD(IER, ADDR_DECODE_ERR, 1, 31)
98 FIELD(IER, PL_OT, 1, 23)
99 FIELD(IER, PL_ALM_6, 1, 22)
100 FIELD(IER, PL_ALM_5, 1, 21)
101 FIELD(IER, PL_ALM_4, 1, 20)
102 FIELD(IER, PL_ALM_3, 1, 19)
103 FIELD(IER, PL_ALM_2, 1, 18)
104 FIELD(IER, PL_ALM_1, 1, 17)
105 FIELD(IER, PL_ALM_0, 1, 16)
106 FIELD(IER, EOS_ADC1, 1, 15)
107 FIELD(IER, EOS_ADC0, 1, 14)
108 FIELD(IER, EOC_ADC1, 1, 13)
109 FIELD(IER, EOC_ADC0, 1, 12)
110 FIELD(IER, PS_SYSMON_OT, 1, 11)
111 FIELD(IER, PS_OT, 1, 10)
112 FIELD(IER, PS_ALM_9, 1, 9)
113 FIELD(IER, PS_ALM_8, 1, 8)
114 FIELD(IER, PS_ALM_7, 1, 7)
115 FIELD(IER, PS_ALM_6, 1, 6)
116 FIELD(IER, PS_ALM_5, 1, 5)
117 FIELD(IER, PS_ALM_4, 1, 4)
118 FIELD(IER, PS_ALM_3, 1, 3)
119 FIELD(IER, PS_ALM_2, 1, 2)
120 FIELD(IER, PS_ALM_1, 1, 1)
121 FIELD(IER, PS_ALM_0, 1, 0)
122REG32(IDR, 0x10)
123 FIELD(IDR, ADDR_DECODE_ERR, 1, 31)
124 FIELD(IDR, PL_OT, 1, 23)
125 FIELD(IDR, PL_ALM_6, 1, 22)
126 FIELD(IDR, PL_ALM_5, 1, 21)
127 FIELD(IDR, PL_ALM_4, 1, 20)
128 FIELD(IDR, PL_ALM_3, 1, 19)
129 FIELD(IDR, PL_ALM_2, 1, 18)
130 FIELD(IDR, PL_ALM_1, 1, 17)
131 FIELD(IDR, PL_ALM_0, 1, 16)
132 FIELD(IDR, EOS_ADC1, 1, 15)
133 FIELD(IDR, EOS_ADC0, 1, 14)
134 FIELD(IDR, EOC_ADC1, 1, 13)
135 FIELD(IDR, EOC_ADC0, 1, 12)
136 FIELD(IDR, PS_SYSMON_OT, 1, 11)
137 FIELD(IDR, PS_OT, 1, 10)
138 FIELD(IDR, PS_ALM_9, 1, 9)
139 FIELD(IDR, PS_ALM_8, 1, 8)
140 FIELD(IDR, PS_ALM_7, 1, 7)
141 FIELD(IDR, PS_ALM_6, 1, 6)
142 FIELD(IDR, PS_ALM_5, 1, 5)
143 FIELD(IDR, PS_ALM_4, 1, 4)
144 FIELD(IDR, PS_ALM_3, 1, 3)
145 FIELD(IDR, PS_ALM_2, 1, 2)
146 FIELD(IDR, PS_ALM_1, 1, 1)
147 FIELD(IDR, PS_ALM_0, 1, 0)
148REG32(ITR, 0x14)
149 FIELD(ITR, ADDR_DECODE_ERR, 1, 31)
150 FIELD(ITR, PL_OT, 1, 23)
151 FIELD(ITR, PL_ALM_6, 1, 22)
152 FIELD(ITR, PL_ALM_5, 1, 21)
153 FIELD(ITR, PL_ALM_4, 1, 20)
154 FIELD(ITR, PL_ALM_3, 1, 19)
155 FIELD(ITR, PL_ALM_2, 1, 18)
156 FIELD(ITR, PL_ALM_1, 1, 17)
157 FIELD(ITR, PL_ALM_0, 1, 16)
158 FIELD(ITR, EOS_ADC1, 1, 15)
159 FIELD(ITR, EOS_ADC0, 1, 14)
160 FIELD(ITR, EOC_ADC1, 1, 13)
161 FIELD(ITR, EOC_ADC0, 1, 12)
162 FIELD(ITR, PS_SYSMON_OT, 1, 11)
163 FIELD(ITR, PS_OT, 1, 10)
164 FIELD(ITR, PS_ALM_9, 1, 9)
165 FIELD(ITR, PS_ALM_8, 1, 8)
166 FIELD(ITR, PS_ALM_7, 1, 7)
167 FIELD(ITR, PS_ALM_6, 1, 6)
168 FIELD(ITR, PS_ALM_5, 1, 5)
169 FIELD(ITR, PS_ALM_4, 1, 4)
170 FIELD(ITR, PS_ALM_3, 1, 3)
171 FIELD(ITR, PS_ALM_2, 1, 2)
172 FIELD(ITR, PS_ALM_1, 1, 1)
173 FIELD(ITR, PS_ALM_0, 1, 0)
174REG32(PS_SYSMON_CONTROL_STATUS, 0x20)
175 FIELD(PS_SYSMON_CONTROL_STATUS, STARTUP_STATE, 4, 24)
176 FIELD(PS_SYSMON_CONTROL_STATUS, STARTUP_DONE, 1, 16)
177 FIELD(PS_SYSMON_CONTROL_STATUS, AUTO_CONVST, 1, 3)
178 FIELD(PS_SYSMON_CONTROL_STATUS, CONVST, 1, 2)
179 FIELD(PS_SYSMON_CONTROL_STATUS, SYSMON_RESET, 1, 1)
180 FIELD(PS_SYSMON_CONTROL_STATUS, STARTUP_TRIGGER, 1, 0)
181REG32(PL_SYSMON_CONTROL_STATUS, 0x24)
182 FIELD(PL_SYSMON_CONTROL_STATUS, ACCESSIBLE, 1, 0)
183REG32(OSC, 0x28)
184 FIELD(OSC, CTRL, 8, 0)
185REG32(MON_STATUS, 0x30)
186 FIELD(MON_STATUS, JTAG_MODIFIED, 1, 24)
187 FIELD(MON_STATUS, JTAG_LOCKED, 1, 23)
188 FIELD(MON_STATUS, JTAG_BUSY, 1, 22)
189 FIELD(MON_STATUS, BUSY, 1, 21)
190 FIELD(MON_STATUS, CHANNEL, 5, 16)
191 FIELD(MON_STATUS, MON_DATA, 16, 0)
192REG32(TEST_ATTR_A, 0x40)
193 FIELD(TEST_ATTR_A, RSVD, 11, 5)
194 FIELD(TEST_ATTR_A, TEST_CHAR_IO_ENABLE, 1, 4)
195 FIELD(TEST_ATTR_A, TEST_ANALOG_IO_ENABLE, 1, 3)
196 FIELD(TEST_ATTR_A, TEST_SCAN_IO_ENABLE, 1, 2)
197 FIELD(TEST_ATTR_A, TEST_JTAG_IO_ENABLE, 1, 1)
198 FIELD(TEST_ATTR_A, DRP_IO_ENABLE, 1, 0)
199REG32(TEST_ATTR_B, 0x44)
200 FIELD(TEST_ATTR_B, TEST_ATTR_B, 16, 0)
201REG32(TEST_ATTR_C, 0x48)
202 FIELD(TEST_ATTR_C, TEST_ATTR_C, 16, 0)
203REG32(TEST_ATTR_D, 0x4c)
204 FIELD(TEST_ATTR_D, TEST_ATTR_D, 16, 0)
205REG32(TEST_ATTR_E, 0x50)
206 FIELD(TEST_ATTR_E, RSVD, 8, 8)
207 FIELD(TEST_ATTR_E, JTAG_READ_ONLY1, 2, 6)
208 FIELD(TEST_ATTR_E, DRP_TEST_STATUS_BITS, 1, 5)
209 FIELD(TEST_ATTR_E, DRP_NO_CLOCK_SWITCH, 1, 4)
210 FIELD(TEST_ATTR_E, JTAG_READ_ONLY0, 1, 3)
211 FIELD(TEST_ATTR_E, JTAG_DISABLE, 3, 0)
212REG32(ECO_0, 0x60)
213REG32(ECO_1, 0x64)
214
215#define R_MAX (R_ECO_1 + 1)
216
217typedef struct AMS {
218 SysBusDevice parent_obj;
219 MemoryRegion iomem;
220 qemu_irq irq_isr;
221
222 uint32_t regs[R_MAX];
223 RegisterInfo regs_info[R_MAX];
224} AMS;
225
226static const MemoryRegionOps ams_ops = {
227 .read = register_read_memory_le,
228 .write = register_write_memory_le,
229 .endianness = DEVICE_LITTLE_ENDIAN,
230 .valid = {
231 .min_access_size = 4,
232 .max_access_size = 4,
233 },
234};
235
236static void isr_update_irq(AMS *s)
237{
238 bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
239 qemu_set_irq(s->irq_isr, pending);
240}
241
242static void isr_postw(RegisterInfo *reg, uint64_t val64)
243{
244 AMS *s = XILINX_AMS(reg->opaque);
245 isr_update_irq(s);
246}
247
248static uint64_t ier_prew(RegisterInfo *reg, uint64_t val64)
249{
250 AMS *s = XILINX_AMS(reg->opaque);
251 uint32_t val = val64;
252
253 s->regs[R_IMR] &= ~val;
254 isr_update_irq(s);
255 return 0;
256}
257
258static uint64_t idr_prew(RegisterInfo *reg, uint64_t val64)
259{
260 AMS *s = XILINX_AMS(reg->opaque);
261 uint32_t val = val64;
262
263 s->regs[R_IMR] |= val;
264 isr_update_irq(s);
265 return 0;
266}
267
268static uint64_t itr_prew(RegisterInfo *reg, uint64_t val64)
269{
270 AMS *s = XILINX_AMS(reg->opaque);
271 uint32_t val = val64;
272
273 s->regs[R_ISR] |= val;
274 isr_update_irq(s);
275 return 0;
276}
277
278static RegisterAccessInfo ams_regs_info[] = {
279 { .name = "MISC_CTRL", .decode.addr = A_MISC_CTRL,
280 },{ .name = "ISR", .decode.addr = A_ISR,
281 .rsvd = 0x7f000000,
282 .ro = 0x7f000000,
283 .w1c = 0x80ffffffL,
284 .post_write = isr_postw,
285 },{ .name = "IMR", .decode.addr = A_IMR,
286 .reset = 0x81ffffffL,
287 .rsvd = 0x7f000000,
288 .ro = 0xffffffffL,
289 },{ .name = "IER", .decode.addr = A_IER,
290 .rsvd = 0x7f000000,
291 .pre_write = ier_prew,
292 },{ .name = "IDR", .decode.addr = A_IDR,
293 .rsvd = 0x7f000000,
294 .pre_write = idr_prew,
295 },{ .name = "ITR", .decode.addr = A_ITR,
296 .rsvd = 0x7f000000,
297 .pre_write = itr_prew,
298 },{ .name = "PS_SYSMON_CONTROL_STATUS", .decode.addr = A_PS_SYSMON_CONTROL_STATUS,
299 .reset = 0x2,
300 .rsvd = 0xfefff0,
301 .ro = 0xffffff0,
302 },{ .name = "PL_SYSMON_CONTROL_STATUS", .decode.addr = A_PL_SYSMON_CONTROL_STATUS,
303 .ro = 0x1,
304 },{ .name = "OSC", .decode.addr = A_OSC,
305 },{ .name = "MON_STATUS", .decode.addr = A_MON_STATUS,
306 .ro = 0x1ffffff,
307 },{ .name = "TEST_ATTR_A", .decode.addr = A_TEST_ATTR_A,
308 .reset = 0x1,
309 },{ .name = "TEST_ATTR_B", .decode.addr = A_TEST_ATTR_B,
310 },{ .name = "TEST_ATTR_C", .decode.addr = A_TEST_ATTR_C,
311 },{ .name = "TEST_ATTR_D", .decode.addr = A_TEST_ATTR_D,
312 },{ .name = "TEST_ATTR_E", .decode.addr = A_TEST_ATTR_E,
313 },{ .name = "ECO_0", .decode.addr = A_ECO_0,
314 },{ .name = "ECO_1", .decode.addr = A_ECO_1,
315 .reset = 0xffffffffL,
316 }
317};
318
319static void ams_reset(DeviceState *dev)
320{
321 AMS *s = XILINX_AMS(dev);
322 unsigned int i;
323
324 for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
325 register_reset(&s->regs_info[i]);
326 }
327
328 isr_update_irq(s);
329}
330
331static void ams_realize(DeviceState *dev, Error **errp)
332{
333 AMS *s = XILINX_AMS(dev);
334 const char *prefix = object_get_canonical_path(OBJECT(dev));
335 unsigned int i;
336
337 for (i = 0; i < ARRAY_SIZE(ams_regs_info); ++i) {
338 RegisterInfo *r = &s->regs_info[i];
339
340 *r = (RegisterInfo) {
341 .data = (uint8_t *)&s->regs[
342 ams_regs_info[i].decode.addr/4],
343 .data_size = sizeof(uint32_t),
344 .access = &ams_regs_info[i],
345 .debug = XILINX_AMS_ERR_DEBUG,
346 .prefix = prefix,
347 .opaque = s,
348 };
349 memory_region_init_io(&r->mem, OBJECT(dev), &ams_ops, r,
350 r->access->name, 4);
351 memory_region_add_subregion(&s->iomem, r->access->decode.addr, &r->mem);
352 }
353}
354
355static void ams_init(Object *obj)
356{
357 AMS *s = XILINX_AMS(obj);
358 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
359
360 memory_region_init(&s->iomem, obj, TYPE_XILINX_AMS, R_MAX * 4);
361 sysbus_init_mmio(sbd, &s->iomem);
362 sysbus_init_irq(sbd, &s->irq_isr);
363}
364
365static const VMStateDescription vmstate_ams = {
366 .name = TYPE_XILINX_AMS,
367 .version_id = 1,
368 .minimum_version_id = 1,
369 .minimum_version_id_old = 1,
370 .fields = (VMStateField[]) {
371 VMSTATE_UINT32_ARRAY(regs, AMS, R_MAX),
372 VMSTATE_END_OF_LIST(),
373 }
374};
375
376static void ams_class_init(ObjectClass *klass, void *data)
377{
378 DeviceClass *dc = DEVICE_CLASS(klass);
379
380 dc->reset = ams_reset;
381 dc->realize = ams_realize;
382 dc->vmsd = &vmstate_ams;
383}
384
385static const TypeInfo ams_info = {
386 .name = TYPE_XILINX_AMS,
387 .parent = TYPE_SYS_BUS_DEVICE,
388 .instance_size = sizeof(AMS),
389 .class_init = ams_class_init,
390 .instance_init = ams_init,
391};
392
393static void ams_register_types(void)
394{
395 type_register_static(&ams_info);
396}
397
398type_init(ams_register_types)
399
